ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF

JUNG-TSE TSAI

Patent

Atlas literature

Patent

US 10,720,521

ENHANCEMENT MODE GALLIUM NITRIDE BASED TRANSISTOR DEVICE AND MANUFACTURING METHOD THEREOF

JUNG-TSE TSAI

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

process chamber schematic

FIG. 1, the enhancement mode GaN transistor device 1 includes a substrate 11, a buﬀer layer 12, a GaN layer 13, a quantum well structure 14, a dielectric 15, a …

FIG. 2

FIG. 2.

FIG. 3

FIG. 3B.

FIG. 4

FIG. 4, the enhancement mode GaN transistor device 1 includes a substrate 11, a buﬀer layer 12, a GaN layer 13, a quantum well structure 14, a dielectric 15, a …

FIG. 5

FIG. 5.

FIG. 6

FIG. 6B.

FIG. 7

FIG. 7, the enhancement mode GaN transistor device 1 includes a substrate 11, a buﬀer layer 12, a GaN layer 13, a quantum well structure 14, a dielectric 15, a …

FIG. 8

FIG. 8.

FIG. 9

FIG. 9, the enhancement mode GaN transistor device 1 includes a substrate 11, a buﬀer layer 12, a GaN layer 13, a quantum well structure 14, a dielectric 15, a …

FIG. 10

FIG. 10.

FIG. 11

FIG. 11C. [0064] Afterwards, implement metal-organic chemical vapor deposition again to re- grow a ﬁrst barrier layer 19 on the epitaxy stack and the …

FIG. 12

FIG. 12, which is a ﬂow chart of a manufacturing method of the enhancement mode GaN transistor device in accordance with the fourth embodiment of the …

FIG. 13

FIG. 13, the horizontal axis stands for the thickness (which is corresponding to the positions of the ﬁrst barrier layer 19, the GaN layer 13', the second …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

6 independent · 18 dependent

1
IndependentGaNquantum well structurefirst barrier layerenhancement mode GaN transistor
An enhancement mode G aN transistor device, comprising: a quantum well structure [[,]] disposed on an upper surface of [[the]]a G aN layer; a dielectric disposed on the quantum well structure; a gate[[;]] disposed on the dielectric; a source [[,]] disposed on one end of the upper surface of the G aN layer; a drain [[,]] disposed on the other end of the upper surface of the G aN layer; and a ﬁrst barrier layer [[,]] disposed on the upper surface of the G aN layer; wherein the ﬁrst barrier la y er extends to lateral surfaces of the quantum well structure and covers the quantum well structure while the gate and the dielectric are exposed from the ﬁrst barrier layer. Currently amended
1. 2
  Dependent← claim 1GaNquantum well structureenhancement mode GaN transistor
  The enhancement mode G aN transistor device of claim 1, wherein an average lattice constant of the quantum well structure is higher than a lattice constant of the G aN layer. Original
2. 3
  Dependent← claim 1first barrier layerGaNenhancement mode GaN transistor
  The enhancement mode G aN transistor device of claim 1, wherein a material of the ﬁrst barrier layer comprises Al(x) l n(y) G a(1-x-y)N and a lattice constant of the ﬁrst barrier layer is less than a lattice constant of the G aN layer. Original
3. 4
  Dependent← claim 1quantum well structureenhancement mode GaN transistor
  The enhancement mode G aN transistor device of claim 1, wherein the quantum well layer comprises a quantum well layer and two barrier layers, and the uantum well structure is disposed between the barrier layers. Currently amended
4. 9
  Dependent← claim 1quantum well structureenhancement mode GaN transistor
  The enhancement mode GaN transistor device of claim 1, wherein the quantum well structure comprises a plurality of quantum well layers and a plurality of barrier layers, and the quantum well layers and the barrier layers are arranged alternately. Original
5. 15
  Dependent← claim 1enhancement mode GaN transistor
  The enhancement mode GaN transistor device of claim 1, wherein the quantum well structure is substantially a cone, and the gate is disposed on a tip of the cone or a plane surface on a top of the cone. Original
6. 16
  Dependent← claim 1enhancement mode GaN transistor
  The enhancement mode GaN transistor device of claim 1, further comprising a buﬀer layer and a substrate, wherein the GaN layer is disposed on the buﬀer layer and the buﬀer layer is disposed on the substrate. Original
7. 17
  Dependent← claim 1Al(x)In(y)Ga(1-x-y)Nenhancement mode GaN transistor
  The enhancement mode GaN transistor device of claim 1, further comprising a second barrier layer disposed on the ﬁrst barrier layer. Original
14
Independent
Canceled
19
IndependentGaNquantum well structurefirst barrier layerenhancement mode GaN transistor
A method for manufacturing enhancement mode GaN transistor device, comprising: forming an epitaxy stack comprising a GaN layer, a quantum well layer and two barrier layers, wherein the quantum well layer and the barrier layers are disposed on an upper surface of the GaN layer, and the quantum well layer is disposed between the barrier layers; forming a dielectric capping layer on the epitaxy stack; etching the epitaxy stack and the dielectric capping la y er to make the quantum well layer,. [[and]]the barrier layers and the dielectric capping la y er form a quantum well structure on the upper surface of the GaN layer and a dielectric on the quantum well structure; depositing a ﬁrst barrier layer on the upper surface of the GaN layer, wherein the ﬁrst barrier la y er extends to lateral surfaces of the quantum well structure and covers the quantum well structure while the dielectric is exposed from the ﬁrst barrier layer; forming a source on one end of the upper surface of the G aN layer; forming a drain on the other end of the upper surface of the G aN layer; and forming a gate on the dielectric, wherein the gate is exposed from the ﬁrst barrier la y er. Currently amended
1. 20
  Dependent← claim 19Al(x)In(y)Ga(1-x-y)Nenhancement mode GaN transistor
  The method of claim 19, further comprising: forming a second barrier layer on the ﬁrst barrier layer. Original
2. 21
  Dependent← claim 19quantum well structureenhancement mode GaN transistor
  The method of claim 19, wherein a step of forming the epitaxy stack comprising the G aN layer, the quantum well layer and the barrier layers further comprises: forming an antipolarization layer on the quantum well layer and the barrier layers. Original
22
Independent
Canceled
23
Independent
Canceled
24
Independentenhancement mode GaN transistor
The method of claim [[22]] 19, wherein a step of etching the epitaxy stack to make the quantum well layer and the barrier layers form the quantum well structure on the upper surface of the G aN layer further comprises: forming the quantum well structure having a cone shape. Currently amended

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

enhancement mode GaN transistor

gategate

dielectricdielectric

Al(x)In(y)Ga(1-x-y)Nsecond barrier layer

first barrier layerfirst barrier layer

quantum well structurequantum well structure

GaNchannel layer

Materials

Materials described outside the worked examples.

GaN

Channel Layer

quantum well structure

Quantum Well Structure

Process steps

Additional fabrication and treatment steps described in the patent.

Epitaxy And Etch Device Fabrication

Step 1

Process details

steps:forming epitaxy stack comprising GaN layer, quantum well layer and two barrier layers, forming dielectric capping layer on epitaxy stack, etching epitaxy stack and dielectric capping layer to form quantum well structure and dielectric, depositing first barrier layer on upper surface of GaN layer covering lateral surfaces of quantum well structure, forming source on one end of upper surface of GaN layer, forming drain on other end of upper surface of GaN layer, forming gate on dielectric

Materials:GaN

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 1, the enhancement mode GaN transistor device 1 includes a substrate 11, a buﬀer layer 12, a GaN layer 13, a quantum well structure 14, a dielectric 15, a …

Figure references

FIG. 1

GaN

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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