Patent
US 9,269,793METHOD AND SYSTEM FOR A GALLIUM NITRIDE SELF-ALIGNED VERTICAL MESFET
Richard J. Brown, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards et al.
AVOGY, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,269,793Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN 5 epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5 also illustrates the formation of a metallic structure 503 below the GaN substrate 200. The metallic structure 503 can be one or more layers of Ohmic …
FIG. 6 is simplified cross-section diagram illustrating the deposition of three sacrificial layers 601, 602, and 603. The first sacrificial layer 601 includes a …
FIG. 7 is a simplified cross-sectional diagram illustrating the removal at least a portion 20 of third sacrificial layer 603 and second sacrificial layer 602 to …
FIG. 8. An outside angle 804 of greater than 90 0 can facilitate formation of subsequent layers and result in improved performance by enabling better 25 …
FIG. 9. The first hardmask 701 is used to define the second hardmask 801, which, in turn, is used to define the channel 5 region 802. The first hardmask 701 is …
FIG. 10, a lift-off and subsequent etch process is used to remove structure 701 and 702 to expose the metallic structure 501 and source region 502 (e.g., …
FIG. 11 illustrates the formation of dielectric layer 1101 and subsequent contact via 10 opening 1102 on top of the source metal structure 501 (for purposes of …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 13 is a simplified flowchart illustrating a method of fabricating a vertical MESFET with a self-aligned gate region according to an embodiment of the …
FIG. 14 is a simplified flowchart illustrating a method of fabricating a controlled switching device according to an embodiment of the present invention. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical metal-semiconductor field- effect transistor (MESFET), the method comprising: providing a gallium nitride (GaN) substrate; forming a first n-type GaN epitaxial layer coupled to the GaN substrate, a second n-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer, and a third n-type GaN epitaxial layer coupled to the second n-type GaN epitaxial layer; forming a metallic contact electrically coupled to the third n-type GaN epitaxial layer; removing at least a portion of the third n-type GaN epitaxial layer to form a source region; forming a plurality of sacrificial layers coupled to the second n-type GaN epitaxial layer; patterning the plurality of sacrificial layers to provide an etch mask coupled to the second n-type GaN epitaxial layer; forming a self-aligned channel region; and forming one or more Schottky metal structures coupled to the self-aligned channel region.
The method of claim 1 wherein the one or more Schottky metal structures are also self-aligned.
The method of claim 1 wherein the first n-type GaN epitaxial layer is characterized by a first dopant concentration; the second n-type GaN epitaxial layer is characterized by a second dopant concentration; and Page 2 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of the third n-type GaN epitaxial layer is characterized by a third dopant concentration greater than the first dopant concentration and the second dopant concentration.
The method of claim 1 wherein the Schottky metal structure comprises at least one of nickel, platinum, palladium, or gold.
The method of claim 1 wherein forming the Schottky metal structure comprises using a sacrificial mask in a liftoff process.
The method of claim 1 further comprising: forming a second metallic structure electrically coupled to the GaN substrate; and forming a third metallic structure electrically coupled to the third n-type GaN epitaxial layer.
The method of claim 1 wherein a thickness of the first n-type GaN epitaxial layer is between about 1 m and about 100 m.
The method of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration varies as a function of thickness.
A method for fabricating a controlled switching device, the method comprising: providing a I II -nitride substrate; forming a plurality of I II -nitride epitaxial layers coupled to the I II -nitride substrate; Page 3 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of forming a source contact coupled to one of the plurality of I II-nitride epitaxial layers; patterning the one of the plurality of I II -nitride epitaxial layers to form a source region; forming a first sacrificial layer, a second sacrificial layer, and third sacrificial layer, wherein the first sacrificial layer is coupled to another of the plurality of I II -nitride epitaxial layers; patterning the third sacrificial layer to form a hardmask; patterning the second sacrificial layer; patterning the first sacrificial layer, using the hardmask, to form a second hardmask; patterning the another of the plurality of I II -nitride epitaxial layers, using the second hardmask, to form a channel region; and performing a metal lift-off process, using the hardmask, to form gate contacts.
The method of claim 10 f u rther comprising forming an interlevel dielectric layer coupled to the gate contacts and the source contact.
The method of claim 10 wherein the first sacrificial layer and the third sacrificial layer comprise at least one of an oxide or a nitride.
The method of claim 10 wherein the second sacrificial layer comprises at least one of a metallic material or a material characterized by etch selectivity between sacrificial layers.
The method of claim 10 wherein pa t terning the second sacrificial layer comprises forming a masking element having a lateral width less than a lateral width of at least the first hardmask or the second hardmask.
The method of claim 10 wherein the gate contacts comprise a Schottky metal layer coupled to the another of the plurality of I II -nitride epitaxial layers. Page 4 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of
The method of claim 10 further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 10 wherein forming the sacrificial mask in a liftoff process.
The method of claim 10 wherein a thickness about 1 m and about 100 pm.
The method of claim 10 wherein at least one dopant concentration, or the third dopant concentration Page 5 of 7 Schottky metal layer comprises using a of the first III- nitride epitaxial layer is between is between about 3 p m and 20 pm. of the first dopant concentration, the second is non-uniform as a function of thickness.
Layer stacks claimed or described, ordered top of device to substrate.
vertical metal-semiconductor field-effect transistor (MESFET)
controlled switching device (vertical III-nitride MESFET)
Materials described outside the worked examples.
gallium nitride substrate
GaN
Schottky metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 0.8–2 eV | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,793Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN 5 epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5 also illustrates the formation of a metallic structure 503 below the GaN substrate 200. The metallic structure 503 can be one or more layers of Ohmic …
FIG. 6 is simplified cross-section diagram illustrating the deposition of three sacrificial layers 601, 602, and 603. The first sacrificial layer 601 includes a …
FIG. 7 is a simplified cross-sectional diagram illustrating the removal at least a portion 20 of third sacrificial layer 603 and second sacrificial layer 602 to …
FIG. 8. An outside angle 804 of greater than 90 0 can facilitate formation of subsequent layers and result in improved performance by enabling better 25 …
FIG. 9. The first hardmask 701 is used to define the second hardmask 801, which, in turn, is used to define the channel 5 region 802. The first hardmask 701 is …
FIG. 10, a lift-off and subsequent etch process is used to remove structure 701 and 702 to expose the metallic structure 501 and source region 502 (e.g., …
FIG. 11 illustrates the formation of dielectric layer 1101 and subsequent contact via 10 opening 1102 on top of the source metal structure 501 (for purposes of …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 13 is a simplified flowchart illustrating a method of fabricating a vertical MESFET with a self-aligned gate region according to an embodiment of the …
FIG. 14 is a simplified flowchart illustrating a method of fabricating a controlled switching device according to an embodiment of the present invention. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical metal-semiconductor field- effect transistor (MESFET), the method comprising: providing a gallium nitride (GaN) substrate; forming a first n-type GaN epitaxial layer coupled to the GaN substrate, a second n-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer, and a third n-type GaN epitaxial layer coupled to the second n-type GaN epitaxial layer; forming a metallic contact electrically coupled to the third n-type GaN epitaxial layer; removing at least a portion of the third n-type GaN epitaxial layer to form a source region; forming a plurality of sacrificial layers coupled to the second n-type GaN epitaxial layer; patterning the plurality of sacrificial layers to provide an etch mask coupled to the second n-type GaN epitaxial layer; forming a self-aligned channel region; and forming one or more Schottky metal structures coupled to the self-aligned channel region.
The method of claim 1 wherein the one or more Schottky metal structures are also self-aligned.
The method of claim 1 wherein the first n-type GaN epitaxial layer is characterized by a first dopant concentration; the second n-type GaN epitaxial layer is characterized by a second dopant concentration; and Page 2 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of the third n-type GaN epitaxial layer is characterized by a third dopant concentration greater than the first dopant concentration and the second dopant concentration.
The method of claim 1 wherein the Schottky metal structure comprises at least one of nickel, platinum, palladium, or gold.
The method of claim 1 wherein forming the Schottky metal structure comprises using a sacrificial mask in a liftoff process.
The method of claim 1 further comprising: forming a second metallic structure electrically coupled to the GaN substrate; and forming a third metallic structure electrically coupled to the third n-type GaN epitaxial layer.
The method of claim 1 wherein a thickness of the first n-type GaN epitaxial layer is between about 1 m and about 100 m.
The method of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration varies as a function of thickness.
A method for fabricating a controlled switching device, the method comprising: providing a I II -nitride substrate; forming a plurality of I II -nitride epitaxial layers coupled to the I II -nitride substrate; Page 3 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of forming a source contact coupled to one of the plurality of I II-nitride epitaxial layers; patterning the one of the plurality of I II -nitride epitaxial layers to form a source region; forming a first sacrificial layer, a second sacrificial layer, and third sacrificial layer, wherein the first sacrificial layer is coupled to another of the plurality of I II -nitride epitaxial layers; patterning the third sacrificial layer to form a hardmask; patterning the second sacrificial layer; patterning the first sacrificial layer, using the hardmask, to form a second hardmask; patterning the another of the plurality of I II -nitride epitaxial layers, using the second hardmask, to form a channel region; and performing a metal lift-off process, using the hardmask, to form gate contacts.
The method of claim 10 f u rther comprising forming an interlevel dielectric layer coupled to the gate contacts and the source contact.
The method of claim 10 wherein the first sacrificial layer and the third sacrificial layer comprise at least one of an oxide or a nitride.
The method of claim 10 wherein the second sacrificial layer comprises at least one of a metallic material or a material characterized by etch selectivity between sacrificial layers.
The method of claim 10 wherein pa t terning the second sacrificial layer comprises forming a masking element having a lateral width less than a lateral width of at least the first hardmask or the second hardmask.
The method of claim 10 wherein the gate contacts comprise a Schottky metal layer coupled to the another of the plurality of I II -nitride epitaxial layers. Page 4 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of
The method of claim 10 further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 10 wherein forming the sacrificial mask in a liftoff process.
The method of claim 10 wherein a thickness about 1 m and about 100 pm.
The method of claim 10 wherein at least one dopant concentration, or the third dopant concentration Page 5 of 7 Schottky metal layer comprises using a of the first III- nitride epitaxial layer is between is between about 3 p m and 20 pm. of the first dopant concentration, the second is non-uniform as a function of thickness.
Layer stacks claimed or described, ordered top of device to substrate.
vertical metal-semiconductor field-effect transistor (MESFET)
controlled switching device (vertical III-nitride MESFET)
Materials described outside the worked examples.
gallium nitride substrate
GaN
Schottky metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 0.8–2 eV | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,793Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN 5 epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5 also illustrates the formation of a metallic structure 503 below the GaN substrate 200. The metallic structure 503 can be one or more layers of Ohmic …
FIG. 6 is simplified cross-section diagram illustrating the deposition of three sacrificial layers 601, 602, and 603. The first sacrificial layer 601 includes a …
FIG. 7 is a simplified cross-sectional diagram illustrating the removal at least a portion 20 of third sacrificial layer 603 and second sacrificial layer 602 to …
FIG. 8. An outside angle 804 of greater than 90 0 can facilitate formation of subsequent layers and result in improved performance by enabling better 25 …
FIG. 9. The first hardmask 701 is used to define the second hardmask 801, which, in turn, is used to define the channel 5 region 802. The first hardmask 701 is …
FIG. 10, a lift-off and subsequent etch process is used to remove structure 701 and 702 to expose the metallic structure 501 and source region 502 (e.g., …
FIG. 11 illustrates the formation of dielectric layer 1101 and subsequent contact via 10 opening 1102 on top of the source metal structure 501 (for purposes of …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 13 is a simplified flowchart illustrating a method of fabricating a vertical MESFET with a self-aligned gate region according to an embodiment of the …
FIG. 14 is a simplified flowchart illustrating a method of fabricating a controlled switching device according to an embodiment of the present invention. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical metal-semiconductor field- effect transistor (MESFET), the method comprising: providing a gallium nitride (GaN) substrate; forming a first n-type GaN epitaxial layer coupled to the GaN substrate, a second n-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer, and a third n-type GaN epitaxial layer coupled to the second n-type GaN epitaxial layer; forming a metallic contact electrically coupled to the third n-type GaN epitaxial layer; removing at least a portion of the third n-type GaN epitaxial layer to form a source region; forming a plurality of sacrificial layers coupled to the second n-type GaN epitaxial layer; patterning the plurality of sacrificial layers to provide an etch mask coupled to the second n-type GaN epitaxial layer; forming a self-aligned channel region; and forming one or more Schottky metal structures coupled to the self-aligned channel region.
The method of claim 1 wherein the one or more Schottky metal structures are also self-aligned.
The method of claim 1 wherein the first n-type GaN epitaxial layer is characterized by a first dopant concentration; the second n-type GaN epitaxial layer is characterized by a second dopant concentration; and Page 2 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of the third n-type GaN epitaxial layer is characterized by a third dopant concentration greater than the first dopant concentration and the second dopant concentration.
The method of claim 1 wherein the Schottky metal structure comprises at least one of nickel, platinum, palladium, or gold.
The method of claim 1 wherein forming the Schottky metal structure comprises using a sacrificial mask in a liftoff process.
The method of claim 1 further comprising: forming a second metallic structure electrically coupled to the GaN substrate; and forming a third metallic structure electrically coupled to the third n-type GaN epitaxial layer.
The method of claim 1 wherein a thickness of the first n-type GaN epitaxial layer is between about 1 m and about 100 m.
The method of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration varies as a function of thickness.
A method for fabricating a controlled switching device, the method comprising: providing a I II -nitride substrate; forming a plurality of I II -nitride epitaxial layers coupled to the I II -nitride substrate; Page 3 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of forming a source contact coupled to one of the plurality of I II-nitride epitaxial layers; patterning the one of the plurality of I II -nitride epitaxial layers to form a source region; forming a first sacrificial layer, a second sacrificial layer, and third sacrificial layer, wherein the first sacrificial layer is coupled to another of the plurality of I II -nitride epitaxial layers; patterning the third sacrificial layer to form a hardmask; patterning the second sacrificial layer; patterning the first sacrificial layer, using the hardmask, to form a second hardmask; patterning the another of the plurality of I II -nitride epitaxial layers, using the second hardmask, to form a channel region; and performing a metal lift-off process, using the hardmask, to form gate contacts.
The method of claim 10 f u rther comprising forming an interlevel dielectric layer coupled to the gate contacts and the source contact.
The method of claim 10 wherein the first sacrificial layer and the third sacrificial layer comprise at least one of an oxide or a nitride.
The method of claim 10 wherein the second sacrificial layer comprises at least one of a metallic material or a material characterized by etch selectivity between sacrificial layers.
The method of claim 10 wherein pa t terning the second sacrificial layer comprises forming a masking element having a lateral width less than a lateral width of at least the first hardmask or the second hardmask.
The method of claim 10 wherein the gate contacts comprise a Schottky metal layer coupled to the another of the plurality of I II -nitride epitaxial layers. Page 4 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of
The method of claim 10 further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 10 wherein forming the sacrificial mask in a liftoff process.
The method of claim 10 wherein a thickness about 1 m and about 100 pm.
The method of claim 10 wherein at least one dopant concentration, or the third dopant concentration Page 5 of 7 Schottky metal layer comprises using a of the first III- nitride epitaxial layer is between is between about 3 p m and 20 pm. of the first dopant concentration, the second is non-uniform as a function of thickness.
Layer stacks claimed or described, ordered top of device to substrate.
vertical metal-semiconductor field-effect transistor (MESFET)
controlled switching device (vertical III-nitride MESFET)
Materials described outside the worked examples.
gallium nitride substrate
GaN
Schottky metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 0.8–2 eV | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,269,793Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 3 illustrates the formation of a second GaN epitaxial layer 301 above the first GaN 5 epitaxial layer 201. The second GaN epitaxial layer 301, which …
FIG. 4 illustrates the formation of a third GaN epitaxial layer 401 above the second GaN epitaxial layer 301. The third GaN epitaxial layer 401, which …
FIG. 5 also illustrates the formation of a metallic structure 503 below the GaN substrate 200. The metallic structure 503 can be one or more layers of Ohmic …
FIG. 6 is simplified cross-section diagram illustrating the deposition of three sacrificial layers 601, 602, and 603. The first sacrificial layer 601 includes a …
FIG. 7 is a simplified cross-sectional diagram illustrating the removal at least a portion 20 of third sacrificial layer 603 and second sacrificial layer 602 to …
FIG. 8. An outside angle 804 of greater than 90 0 can facilitate formation of subsequent layers and result in improved performance by enabling better 25 …
FIG. 9. The first hardmask 701 is used to define the second hardmask 801, which, in turn, is used to define the channel 5 region 802. The first hardmask 701 is …
FIG. 10, a lift-off and subsequent etch process is used to remove structure 701 and 702 to expose the metallic structure 501 and source region 502 (e.g., …
FIG. 11 illustrates the formation of dielectric layer 1101 and subsequent contact via 10 opening 1102 on top of the source metal structure 501 (for purposes of …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 13 is a simplified flowchart illustrating a method of fabricating a vertical MESFET with a self-aligned gate region according to an embodiment of the …
FIG. 14 is a simplified flowchart illustrating a method of fabricating a controlled switching device according to an embodiment of the present invention. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a vertical metal-semiconductor field- effect transistor (MESFET), the method comprising: providing a gallium nitride (GaN) substrate; forming a first n-type GaN epitaxial layer coupled to the GaN substrate, a second n-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer, and a third n-type GaN epitaxial layer coupled to the second n-type GaN epitaxial layer; forming a metallic contact electrically coupled to the third n-type GaN epitaxial layer; removing at least a portion of the third n-type GaN epitaxial layer to form a source region; forming a plurality of sacrificial layers coupled to the second n-type GaN epitaxial layer; patterning the plurality of sacrificial layers to provide an etch mask coupled to the second n-type GaN epitaxial layer; forming a self-aligned channel region; and forming one or more Schottky metal structures coupled to the self-aligned channel region.
The method of claim 1 wherein the one or more Schottky metal structures are also self-aligned.
The method of claim 1 wherein the first n-type GaN epitaxial layer is characterized by a first dopant concentration; the second n-type GaN epitaxial layer is characterized by a second dopant concentration; and Page 2 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of the third n-type GaN epitaxial layer is characterized by a third dopant concentration greater than the first dopant concentration and the second dopant concentration.
The method of claim 1 wherein the Schottky metal structure comprises at least one of nickel, platinum, palladium, or gold.
The method of claim 1 wherein forming the Schottky metal structure comprises using a sacrificial mask in a liftoff process.
The method of claim 1 further comprising: forming a second metallic structure electrically coupled to the GaN substrate; and forming a third metallic structure electrically coupled to the third n-type GaN epitaxial layer.
The method of claim 1 wherein a thickness of the first n-type GaN epitaxial layer is between about 1 m and about 100 m.
The method of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration varies as a function of thickness.
A method for fabricating a controlled switching device, the method comprising: providing a I II -nitride substrate; forming a plurality of I II -nitride epitaxial layers coupled to the I II -nitride substrate; Page 3 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of forming a source contact coupled to one of the plurality of I II-nitride epitaxial layers; patterning the one of the plurality of I II -nitride epitaxial layers to form a source region; forming a first sacrificial layer, a second sacrificial layer, and third sacrificial layer, wherein the first sacrificial layer is coupled to another of the plurality of I II -nitride epitaxial layers; patterning the third sacrificial layer to form a hardmask; patterning the second sacrificial layer; patterning the first sacrificial layer, using the hardmask, to form a second hardmask; patterning the another of the plurality of I II -nitride epitaxial layers, using the second hardmask, to form a channel region; and performing a metal lift-off process, using the hardmask, to form gate contacts.
The method of claim 10 f u rther comprising forming an interlevel dielectric layer coupled to the gate contacts and the source contact.
The method of claim 10 wherein the first sacrificial layer and the third sacrificial layer comprise at least one of an oxide or a nitride.
The method of claim 10 wherein the second sacrificial layer comprises at least one of a metallic material or a material characterized by etch selectivity between sacrificial layers.
The method of claim 10 wherein pa t terning the second sacrificial layer comprises forming a masking element having a lateral width less than a lateral width of at least the first hardmask or the second hardmask.
The method of claim 10 wherein the gate contacts comprise a Schottky metal layer coupled to the another of the plurality of I II -nitride epitaxial layers. Page 4 of 7 App l. No. 14/489,761 PATENT Am dt. dated Response to Office Action of
The method of claim 10 further comprising forming a drain contact electrically coupled to the I II -nitride substrate.
The method of claim 10 wherein forming the sacrificial mask in a liftoff process.
The method of claim 10 wherein a thickness about 1 m and about 100 pm.
The method of claim 10 wherein at least one dopant concentration, or the third dopant concentration Page 5 of 7 Schottky metal layer comprises using a of the first III- nitride epitaxial layer is between is between about 3 p m and 20 pm. of the first dopant concentration, the second is non-uniform as a function of thickness.
Layer stacks claimed or described, ordered top of device to substrate.
vertical metal-semiconductor field-effect transistor (MESFET)
controlled switching device (vertical III-nitride MESFET)
Materials described outside the worked examples.
gallium nitride substrate
GaN
Schottky metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A, the substrate is an n-type GaN substrate, but the present invention is not limited to this particular material. In other embodiments, substrates with …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | 0.8–2 eV | — |
Voltage |
Related documents with shared materials, methods, properties, or citations.
III-nitride substrate
III-nitride epitaxial layers
oxide or nitride sacrificial layer
metallic sacrificial layer
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
| — |
III-nitride substrate
III-nitride epitaxial layers
oxide or nitride sacrificial layer
metallic sacrificial layer
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
| — |
III-nitride substrate
III-nitride epitaxial layers
oxide or nitride sacrificial layer
metallic sacrificial layer
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
| — |
III-nitride substrate
III-nitride epitaxial layers
oxide or nitride sacrificial layer
metallic sacrificial layer
FIGS. 2-12 are simplified cross-sectional diagrams illustrating the fabrication of a 25 vertical metal-semiconductor field-effect transistor (MESFET) according to …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
FIG. 12, the MESFET includes a I II -nitride substrate 200 and a drift region coupled to the I II -nitride substrate 25 along a growth direction. The drift …
| — |