Patent
US 10,847,644GALLIUM NITRIDE TRANSISTOR WITH IMPROVED TERMINATION STRUCTURE
Daniel M. Kinzer, Maher J. Hamdan
NAVITAS SEMICONDUCTOR INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,847,644Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer formed over and in contact with a first portion of the P-type layer; and a continuous metal layer made from a uniform material that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in direct contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region. Currently amended
The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. Original
The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer. Original
The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region. Original
The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region. Original
The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. Original
The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride. Original
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer extending across a first region of a top surface of the P-type layer; and a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) abuts a first side surface of the P-type layer and is in direct contact with a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate. Currently amended
The transistor of claim 11 wherein the field plate is a hole injection region field plate. Original
The transistor of claim 11 wherein the metal Original
The transistor of claim 11 further comprising formed along a length of the drain region. Original
The transistor of claim 11 wherein the hole a second hole injection region is formed in the injection region and the gate region. Original
Canceled
The transistor of claim [[13]] 12 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. Currently amended
The transistor of claim 14 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. Original
,,. Canceled layer is in ohmic contact with the P-type layer. a plurality of individual hole injection regions injection region is a first hole injection region and substrate and positioned between the first hole second hole injection region includes a P-type and is not in ohmic contact with the
Layer stacks claimed or described, ordered top of device to substrate.
GaN field-effect transistor with hole injection region and field plate (continuous metal layer)
GaN field-effect transistor with hole injection region and field plate (metal layer, claim 11)
Materials described outside the worked examples.
gallium nitride
GaN
P-type layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,644Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer formed over and in contact with a first portion of the P-type layer; and a continuous metal layer made from a uniform material that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in direct contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region. Currently amended
The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. Original
The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer. Original
The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region. Original
The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region. Original
The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. Original
The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride. Original
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer extending across a first region of a top surface of the P-type layer; and a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) abuts a first side surface of the P-type layer and is in direct contact with a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate. Currently amended
The transistor of claim 11 wherein the field plate is a hole injection region field plate. Original
The transistor of claim 11 wherein the metal Original
The transistor of claim 11 further comprising formed along a length of the drain region. Original
The transistor of claim 11 wherein the hole a second hole injection region is formed in the injection region and the gate region. Original
Canceled
The transistor of claim [[13]] 12 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. Currently amended
The transistor of claim 14 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. Original
,,. Canceled layer is in ohmic contact with the P-type layer. a plurality of individual hole injection regions injection region is a first hole injection region and substrate and positioned between the first hole second hole injection region includes a P-type and is not in ohmic contact with the
Layer stacks claimed or described, ordered top of device to substrate.
GaN field-effect transistor with hole injection region and field plate (continuous metal layer)
GaN field-effect transistor with hole injection region and field plate (metal layer, claim 11)
Materials described outside the worked examples.
gallium nitride
GaN
P-type layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,644Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer formed over and in contact with a first portion of the P-type layer; and a continuous metal layer made from a uniform material that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in direct contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region. Currently amended
The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. Original
The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer. Original
The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region. Original
The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region. Original
The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. Original
The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride. Original
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer extending across a first region of a top surface of the P-type layer; and a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) abuts a first side surface of the P-type layer and is in direct contact with a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate. Currently amended
The transistor of claim 11 wherein the field plate is a hole injection region field plate. Original
The transistor of claim 11 wherein the metal Original
The transistor of claim 11 further comprising formed along a length of the drain region. Original
The transistor of claim 11 wherein the hole a second hole injection region is formed in the injection region and the gate region. Original
Canceled
The transistor of claim [[13]] 12 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. Currently amended
The transistor of claim 14 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. Original
,,. Canceled layer is in ohmic contact with the P-type layer. a plurality of individual hole injection regions injection region is a first hole injection region and substrate and positioned between the first hole second hole injection region includes a P-type and is not in ohmic contact with the
Layer stacks claimed or described, ordered top of device to substrate.
GaN field-effect transistor with hole injection region and field plate (continuous metal layer)
GaN field-effect transistor with hole injection region and field plate (metal layer, claim 11)
Materials described outside the worked examples.
gallium nitride
GaN
P-type layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,847,644Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer formed over and in contact with a first portion of the P-type layer; and a continuous metal layer made from a uniform material that is (1) formed over and in contact with the drain region of the substrate to form a drain electrode, (2) formed over and in direct contact with a second portion of the P-type layer to form a hole injection electrode, and (3) formed over and in contact with a portion of the dielectric layer to form a field plate for the hole injection region. Currently amended
The transistor of claim 1 wherein the continuous metal layer extends across the drain region of the substrate, abuts a first side surface of the P-type layer and extends across a first region of a top surface of the P-type layer. Original
The transistor of claim 1 wherein the continuous metal layer is in ohmic contact with the P-type layer. Original
The transistor of claim 1 further comprising a plurality of individual hole injection regions formed along a length of the drain region. Original
The transistor of claim 1 wherein the hole injection region is a first hole injection region and a second hole injection region is formed in the substrate and positioned between the first hole injection region and the gate region. Original
The transistor of claim 1 wherein the continuous metal layer is formed over approximately one half of a top surface of the P-type layer and the dielectric layer is formed over a remaining portion of the top surface of the P-type layer. Original
The transistor of claim 1 wherein the semiconductor substrate comprises gallium nitride. Original
A transistor comprising: a semiconductor substrate; a source region formed in the substrate and including a source electrode in contact with a portion of the substrate; a drain region formed in the substrate and separated from the source region; a gate region formed in the substrate and including a gate stack in contact with a portion of the substrate, the gate region positioned between the source region and the drain region; a hole injection region formed in the substrate and including a P-type layer in contact with a portion of the substrate, the hole injection region positioned between the gate region and the drain region; a dielectric layer extending across a first region of a top surface of the P-type layer; and a metal layer that (1) extends across a drain region of the substrate to form a drain electrode, (2) abuts a first side surface of the P-type layer and is in direct contact with a second region of the top surface of the P-type layer to form a hole injection electrode, and (3) extends across a portion of the dielectric layer to form a field plate. Currently amended
The transistor of claim 11 wherein the field plate is a hole injection region field plate. Original
The transistor of claim 11 wherein the metal Original
The transistor of claim 11 further comprising formed along a length of the drain region. Original
The transistor of claim 11 wherein the hole a second hole injection region is formed in the injection region and the gate region. Original
Canceled
The transistor of claim [[13]] 12 wherein the dielectric layer extends across a surface of the substrate, abuts a second side surface of the P-type layer and extends across the first region of the top surface of the P-type layer. Currently amended
The transistor of claim 14 wherein the field plate extends across the first region of the dielectric layer and terminates before becoming coplanar with the second side surface of the P-type layer. Original
,,. Canceled layer is in ohmic contact with the P-type layer. a plurality of individual hole injection regions injection region is a first hole injection region and substrate and positioned between the first hole second hole injection region includes a P-type and is not in ohmic contact with the
Layer stacks claimed or described, ordered top of device to substrate.
GaN field-effect transistor with hole injection region and field plate (continuous metal layer)
GaN field-effect transistor with hole injection region and field plate (metal layer, claim 11)
Materials described outside the worked examples.
gallium nitride
GaN
P-type layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a simplified plan view of a GaN-based semiconductor transistor 100 according to an embodiment of the disclosure; [0015]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.5–5 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
dielectric layer
continuous metal layer
AlGaN/GaN heteroepitaxial junction
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
| 0.75–2 µm |
| — |
Thickness | 0.9–1.1 µm | — |
Thickness | 0.125–2 µm | — |
Thickness | 0.2–0.75 µm | — |
dielectric layer
continuous metal layer
AlGaN/GaN heteroepitaxial junction
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
| 0.75–2 µm |
| — |
Thickness | 0.9–1.1 µm | — |
Thickness | 0.125–2 µm | — |
Thickness | 0.2–0.75 µm | — |
dielectric layer
continuous metal layer
AlGaN/GaN heteroepitaxial junction
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
| 0.75–2 µm |
| — |
Thickness | 0.9–1.1 µm | — |
Thickness | 0.125–2 µm | — |
Thickness | 0.2–0.75 µm | — |
dielectric layer
continuous metal layer
AlGaN/GaN heteroepitaxial junction
FIG. 2 illustrates a magnified partial plan view of the active region of the GaN-based semiconductor transistor shown in
FIG. 3 illustrates a partial cross-sectional view across line A-A on the transistor cell illustrated in
FIG. 4 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0018]
FIG. 5 illustrates a partial cross-sectional view across the transistor shown in
FIG. 6 illustrates a simplified plan view of a drain region of a GaN-based transistor according to an embodiment of the disclosure; [0020]
FIG. 7 illustrates a partial cross-sectional view across the transistor shown in
FIG. 8 illustrates a cross-section B-B of the transistor shown in
FIG. 9 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0023]
FIG. 10 illustrates a partial cross-sectional view C-C across the transistor shown in
FIG. 11 illustrates a partial cross-sectional view of a GaN-based transistor according to an embodiment of the disclosure; [0025]
FIG. 12 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0026]
FIG. 13 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0027]
FIG. 14 illustrates a simplified plan view of a GaN-based transistor according to an embodiment of the disclosure; [0028]
FIG. 15 illustrates a partial cross-sectional view of a GaN- based transistor according to an embodiment of the disclosure; and [0029]
FIG. 16 illustrates a plan view of a GaN-based transistor according to an embodiment of the disclosure.
| 0.75–2 µm |
| — |
Thickness | 0.9–1.1 µm | — |
Thickness | 0.125–2 µm | — |
Thickness | 0.2–0.75 µm | — |