Patent
US 10,778,219LEVEL SHIFTING IN A GAN HALF BRIDGE CIRCUIT
Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
NAVITAS SEMICONDUCTOR, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,778,219Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0009]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 1 is a schematic illustration of an embodiment of a receiver circuit. [0059]
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UJ VLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a hi g h side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0029]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the hi gh side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention: [0043]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0044]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of an alternative high side control circuit. [0046]
FIG. 39 is a schematic illustration of a receiver. [0047]
FIG. 40 is a schematic illustration of a level shift circuit. [0048]
FIG. 41 is a schematic illustration of a logic block circuit. [0049]
FIG. 42 is a wavefo i m diagram illustrating waveforms for various signals of a high side control circuit. [0050]
FIG. 43 is a schematic illustration of a receiver circuit. [0051]
FIG. 44 is a schematic illustration of a logic block circuit. [0052]
FIG. 45 is a waveform diagram illustrating waveforms for various si g nals of a hi g h side control circ tu it. [0053]
FIG. 46 is a wavefo r m diagram illustrating waveforms for various signals of a high side control circuit. [0054]
FIG. 47 is a schematic illustration of an embodiment of an alternative high side control circuit. [0055] FIG s. 48A and 48B are schematic illustrations of a …
FIG. 50 is a wavefo r m diagram illustrating waveforms for various signals of the high side control circuit of figure 47. [0058]
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
FIG. 52 is a schematic illustration of an embodiment of a VMID voltage generator. [0060]
FIG. 53 is a schematic illustration of an embodiment of a VMID voltage generator. [0061]
FIG. 54 is a schematic illustration of an embodiment of a VMID voltage generator. [0062]
FIG. 55 is a schematic illustration of a Vdd power supply voltage generator.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A half bridge circuit, comprising: a switch node; a low side power switch configured to selectively conduct current from the switch node according to one or more input signals; a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals; a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node; a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage; a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, wherein the first logic circuit is configured to generate a first logic output voltage, which controls a conductivity of the high side power switch, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the second logic circuit is configured to generate a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The half bridge circuit of claim 1, further comprising a control level shift circuit comprising a level shift transistor, wherein the control level shift circuit is configured to cause the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor, wherein the first logic circuit controls the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The half bridge circuit of claim 1, further comprising: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and wherein the DC voltage is generated by a voltage generator which is not formed on the semiconductor substrate. Currently amended
The half bridge circuit of claim 1, further comprising: a particular voltage generator configured to receive the DC voltage referenced to the switch voltage and to generate the particular power voltage based on the DC voltage. Currently amended
A method of using a GaN half bridge circuit, comprising: a switch node, a low side power switch, a high side power switch, a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node, a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage, a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the method comprises: with the low side power switch, selectively conducting current from the switch node according to one or more input signals; with the high side power switch, selectively conducting current to the switch node according to the one or more input signals; with the first logic circuit, generating a logic output voltage, which controls a conductivity of the high side power switch; and with the second logic circuit, generating a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises a control level shift circuit having a level shift transistor, and wherein the method further comprises: with the control level shift circuit, causing the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor; and with the first logic circuit, controlling a-the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and with a voltage generator which is not formed on the semiconductor substrate, generating the DC voltage. Currently amended
The method of claim 11, wherein the half b ri dge GaN circuit further comprises a particular voltage generator, and wherein the method further comprises, with the particular voltage generator, receiving the DC voltage and generating the particular power voltage based on the DC voltage. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN half bridge circuit
GaN-based enhancement-mode field effect transistor
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 10,778,219Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0009]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 1 is a schematic illustration of an embodiment of a receiver circuit. [0059]
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UJ VLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a hi g h side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0029]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the hi gh side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention: [0043]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0044]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of an alternative high side control circuit. [0046]
FIG. 39 is a schematic illustration of a receiver. [0047]
FIG. 40 is a schematic illustration of a level shift circuit. [0048]
FIG. 41 is a schematic illustration of a logic block circuit. [0049]
FIG. 42 is a wavefo i m diagram illustrating waveforms for various signals of a high side control circuit. [0050]
FIG. 43 is a schematic illustration of a receiver circuit. [0051]
FIG. 44 is a schematic illustration of a logic block circuit. [0052]
FIG. 45 is a waveform diagram illustrating waveforms for various si g nals of a hi g h side control circ tu it. [0053]
FIG. 46 is a wavefo r m diagram illustrating waveforms for various signals of a high side control circuit. [0054]
FIG. 47 is a schematic illustration of an embodiment of an alternative high side control circuit. [0055] FIG s. 48A and 48B are schematic illustrations of a …
FIG. 50 is a wavefo r m diagram illustrating waveforms for various signals of the high side control circuit of figure 47. [0058]
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
FIG. 52 is a schematic illustration of an embodiment of a VMID voltage generator. [0060]
FIG. 53 is a schematic illustration of an embodiment of a VMID voltage generator. [0061]
FIG. 54 is a schematic illustration of an embodiment of a VMID voltage generator. [0062]
FIG. 55 is a schematic illustration of a Vdd power supply voltage generator.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A half bridge circuit, comprising: a switch node; a low side power switch configured to selectively conduct current from the switch node according to one or more input signals; a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals; a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node; a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage; a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, wherein the first logic circuit is configured to generate a first logic output voltage, which controls a conductivity of the high side power switch, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the second logic circuit is configured to generate a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The half bridge circuit of claim 1, further comprising a control level shift circuit comprising a level shift transistor, wherein the control level shift circuit is configured to cause the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor, wherein the first logic circuit controls the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The half bridge circuit of claim 1, further comprising: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and wherein the DC voltage is generated by a voltage generator which is not formed on the semiconductor substrate. Currently amended
The half bridge circuit of claim 1, further comprising: a particular voltage generator configured to receive the DC voltage referenced to the switch voltage and to generate the particular power voltage based on the DC voltage. Currently amended
A method of using a GaN half bridge circuit, comprising: a switch node, a low side power switch, a high side power switch, a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node, a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage, a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the method comprises: with the low side power switch, selectively conducting current from the switch node according to one or more input signals; with the high side power switch, selectively conducting current to the switch node according to the one or more input signals; with the first logic circuit, generating a logic output voltage, which controls a conductivity of the high side power switch; and with the second logic circuit, generating a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises a control level shift circuit having a level shift transistor, and wherein the method further comprises: with the control level shift circuit, causing the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor; and with the first logic circuit, controlling a-the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and with a voltage generator which is not formed on the semiconductor substrate, generating the DC voltage. Currently amended
The method of claim 11, wherein the half b ri dge GaN circuit further comprises a particular voltage generator, and wherein the method further comprises, with the particular voltage generator, receiving the DC voltage and generating the particular power voltage based on the DC voltage. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN half bridge circuit
GaN-based enhancement-mode field effect transistor
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,778,219Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0009]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 1 is a schematic illustration of an embodiment of a receiver circuit. [0059]
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UJ VLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a hi g h side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0029]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the hi gh side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention: [0043]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0044]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of an alternative high side control circuit. [0046]
FIG. 39 is a schematic illustration of a receiver. [0047]
FIG. 40 is a schematic illustration of a level shift circuit. [0048]
FIG. 41 is a schematic illustration of a logic block circuit. [0049]
FIG. 42 is a wavefo i m diagram illustrating waveforms for various signals of a high side control circuit. [0050]
FIG. 43 is a schematic illustration of a receiver circuit. [0051]
FIG. 44 is a schematic illustration of a logic block circuit. [0052]
FIG. 45 is a waveform diagram illustrating waveforms for various si g nals of a hi g h side control circ tu it. [0053]
FIG. 46 is a wavefo r m diagram illustrating waveforms for various signals of a high side control circuit. [0054]
FIG. 47 is a schematic illustration of an embodiment of an alternative high side control circuit. [0055] FIG s. 48A and 48B are schematic illustrations of a …
FIG. 50 is a wavefo r m diagram illustrating waveforms for various signals of the high side control circuit of figure 47. [0058]
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
FIG. 52 is a schematic illustration of an embodiment of a VMID voltage generator. [0060]
FIG. 53 is a schematic illustration of an embodiment of a VMID voltage generator. [0061]
FIG. 54 is a schematic illustration of an embodiment of a VMID voltage generator. [0062]
FIG. 55 is a schematic illustration of a Vdd power supply voltage generator.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A half bridge circuit, comprising: a switch node; a low side power switch configured to selectively conduct current from the switch node according to one or more input signals; a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals; a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node; a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage; a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, wherein the first logic circuit is configured to generate a first logic output voltage, which controls a conductivity of the high side power switch, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the second logic circuit is configured to generate a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The half bridge circuit of claim 1, further comprising a control level shift circuit comprising a level shift transistor, wherein the control level shift circuit is configured to cause the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor, wherein the first logic circuit controls the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The half bridge circuit of claim 1, further comprising: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and wherein the DC voltage is generated by a voltage generator which is not formed on the semiconductor substrate. Currently amended
The half bridge circuit of claim 1, further comprising: a particular voltage generator configured to receive the DC voltage referenced to the switch voltage and to generate the particular power voltage based on the DC voltage. Currently amended
A method of using a GaN half bridge circuit, comprising: a switch node, a low side power switch, a high side power switch, a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node, a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage, a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the method comprises: with the low side power switch, selectively conducting current from the switch node according to one or more input signals; with the high side power switch, selectively conducting current to the switch node according to the one or more input signals; with the first logic circuit, generating a logic output voltage, which controls a conductivity of the high side power switch; and with the second logic circuit, generating a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises a control level shift circuit having a level shift transistor, and wherein the method further comprises: with the control level shift circuit, causing the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor; and with the first logic circuit, controlling a-the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and with a voltage generator which is not formed on the semiconductor substrate, generating the DC voltage. Currently amended
The method of claim 11, wherein the half b ri dge GaN circuit further comprises a particular voltage generator, and wherein the method further comprises, with the particular voltage generator, receiving the DC voltage and generating the particular power voltage based on the DC voltage. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN half bridge circuit
GaN-based enhancement-mode field effect transistor
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,778,219Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0009]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 1 is a schematic illustration of an embodiment of a receiver circuit. [0059]
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UJ VLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a hi g h side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0029]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the hi gh side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0042]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention: [0043]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0044]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of an alternative high side control circuit. [0046]
FIG. 39 is a schematic illustration of a receiver. [0047]
FIG. 40 is a schematic illustration of a level shift circuit. [0048]
FIG. 41 is a schematic illustration of a logic block circuit. [0049]
FIG. 42 is a wavefo i m diagram illustrating waveforms for various signals of a high side control circuit. [0050]
FIG. 43 is a schematic illustration of a receiver circuit. [0051]
FIG. 44 is a schematic illustration of a logic block circuit. [0052]
FIG. 45 is a waveform diagram illustrating waveforms for various si g nals of a hi g h side control circ tu it. [0053]
FIG. 46 is a wavefo r m diagram illustrating waveforms for various signals of a high side control circuit. [0054]
FIG. 47 is a schematic illustration of an embodiment of an alternative high side control circuit. [0055] FIG s. 48A and 48B are schematic illustrations of a …
FIG. 50 is a wavefo r m diagram illustrating waveforms for various signals of the high side control circuit of figure 47. [0058]
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
FIG. 52 is a schematic illustration of an embodiment of a VMID voltage generator. [0060]
FIG. 53 is a schematic illustration of an embodiment of a VMID voltage generator. [0061]
FIG. 54 is a schematic illustration of an embodiment of a VMID voltage generator. [0062]
FIG. 55 is a schematic illustration of a Vdd power supply voltage generator.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A half bridge circuit, comprising: a switch node; a low side power switch configured to selectively conduct current from the switch node according to one or more input signals; a high side power switch configured to selectively conduct current to the switch node according to the one or more input signals; a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node; a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage; a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, wherein the first logic circuit is configured to generate a first logic output voltage, which controls a conductivity of the high side power switch, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the second logic circuit is configured to generate a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The half bridge circuit of claim 1, further comprising a control level shift circuit comprising a level shift transistor, wherein the control level shift circuit is configured to cause the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor, wherein the first logic circuit controls the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The half bridge circuit of claim 1, further comprising: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and wherein the DC voltage is generated by a voltage generator which is not formed on the semiconductor substrate. Currently amended
The half bridge circuit of claim 1, further comprising: a particular voltage generator configured to receive the DC voltage referenced to the switch voltage and to generate the particular power voltage based on the DC voltage. Currently amended
A method of using a GaN half bridge circuit, comprising: a switch node, a low side power switch, a high side power switch, a first power node having a first power voltage, wherein the first power voltage is referenced to a switch voltage at the switch node, a particular power node having a particular power voltage, wherein the particular power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage, a first logic circuit, wherein a negative power terminal of the first logic circuit is connected to the particular power node, and wherein a positive power terminal of the first logic circuit is connected to the first power node, and a second logic circuit, wherein a negative power terminal of the second logic circuit is connected to the switch node, and wherein a positive power terminal of the second logic circuit is connected to the first power node, wherein the method comprises: with the low side power switch, selectively conducting current from the switch node according to one or more input signals; with the high side power switch, selectively conducting current to the switch node according to the one or more input signals; with the first logic circuit, generating a logic output voltage, which controls a conductivity of the high side power switch; and with the second logic circuit, generating a second logic output voltage, which controls the conductivity of the high side power switch. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises a control level shift circuit having a level shift transistor, and wherein the method further comprises: with the control level shift circuit, causing the first logic circuit to cause the high side power switch to be conductive by generating a level shift signal, wherein a temperature dependence of a voltage of the level shift signal is dominated by a temperature dependence of a gate to source threshold voltage of the level shift transistor; and with the first logic circuit, controlling a-the conductivity of the high side power switch based on the level shift signal, wherein the first logic circuit comprises a logic circuit transistor, and wherein the first logic circuit has a logic input threshold having a temperature dependence which is dominated by a temperature dependence of a gate to source threshold of the first logic circuit. Currently amended
The method of claim 11, wherein the half bridge GaN circuit further comprises: a semiconductor substrate, wherein the first logic circuit is integrated on the semiconductor substrate, and with a voltage generator which is not formed on the semiconductor substrate, generating the DC voltage. Currently amended
The method of claim 11, wherein the half b ri dge GaN circuit further comprises a particular voltage generator, and wherein the method further comprises, with the particular voltage generator, receiving the DC voltage and generating the particular power voltage based on the DC voltage. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN half bridge circuit
GaN-based enhancement-mode field effect transistor
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
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AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 51 also includes a schematic illustration of level shift circuit 5190, which includes level shift transistor 5192, which may be similar or identical to …