Patent
US 10,811,951GAN DRIVER CIRCUIT
Santosh Sharma, Daniel Marvin Kinzer
NAVITAS SEMICONDUCTOR, INC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,811,951Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0005]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0025]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0038]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0039]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0040]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit. [0042]
FIG. 39 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit. [0044]
FIG. 41 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 42 is a schematic illustration of an embodiment of a multiplier circuit. [0046]
FIG. 43 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
FIG. 44 is a schematic illustration of an embodiment of a multiplier circuit. [0048]
FIG. 45 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN driver circuit, comprising: an input node configured to receive an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; a low side switch connected to an output node, wherein, in response to the input voltage, the low side switch is configured to selectively connect the output node to a first node at a first voltage; a high side switch connected to the output node, wherein, in response to the input voltage, the high side switch is configured to selectively connect the output node to a second node at a second voltage; and a high side switch driver circuit configured to, in response to the input voltage, selectively cause the high side switch to connect the output node to the second node, wherein the high side switch driver circuit comprises: a pass gate configured to connect the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and a pass gate driver configured to cause the pass gate to be conductive in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, wherein the pass gate comprises a gate node, and wherein the pass gate driver is configured to cause a voltage at the gate node of the pass gate to change in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, further comprising an inverting logic circuit configured to cause the voltage at the first internal node to become greater than the second voltage by at least a threshold voltage of the high side switch in response to the input voltage. Previously presented
The GaN driver circuit of claim I, wherein the pass gate is configured to conduct current from the first internal node to the high side switch until the voltage at the gate of the high side switch is substantially equal to a voltage at the first internal node. Previously presented
A method of operating a GaN driver circuit, the method comprising: with an input node, receiving an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; with a low side switch connected to an output node, in response to the input voltage, selectively connecting the output node to a first node at a first voltage; with a high side switch connected to the output node, in response to the input voltage, selectively connecting the output node to a second node at a second voltage; with a high side switch driver circuit, in response to the input voltage, selectively causing the high side switch to connect the output node to the second node, wherein selectively causing the high side switch to connect the output node to the second node comprises: with a pass gate, connecting the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and with a pass gate driver, causing the pass gate to be conductive in response to the input voltage. Previously presented
The method of claim 18, with the pass gate, conducting current from the first internal node to the high side switch until the voltage at the gate voltage at the first internal node. Previously
The method of claim 18, wherein the pass gate method further comprises, with the pass gate driver, gate to change in response to the input voltage. of the high side switch is substantially equal to a presented comprises a gate node, and wherein the causing a voltage at the gate node of the pass Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
No layer stack recorded.
integrated half bridge power conversion circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,951Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0005]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0025]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0038]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0039]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0040]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit. [0042]
FIG. 39 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit. [0044]
FIG. 41 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 42 is a schematic illustration of an embodiment of a multiplier circuit. [0046]
FIG. 43 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
FIG. 44 is a schematic illustration of an embodiment of a multiplier circuit. [0048]
FIG. 45 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN driver circuit, comprising: an input node configured to receive an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; a low side switch connected to an output node, wherein, in response to the input voltage, the low side switch is configured to selectively connect the output node to a first node at a first voltage; a high side switch connected to the output node, wherein, in response to the input voltage, the high side switch is configured to selectively connect the output node to a second node at a second voltage; and a high side switch driver circuit configured to, in response to the input voltage, selectively cause the high side switch to connect the output node to the second node, wherein the high side switch driver circuit comprises: a pass gate configured to connect the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and a pass gate driver configured to cause the pass gate to be conductive in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, wherein the pass gate comprises a gate node, and wherein the pass gate driver is configured to cause a voltage at the gate node of the pass gate to change in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, further comprising an inverting logic circuit configured to cause the voltage at the first internal node to become greater than the second voltage by at least a threshold voltage of the high side switch in response to the input voltage. Previously presented
The GaN driver circuit of claim I, wherein the pass gate is configured to conduct current from the first internal node to the high side switch until the voltage at the gate of the high side switch is substantially equal to a voltage at the first internal node. Previously presented
A method of operating a GaN driver circuit, the method comprising: with an input node, receiving an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; with a low side switch connected to an output node, in response to the input voltage, selectively connecting the output node to a first node at a first voltage; with a high side switch connected to the output node, in response to the input voltage, selectively connecting the output node to a second node at a second voltage; with a high side switch driver circuit, in response to the input voltage, selectively causing the high side switch to connect the output node to the second node, wherein selectively causing the high side switch to connect the output node to the second node comprises: with a pass gate, connecting the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and with a pass gate driver, causing the pass gate to be conductive in response to the input voltage. Previously presented
The method of claim 18, with the pass gate, conducting current from the first internal node to the high side switch until the voltage at the gate voltage at the first internal node. Previously
The method of claim 18, wherein the pass gate method further comprises, with the pass gate driver, gate to change in response to the input voltage. of the high side switch is substantially equal to a presented comprises a gate node, and wherein the causing a voltage at the gate node of the pass Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
No layer stack recorded.
integrated half bridge power conversion circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,951Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0005]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0025]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0038]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0039]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0040]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit. [0042]
FIG. 39 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit. [0044]
FIG. 41 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 42 is a schematic illustration of an embodiment of a multiplier circuit. [0046]
FIG. 43 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
FIG. 44 is a schematic illustration of an embodiment of a multiplier circuit. [0048]
FIG. 45 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN driver circuit, comprising: an input node configured to receive an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; a low side switch connected to an output node, wherein, in response to the input voltage, the low side switch is configured to selectively connect the output node to a first node at a first voltage; a high side switch connected to the output node, wherein, in response to the input voltage, the high side switch is configured to selectively connect the output node to a second node at a second voltage; and a high side switch driver circuit configured to, in response to the input voltage, selectively cause the high side switch to connect the output node to the second node, wherein the high side switch driver circuit comprises: a pass gate configured to connect the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and a pass gate driver configured to cause the pass gate to be conductive in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, wherein the pass gate comprises a gate node, and wherein the pass gate driver is configured to cause a voltage at the gate node of the pass gate to change in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, further comprising an inverting logic circuit configured to cause the voltage at the first internal node to become greater than the second voltage by at least a threshold voltage of the high side switch in response to the input voltage. Previously presented
The GaN driver circuit of claim I, wherein the pass gate is configured to conduct current from the first internal node to the high side switch until the voltage at the gate of the high side switch is substantially equal to a voltage at the first internal node. Previously presented
A method of operating a GaN driver circuit, the method comprising: with an input node, receiving an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; with a low side switch connected to an output node, in response to the input voltage, selectively connecting the output node to a first node at a first voltage; with a high side switch connected to the output node, in response to the input voltage, selectively connecting the output node to a second node at a second voltage; with a high side switch driver circuit, in response to the input voltage, selectively causing the high side switch to connect the output node to the second node, wherein selectively causing the high side switch to connect the output node to the second node comprises: with a pass gate, connecting the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and with a pass gate driver, causing the pass gate to be conductive in response to the input voltage. Previously presented
The method of claim 18, with the pass gate, conducting current from the first internal node to the high side switch until the voltage at the gate voltage at the first internal node. Previously
The method of claim 18, wherein the pass gate method further comprises, with the pass gate driver, gate to change in response to the input voltage. of the high side switch is substantially equal to a presented comprises a gate node, and wherein the causing a voltage at the gate node of the pass Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
No layer stack recorded.
integrated half bridge power conversion circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,811,951Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0005]
FIG. 2 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 3 is a schematic of the first level shift transistor illustrated in
FIG. 4 is a schematic of the level shift driver circuit illustrated in
FIG. 5 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 6 is an example of waveforms within the blanking pulse generator illustrated in
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 9 is a schematic of the startup circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 11 is a schematic of the UVLO circuit illustrated in
FIG. 12 is a schematic of the bootstrap capacitor charging circuit illustrated in
FIG. 13 is a schematic of an alternative bootstrap capacitor charging circuit as compared to the circuit illustrated in
FIG. 14 is a schematic of the high side logic and control circuit illustrated in
FIG. 15 is a schematic of the first level shift receiver circuit illustrated in
FIG. 16 is a schematic of the second level shift receiver circuit illustrated in
FIG. 17 is a schematic of the pull up trigger circuit illustrated in
FIG. 18 is a schematic of the high side UVLO circuit illustrated in
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 20 is a schematic of a high side reference voltage generation circuit illustrated in
FIG. 21 is a simplified schematic of a half bridge power conversion circuit according to another embodiment of the invention; [0025]
FIG. 22 is a simplified schematic of the circuits within the low side control circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 24 is a schematic of the inverter/buffer circuit illustrated in
FIG. 25 is a schematic of the on pulse generator circuit illustrated in
FIG. 26 is a schematic of the off pulse generator circuit illustrated in
FIG. 27 is a schematic of the blanking pulse generator circuit illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 29 is a simplified schematic of the circuits within the high side control circuit illustrated in
FIG. 30 is a schematic of the level shift 1 receiver circuit illustrated in
FIG. 31 is a schematic of level shift 2 receiver circuit illustrated in
FIG. 32 is a schematic of the high side UVLO circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
FIG. 34 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0038]
FIG. 35 is a schematic of an electro-static discharge (ESD) clamp circuit according to an embodiment of the invention; [0039]
FIG. 36 is an illustration of a portion of an electronic package according to an embodiment of the invention; [0040]
FIG. 37 is an illustration of the electronic package of
FIG. 38 is a schematic illustration of an embodiment of a driver circuit. [0042]
FIG. 39 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 40 is a schematic illustration of an embodiment of a driver circuit. [0044]
FIG. 41 is a timing diagram illustrating timing relationships between various signals of the driver circuit of
FIG. 42 is a schematic illustration of an embodiment of a multiplier circuit. [0046]
FIG. 43 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
FIG. 44 is a schematic illustration of an embodiment of a multiplier circuit. [0048]
FIG. 45 is a timing diagram illustrating timing relationships between various signals of the multiplier circuit of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN driver circuit, comprising: an input node configured to receive an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; a low side switch connected to an output node, wherein, in response to the input voltage, the low side switch is configured to selectively connect the output node to a first node at a first voltage; a high side switch connected to the output node, wherein, in response to the input voltage, the high side switch is configured to selectively connect the output node to a second node at a second voltage; and a high side switch driver circuit configured to, in response to the input voltage, selectively cause the high side switch to connect the output node to the second node, wherein the high side switch driver circuit comprises: a pass gate configured to connect the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and a pass gate driver configured to cause the pass gate to be conductive in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, wherein the pass gate comprises a gate node, and wherein the pass gate driver is configured to cause a voltage at the gate node of the pass gate to change in response to the input voltage. Previously presented
The GaN driver circuit of claim 1, further comprising an inverting logic circuit configured to cause the voltage at the first internal node to become greater than the second voltage by at least a threshold voltage of the high side switch in response to the input voltage. Previously presented
The GaN driver circuit of claim I, wherein the pass gate is configured to conduct current from the first internal node to the high side switch until the voltage at the gate of the high side switch is substantially equal to a voltage at the first internal node. Previously presented
A method of operating a GaN driver circuit, the method comprising: with an input node, receiving an input voltage, wherein the input voltage switches between a first voltage value and a second voltage value; with a low side switch connected to an output node, in response to the input voltage, selectively connecting the output node to a first node at a first voltage; with a high side switch connected to the output node, in response to the input voltage, selectively connecting the output node to a second node at a second voltage; with a high side switch driver circuit, in response to the input voltage, selectively causing the high side switch to connect the output node to the second node, wherein selectively causing the high side switch to connect the output node to the second node comprises: with a pass gate, connecting the high side switch to a first internal node, such that the pass gate conducts current from the first internal node to the high side switch to cause a voltage at a gate of the high side switch to be substantially equal to a voltage at the first internal node, thereby causing the high side switch to connect the output node to the second node, and with a pass gate driver, causing the pass gate to be conductive in response to the input voltage. Previously presented
The method of claim 18, with the pass gate, conducting current from the first internal node to the high side switch until the voltage at the gate voltage at the first internal node. Previously
The method of claim 18, wherein the pass gate method further comprises, with the pass gate driver, gate to change in response to the input voltage. of the high side switch is substantially equal to a presented comprises a gate node, and wherein the causing a voltage at the gate node of the pass Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
No layer stack recorded.
integrated half bridge power conversion circuit
No layer stack recorded.
Materials described outside the worked examples.
gallium nitride (GaN)
GaN
GaN on silicon
GaN on silicon carbide
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic of the first level shift transistor illustrated in
Related documents with shared materials, methods, properties, or citations.
GaN on sapphire
GaN on aluminum nitride
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
GaN on sapphire
GaN on aluminum nitride
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
GaN on sapphire
GaN on aluminum nitride
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in
GaN on sapphire
GaN on aluminum nitride
AlGaN
InGaN
FIG. 7 is a schematic of the bootstrap transistor drive circuit illustrated in
FIG. 8 is a block diagram for the low side transistor drive circuit illustrated in
FIG. 10 is series of diode connected GaN-based enhancement-mode transistors that may be used as a diode clamp in the schematic of
FIG. 19 is a schematic of the high side transistor driver circuit illustrated in
FIG. 23 is a schematic of the first level shift transistor illustrated in
FIG. 28 is a schematic of the low side transistor drive circuit illustrated in
FIG. 33 is a schematic of the high side transistor driver circuit illustrated in