Patent
US 10,192,799METHOD AND APPARATUS TO MODEL AND MONITOR TIME DEPENDENT DIELECTRIC BREAKDOWN IN MULTI-FIELD PLATE GALLIUM NITRIDE DEVICES
Dong Seup Lee
US
Copyright © 2026 Matter42. All rights reserved.
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US 10,192,799Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
FIG. 2 discloses a graph that plots the square root of the gate/drain voltage (V DG) again s t a logarithmic scale of time in seconds. When plotted in this …
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A test method for testing a Gallium-Nitride (GaN) device, comprising: providing a first set of (N+1) test structures that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate; a dielectric material overlying the GaN substrate; a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact; and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X field plates comprising field plates that are nearest to the GaN substrate; and for each test structure TSx, applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 1, wherein first set of (N+1) test structures further comprises a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate of each test structure.
The test method of claim 1, further comprising providing a second set of (N- 1) test structures with Y being an integer between 1 and (N- 1) inclusive, each test structure TS y of the second set of (N- 1) test structures comprising: a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; and a respective field plate corresponding to the Y th field plate of the GaN transistor.
A test method comprising: providing a first set of test structures TS o through TS N f o r a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate, a respective drain contact abutting the GaN substrate, a respective gate overlying the substrate and lying between the source contact and the drain contact, X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate; for each test structure TSx, the test method comprising: applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected; and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 12, wherein the first set of test structures are provided in a scribe structure and the test method further comprises determining whether there is in a determined lifetime of the GaN transistor at the stress voltage.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and using a plurality of the recorded times-to-failure of the test structure to extrapolate a mean time-to-failure at normal operating voltages.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and determining whether there has been a drift in a voltage acceleration factor.
The test method of claim 12, further comprising holding the gate at a voltage that is lower than the threshold voltage of the GaN transistor.
The test method of claim 12, further comprising holding the source contact at a lower rail.
The test method of claim 12, wherein the stress voltage is in the range of approximately three to six times the normal operating voltage.
Layer stacks claimed or described, ordered top of device to substrate.
GaN multi-field-plate transistor test structure TSx (first set)
GaN field-plate-only test structure TSy (second set)
Materials described outside the worked examples.
Gallium Nitride
GaN
dielectric material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,192,799Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
FIG. 2 discloses a graph that plots the square root of the gate/drain voltage (V DG) again s t a logarithmic scale of time in seconds. When plotted in this …
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A test method for testing a Gallium-Nitride (GaN) device, comprising: providing a first set of (N+1) test structures that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate; a dielectric material overlying the GaN substrate; a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact; and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X field plates comprising field plates that are nearest to the GaN substrate; and for each test structure TSx, applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 1, wherein first set of (N+1) test structures further comprises a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate of each test structure.
The test method of claim 1, further comprising providing a second set of (N- 1) test structures with Y being an integer between 1 and (N- 1) inclusive, each test structure TS y of the second set of (N- 1) test structures comprising: a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; and a respective field plate corresponding to the Y th field plate of the GaN transistor.
A test method comprising: providing a first set of test structures TS o through TS N f o r a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate, a respective drain contact abutting the GaN substrate, a respective gate overlying the substrate and lying between the source contact and the drain contact, X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate; for each test structure TSx, the test method comprising: applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected; and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 12, wherein the first set of test structures are provided in a scribe structure and the test method further comprises determining whether there is in a determined lifetime of the GaN transistor at the stress voltage.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and using a plurality of the recorded times-to-failure of the test structure to extrapolate a mean time-to-failure at normal operating voltages.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and determining whether there has been a drift in a voltage acceleration factor.
The test method of claim 12, further comprising holding the gate at a voltage that is lower than the threshold voltage of the GaN transistor.
The test method of claim 12, further comprising holding the source contact at a lower rail.
The test method of claim 12, wherein the stress voltage is in the range of approximately three to six times the normal operating voltage.
Layer stacks claimed or described, ordered top of device to substrate.
GaN multi-field-plate transistor test structure TSx (first set)
GaN field-plate-only test structure TSy (second set)
Materials described outside the worked examples.
Gallium Nitride
GaN
dielectric material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,192,799Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
FIG. 2 discloses a graph that plots the square root of the gate/drain voltage (V DG) again s t a logarithmic scale of time in seconds. When plotted in this …
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A test method for testing a Gallium-Nitride (GaN) device, comprising: providing a first set of (N+1) test structures that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate; a dielectric material overlying the GaN substrate; a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact; and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X field plates comprising field plates that are nearest to the GaN substrate; and for each test structure TSx, applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 1, wherein first set of (N+1) test structures further comprises a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate of each test structure.
The test method of claim 1, further comprising providing a second set of (N- 1) test structures with Y being an integer between 1 and (N- 1) inclusive, each test structure TS y of the second set of (N- 1) test structures comprising: a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; and a respective field plate corresponding to the Y th field plate of the GaN transistor.
A test method comprising: providing a first set of test structures TS o through TS N f o r a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate, a respective drain contact abutting the GaN substrate, a respective gate overlying the substrate and lying between the source contact and the drain contact, X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate; for each test structure TSx, the test method comprising: applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected; and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 12, wherein the first set of test structures are provided in a scribe structure and the test method further comprises determining whether there is in a determined lifetime of the GaN transistor at the stress voltage.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and using a plurality of the recorded times-to-failure of the test structure to extrapolate a mean time-to-failure at normal operating voltages.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and determining whether there has been a drift in a voltage acceleration factor.
The test method of claim 12, further comprising holding the gate at a voltage that is lower than the threshold voltage of the GaN transistor.
The test method of claim 12, further comprising holding the source contact at a lower rail.
The test method of claim 12, wherein the stress voltage is in the range of approximately three to six times the normal operating voltage.
Layer stacks claimed or described, ordered top of device to substrate.
GaN multi-field-plate transistor test structure TSx (first set)
GaN field-plate-only test structure TSy (second set)
Materials described outside the worked examples.
Gallium Nitride
GaN
dielectric material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,192,799Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
FIG. 2 discloses a graph that plots the square root of the gate/drain voltage (V DG) again s t a logarithmic scale of time in seconds. When plotted in this …
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A test method for testing a Gallium-Nitride (GaN) device, comprising: providing a first set of (N+1) test structures that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate; a dielectric material overlying the GaN substrate; a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact; and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X field plates comprising field plates that are nearest to the GaN substrate; and for each test structure TSx, applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 1, wherein first set of (N+1) test structures further comprises a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate of each test structure.
The test method of claim 1, further comprising providing a second set of (N- 1) test structures with Y being an integer between 1 and (N- 1) inclusive, each test structure TS y of the second set of (N- 1) test structures comprising: a respective source contact abutting the GaN substrate; a respective drain contact abutting the GaN substrate; and a respective field plate corresponding to the Y th field plate of the GaN transistor.
A test method comprising: providing a first set of test structures TS o through TS N f o r a gallium nitride (GaN) transistor that comprises N field plates, N being an integer and X being an integer between 0 and N inclusive, each test structure TSx of the first set of test structures comprising: a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate, a respective drain contact abutting the GaN substrate, a respective gate overlying the substrate and lying between the source contact and the drain contact, X respective field plates corresponding to X field plates of the N field plates of the GaN transistor that are nearest to the GaN substrate, and a respective input/output pad coupled to each of the respective source contact, the respective drain contact and the respective gate; for each test structure TSx, the test method comprising: applying a stress voltage to the drain contact of test structure TSx until a dielectric breakdown condition is detected; and recording the time-to-failure of test structure TSx at the stress voltage.
The test method of claim 12, wherein the first set of test structures are provided in a scribe structure and the test method further comprises determining whether there is in a determined lifetime of the GaN transistor at the stress voltage.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and using a plurality of the recorded times-to-failure of the test structure to extrapolate a mean time-to-failure at normal operating voltages.
The test method of claim 12, further comprising: incrementing the stress voltage; performing the applying, recording and incrementing a selected number of times, each of the selected number of times being performed on a new first set of test structures; and determining whether there has been a drift in a voltage acceleration factor.
The test method of claim 12, further comprising holding the gate at a voltage that is lower than the threshold voltage of the GaN transistor.
The test method of claim 12, further comprising holding the source contact at a lower rail.
The test method of claim 12, wherein the stress voltage is in the range of approximately three to six times the normal operating voltage.
Layer stacks claimed or described, ordered top of device to substrate.
GaN multi-field-plate transistor test structure TSx (first set)
GaN field-plate-only test structure TSy (second set)
Materials described outside the worked examples.
Gallium Nitride
GaN
dielectric material
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A represents a cross-section of both an example GaN device and a first test structure 1 00 A for the GaN device according to an embodiment of the …
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlGaN
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
aluminum gallium nitride
AlGaN
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
aluminum gallium nitride
AlGaN
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …
aluminum gallium nitride
AlGaN
FIG. 3B. Accordingly, appropriate voltages can be applied to the I/O pads 312 that correspond to source contact 316, gate 320 and drain contact 318 of each of …
FIGS. 4A-D depict an overall test method for testing a gallium nitride (GaN) transistor or other semiconductor device that comprises N field plates, N being an …