Patent
US 10,199,477COMPLEMENTARY GALLIUM NITRIDE INTEGRATED CIRCUITS AND METHODS OF THEIR FABRICATION
Philippe Renaud
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,199,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 2 and step 200, the method includes forming a first sub- layer 240 over a top surface of a first GaN layer 230 (e.g., GaN layer 130,
FIG. 3 and step 300, a patterned photoresist mask is applied to the top surface of the first sub-layer 240, so that mask material first sub-layer 240, so that …
FIG. 4. This line is not reproduced in subsequent figures, as no actual boundary may be present when the materials for the first and second sub-layers 240, …
FIG. 5 and step 500, a third layer 550 is formed over a top surface of second layer 440 (i.e., over the second region 344 of GaN layer 230). According to an …
FIG. 6 and step 600, the mask material 310 may be removed, and a plurality of conductive contacts 614, conductive contacts 614, 616, conductive contacts 614, …
FIG. 7 and step 700, the method includes forming a relatively thick second layer 740 over a top surface of a first GaN layer 730 (e.g., GaN layer 130,
FIG. 8 and step 800, a third layer 850 is formed over a top surface of second layer 740. According to an embodiment, third layer 850 is formed by epitaxy …
FIG. 9 and step 900, a patterned etch mask is applied to the top surface of the third layer 850, so that mask material third layer 850, so that mask material …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 11 and step 1100, a plurality of conductive contacts 1114, conductive contacts 1114, 1116, conductive contacts 1114, 1116, 1118, conductive contacts 1114, …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 13 is an equivalent schematic diagram 1300 of the single-phase, half-bridge inverter 1200 of
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 15 is an equivalent schematic diagram 1500 of the push-pull output 1400 of
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; 17 NS₃ 01 72ZP-US 06 third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; a positive input terminal coupled to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage; a negative input terminal coupled to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage; a first transistor control terminal coupled to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal; a second transistor control terminal coupled to the second channel control contact of the second transistor, wherein the second transistor control terminal is configured to receive a second switch control signal; a first cathode of a first diode coupled to the first current carrying contact of the first transistor; a first anode of the first diode coupled to the second current carrying contact of the first transistor; a second cathode of a second diode coupled to the third current carrying contact of the second transistor; a second anode of the second diode coupled to the fourth current carrying contact of the second transistor; and an output terminal coupled to the second current carrying contact and the third current carrying contact to form an inverter, wherein the output terminal is configured to provide an AC signal to a load.
The integrated circuit of claim 1, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (A l GaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from an aluminum gallium nitride (A l GaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
The integrated circuit of claim 1, wherein the first height is in a range of 15 nanometers to nanometers.
The integrated circuit of claim 1, wherein the third layer includes a semiconductor material doped with a p-type dopant.
The integrated circuit of claim 1, wherein the third layer has a thickness in a range of 10 nm to 30 nm.
The integrated circuit of claim 1, further comprising: an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 20 NS₃ 01 72ZP-US 06 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; an output of a comparator coupled to the first and second channel control contacts of the first and second transistors; an input terminal coupled to a first input of the comparator; a first power supply terminal coupled to the first current carrying terminal of the first transistor; a second power supply terminal coupled to the fourth current carrying terminal of the second transistor; and an output terminal coupled to a second input of the comparator, and wherein the second current carrying terminal of the first transistor and the third current carrying terminal of the second transistor are coupled to the output terminal to form a push-pull output circuit.
The integrated circuit of claim 12, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; 22 NS₃ 01 72ZP-US 06 a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type, wherein the first current carrying terminal of the first transistor is coupled to the second channel control contact of the second transistor; an input terminal coupled to the channel control contact of the first transistor; a source terminal coupled to the third current carrying terminal of the second transistor; and a drain terminal coupled to the second current carrying terminal of the first transistor and to the fourth current carrying terminal of the second transistor to form a compound transistor.
The integrated circuit of claim 18, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
Layer stacks claimed or described, ordered top of device to substrate.
complementary GaN inverter integrated circuit
complementary GaN push-pull output circuit with comparator feedback
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 15–30 nm | — |
Thickness | 40–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,199,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 2 and step 200, the method includes forming a first sub- layer 240 over a top surface of a first GaN layer 230 (e.g., GaN layer 130,
FIG. 3 and step 300, a patterned photoresist mask is applied to the top surface of the first sub-layer 240, so that mask material first sub-layer 240, so that …
FIG. 4. This line is not reproduced in subsequent figures, as no actual boundary may be present when the materials for the first and second sub-layers 240, …
FIG. 5 and step 500, a third layer 550 is formed over a top surface of second layer 440 (i.e., over the second region 344 of GaN layer 230). According to an …
FIG. 6 and step 600, the mask material 310 may be removed, and a plurality of conductive contacts 614, conductive contacts 614, 616, conductive contacts 614, …
FIG. 7 and step 700, the method includes forming a relatively thick second layer 740 over a top surface of a first GaN layer 730 (e.g., GaN layer 130,
FIG. 8 and step 800, a third layer 850 is formed over a top surface of second layer 740. According to an embodiment, third layer 850 is formed by epitaxy …
FIG. 9 and step 900, a patterned etch mask is applied to the top surface of the third layer 850, so that mask material third layer 850, so that mask material …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 11 and step 1100, a plurality of conductive contacts 1114, conductive contacts 1114, 1116, conductive contacts 1114, 1116, 1118, conductive contacts 1114, …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 13 is an equivalent schematic diagram 1300 of the single-phase, half-bridge inverter 1200 of
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 15 is an equivalent schematic diagram 1500 of the push-pull output 1400 of
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; 17 NS₃ 01 72ZP-US 06 third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; a positive input terminal coupled to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage; a negative input terminal coupled to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage; a first transistor control terminal coupled to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal; a second transistor control terminal coupled to the second channel control contact of the second transistor, wherein the second transistor control terminal is configured to receive a second switch control signal; a first cathode of a first diode coupled to the first current carrying contact of the first transistor; a first anode of the first diode coupled to the second current carrying contact of the first transistor; a second cathode of a second diode coupled to the third current carrying contact of the second transistor; a second anode of the second diode coupled to the fourth current carrying contact of the second transistor; and an output terminal coupled to the second current carrying contact and the third current carrying contact to form an inverter, wherein the output terminal is configured to provide an AC signal to a load.
The integrated circuit of claim 1, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (A l GaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from an aluminum gallium nitride (A l GaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
The integrated circuit of claim 1, wherein the first height is in a range of 15 nanometers to nanometers.
The integrated circuit of claim 1, wherein the third layer includes a semiconductor material doped with a p-type dopant.
The integrated circuit of claim 1, wherein the third layer has a thickness in a range of 10 nm to 30 nm.
The integrated circuit of claim 1, further comprising: an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 20 NS₃ 01 72ZP-US 06 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; an output of a comparator coupled to the first and second channel control contacts of the first and second transistors; an input terminal coupled to a first input of the comparator; a first power supply terminal coupled to the first current carrying terminal of the first transistor; a second power supply terminal coupled to the fourth current carrying terminal of the second transistor; and an output terminal coupled to a second input of the comparator, and wherein the second current carrying terminal of the first transistor and the third current carrying terminal of the second transistor are coupled to the output terminal to form a push-pull output circuit.
The integrated circuit of claim 12, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; 22 NS₃ 01 72ZP-US 06 a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type, wherein the first current carrying terminal of the first transistor is coupled to the second channel control contact of the second transistor; an input terminal coupled to the channel control contact of the first transistor; a source terminal coupled to the third current carrying terminal of the second transistor; and a drain terminal coupled to the second current carrying terminal of the first transistor and to the fourth current carrying terminal of the second transistor to form a compound transistor.
The integrated circuit of claim 18, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
Layer stacks claimed or described, ordered top of device to substrate.
complementary GaN inverter integrated circuit
complementary GaN push-pull output circuit with comparator feedback
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 15–30 nm | — |
Thickness | 40–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,199,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 2 and step 200, the method includes forming a first sub- layer 240 over a top surface of a first GaN layer 230 (e.g., GaN layer 130,
FIG. 3 and step 300, a patterned photoresist mask is applied to the top surface of the first sub-layer 240, so that mask material first sub-layer 240, so that …
FIG. 4. This line is not reproduced in subsequent figures, as no actual boundary may be present when the materials for the first and second sub-layers 240, …
FIG. 5 and step 500, a third layer 550 is formed over a top surface of second layer 440 (i.e., over the second region 344 of GaN layer 230). According to an …
FIG. 6 and step 600, the mask material 310 may be removed, and a plurality of conductive contacts 614, conductive contacts 614, 616, conductive contacts 614, …
FIG. 7 and step 700, the method includes forming a relatively thick second layer 740 over a top surface of a first GaN layer 730 (e.g., GaN layer 130,
FIG. 8 and step 800, a third layer 850 is formed over a top surface of second layer 740. According to an embodiment, third layer 850 is formed by epitaxy …
FIG. 9 and step 900, a patterned etch mask is applied to the top surface of the third layer 850, so that mask material third layer 850, so that mask material …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 11 and step 1100, a plurality of conductive contacts 1114, conductive contacts 1114, 1116, conductive contacts 1114, 1116, 1118, conductive contacts 1114, …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 13 is an equivalent schematic diagram 1300 of the single-phase, half-bridge inverter 1200 of
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 15 is an equivalent schematic diagram 1500 of the push-pull output 1400 of
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; 17 NS₃ 01 72ZP-US 06 third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; a positive input terminal coupled to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage; a negative input terminal coupled to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage; a first transistor control terminal coupled to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal; a second transistor control terminal coupled to the second channel control contact of the second transistor, wherein the second transistor control terminal is configured to receive a second switch control signal; a first cathode of a first diode coupled to the first current carrying contact of the first transistor; a first anode of the first diode coupled to the second current carrying contact of the first transistor; a second cathode of a second diode coupled to the third current carrying contact of the second transistor; a second anode of the second diode coupled to the fourth current carrying contact of the second transistor; and an output terminal coupled to the second current carrying contact and the third current carrying contact to form an inverter, wherein the output terminal is configured to provide an AC signal to a load.
The integrated circuit of claim 1, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (A l GaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from an aluminum gallium nitride (A l GaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
The integrated circuit of claim 1, wherein the first height is in a range of 15 nanometers to nanometers.
The integrated circuit of claim 1, wherein the third layer includes a semiconductor material doped with a p-type dopant.
The integrated circuit of claim 1, wherein the third layer has a thickness in a range of 10 nm to 30 nm.
The integrated circuit of claim 1, further comprising: an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 20 NS₃ 01 72ZP-US 06 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; an output of a comparator coupled to the first and second channel control contacts of the first and second transistors; an input terminal coupled to a first input of the comparator; a first power supply terminal coupled to the first current carrying terminal of the first transistor; a second power supply terminal coupled to the fourth current carrying terminal of the second transistor; and an output terminal coupled to a second input of the comparator, and wherein the second current carrying terminal of the first transistor and the third current carrying terminal of the second transistor are coupled to the output terminal to form a push-pull output circuit.
The integrated circuit of claim 12, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; 22 NS₃ 01 72ZP-US 06 a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type, wherein the first current carrying terminal of the first transistor is coupled to the second channel control contact of the second transistor; an input terminal coupled to the channel control contact of the first transistor; a source terminal coupled to the third current carrying terminal of the second transistor; and a drain terminal coupled to the second current carrying terminal of the first transistor and to the fourth current carrying terminal of the second transistor to form a compound transistor.
The integrated circuit of claim 18, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
Layer stacks claimed or described, ordered top of device to substrate.
complementary GaN inverter integrated circuit
complementary GaN push-pull output circuit with comparator feedback
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 15–30 nm | — |
Thickness | 40–100 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,199,477Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 2 and step 200, the method includes forming a first sub- layer 240 over a top surface of a first GaN layer 230 (e.g., GaN layer 130,
FIG. 3 and step 300, a patterned photoresist mask is applied to the top surface of the first sub-layer 240, so that mask material first sub-layer 240, so that …
FIG. 4. This line is not reproduced in subsequent figures, as no actual boundary may be present when the materials for the first and second sub-layers 240, …
FIG. 5 and step 500, a third layer 550 is formed over a top surface of second layer 440 (i.e., over the second region 344 of GaN layer 230). According to an …
FIG. 6 and step 600, the mask material 310 may be removed, and a plurality of conductive contacts 614, conductive contacts 614, 616, conductive contacts 614, …
FIG. 7 and step 700, the method includes forming a relatively thick second layer 740 over a top surface of a first GaN layer 730 (e.g., GaN layer 130,
FIG. 8 and step 800, a third layer 850 is formed over a top surface of second layer 740. According to an embodiment, third layer 850 is formed by epitaxy …
FIG. 9 and step 900, a patterned etch mask is applied to the top surface of the third layer 850, so that mask material third layer 850, so that mask material …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 11 and step 1100, a plurality of conductive contacts 1114, conductive contacts 1114, 1116, conductive contacts 1114, 1116, 1118, conductive contacts 1114, …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 13 is an equivalent schematic diagram 1300 of the single-phase, half-bridge inverter 1200 of
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 15 is an equivalent schematic diagram 1500 of the push-pull output 1400 of
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; 17 NS₃ 01 72ZP-US 06 third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; a positive input terminal coupled to the first current carrying terminal of the first transistor, wherein the positive input terminal is configured to receive a first voltage; a negative input terminal coupled to the fourth current carrying terminal of the second transistor, wherein the negative input terminal is configured to receive a second voltage; a first transistor control terminal coupled to the first channel control contact of the first transistor, wherein the first transistor control terminal is configured to receive a first switch control signal; a second transistor control terminal coupled to the second channel control contact of the second transistor, wherein the second transistor control terminal is configured to receive a second switch control signal; a first cathode of a first diode coupled to the first current carrying contact of the first transistor; a first anode of the first diode coupled to the second current carrying contact of the first transistor; a second cathode of a second diode coupled to the third current carrying contact of the second transistor; a second anode of the second diode coupled to the fourth current carrying contact of the second transistor; and an output terminal coupled to the second current carrying contact and the third current carrying contact to form an inverter, wherein the output terminal is configured to provide an AC signal to a load.
The integrated circuit of claim 1, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (A l GaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 1, wherein the first and second sub-layers are formed from an aluminum gallium nitride (A l GaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
The integrated circuit of claim 1, wherein the first height is in a range of 15 nanometers to nanometers.
The integrated circuit of claim 1, wherein the third layer includes a semiconductor material doped with a p-type dopant.
The integrated circuit of claim 1, wherein the third layer has a thickness in a range of 10 nm to 30 nm.
The integrated circuit of claim 1, further comprising: an isolation structure between the first transistor and the second transistor, wherein the isolation structure is selected from an isolation mesa, an implant region, and implant well, and a trench isolation structure.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 20 NS₃ 01 72ZP-US 06 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type; an output of a comparator coupled to the first and second channel control contacts of the first and second transistors; an input terminal coupled to a first input of the comparator; a first power supply terminal coupled to the first current carrying terminal of the first transistor; a second power supply terminal coupled to the fourth current carrying terminal of the second transistor; and an output terminal coupled to a second input of the comparator, and wherein the second current carrying terminal of the first transistor and the third current carrying terminal of the second transistor are coupled to the output terminal to form a push-pull output circuit.
The integrated circuit of claim 12, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 12, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
An integrated circuit comprising: a gallium nitride (GaN) layer, wherein the GaN layer has a first bandgap, a first region, and a second region adjacent to the first region; a first sub-layer of a second layer over a top surface of the GaN layer, wherein the first sub-layer has a second bandgap that is different from the first bandgap, resulting in a two dimensional electron gas (2DEG) in a contact region between the GaN layer and the first sub- layer, wherein the first sub-layer has a first portion formed over the first region of the GaN layer, and a second portion formed over the second region of the GaN layer, and wherein the first portion of the first sub-layer has a top surface at a first height above the first region of the GaN layer; a physically damaged structure of the contact region between the second region of the GaN layer and the second portion of the first sub-layer, which suppresses the 2DEG in the contact region between the second region of the GaN layer and the second portion of the first sub-layer; a second sub-layer of the second layer over a top surface of the second portion of the first sub-layer, wherein the second sub-layer has a top surface at a second height above the GaN layer that is greater than the first height, and the second layer includes a vertical sidewall positioned between the first and second portions and extending between the top surface of the first portion of the first sub-layer and the top surface of the second sub-layer; a third layer over the second sub-layer, wherein the third layer has a third bandgap that is different from the second bandgap, resulting in a two dimensional hole gas (2DHG) in a contact region between the second sub-layer and the third layer; first and second current carrying contacts over the first portion of the first sub-layer; 22 NS₃ 01 72ZP-US 06 a first channel control contact over the first portion of the first sub-layer and between the first and second current carrying contacts, wherein the first portion of the first sub-layer, the 2DEG, the first and second current carrying contacts, and the first channel control contact form portions of a first transistor having a first conductivity type; third and fourth current carrying contacts over the third layer; a second channel control contact over the third layer between the third and fourth current carrying contacts, wherein the third layer, the second sub-layer, the 2DHG, the third and fourth current carrying contacts, and the second channel control contact form portions of a second transistor having a second conductivity type, wherein the first current carrying terminal of the first transistor is coupled to the second channel control contact of the second transistor; an input terminal coupled to the channel control contact of the first transistor; a source terminal coupled to the third current carrying terminal of the second transistor; and a drain terminal coupled to the second current carrying terminal of the first transistor and to the fourth current carrying terminal of the second transistor to form a compound transistor.
The integrated circuit of claim 18, wherein the physically damaged structure of the contact region comprises implanted ions in the contact region, wherein the implanted ions form traps that suppress the 2DEG in the second region.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from a material selected from an aluminum gallium nitride (AlGaN) alloy, an indium aluminum nitride (InAl N) alloy, and an indium gallium nitride (InGaN) alloy.
The integrated circuit of claim 18, wherein the first and second sub-layers are formed from an aluminum gallium nitride (AlGaN) alloy having an atomic percentage of aluminum in a range of 20 percent to 30 percent.
Layer stacks claimed or described, ordered top of device to substrate.
complementary GaN inverter integrated circuit
complementary GaN push-pull output circuit with comparator feedback
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 15–30 nm | — |
Thickness | 40–100 nm |
Related documents with shared materials, methods, properties, or citations.
complementary GaN compound transistor integrated circuit
p-type doped semiconductor third layer
indium aluminum nitride
InAlN
indium gallium nitride
InGaN
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
| — |
Thickness | 10–30 nm | — |
complementary GaN compound transistor integrated circuit
p-type doped semiconductor third layer
indium aluminum nitride
InAlN
indium gallium nitride
InGaN
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
| — |
Thickness | 10–30 nm | — |
complementary GaN compound transistor integrated circuit
p-type doped semiconductor third layer
indium aluminum nitride
InAlN
indium gallium nitride
InGaN
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
| — |
Thickness | 10–30 nm | — |
complementary GaN compound transistor integrated circuit
p-type doped semiconductor third layer
indium aluminum nitride
InAlN
indium gallium nitride
InGaN
FIG. 1, the 2DEG 122 is present in region 132 of GaN layer 130, as it is important for the functioning of N-channel transistor 110, but the 2DEG 122 has been …
FIG. 10 and step 1000, with the mask material 910 removed, the etching process yields a modified second layer 1040 that includes a first portion 1044 having the …
FIG. 12. Essentially, inverter 1200, 1300 is configured to produce an AC output waveform from a DC voltage source (e.g., DC voltage source 1360). [0043] …
FIG. 14. Push-pull output 1400, 1500 is configured alternatively to supply current to, or absorb current from, a connected load (e.g., load 1540, not …
FIG. 16. DETA I LED DESCRIPTION [0014] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the …
FIG. 17 is an equivalent schematic diagram 1700 of the compound transistor 1600 of
| — |
Thickness | 10–30 nm | — |