ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

Qhalid RS Fareed; Dong Seup Lee; Jungwoo Joh; Chang Soo Suh

Patent

Atlas literature

Patent

US 12,615,796 B2

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

Qhalid RS Fareed, Dong Seup Lee, Jungwoo Joh, Chang Soo Suh

TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)·Apr. 28, 2026·US

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME | Matter42 Literature

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a partial sectional side elevation view of an electronic device with an enhancement mode GaN transistor gate structure having a substantially undoped …

FIG. 2

FIG. 2 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 3

FIG. 3 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 4

FIG. 4.

FIG. 5

FIGS. 5-16 are partial sectional side elevation views of the electronic device of

FIG. 6

FIG. 6 shows one example, in which an epitaxial deposition process 600 is performed that deposits the ﬁrst aluminum gallium nitride sublayer 111 over the …

FIG. 7

FIG. 7 shows one example, in which a second epitaxial deposition process 700 is performed that deposits the second aluminum gallium nitride sublayer 112 with …

FIG. 8

FIG. 8 shows one example, in which a third epitaxial deposition process 800 is performed that deposits the third aluminum gallium nitride sublayer 113 with an …

FIG. 9

FIG. 9 shows one example, in which an epitaxial deposition process 900 is performed that depos- its the carbon doped gallium nitride layer 116 (GAN:C) over 15 …

FIG. 10

FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the gallium nitride layer 118 to a 40 thickness 144. In one …

FIG. 11

FIG. 11. 50 In one example, the process 1100 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At …

FIG. 12

FIG. 12. In one example, the process 1200 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. In …

FIG. 13

FIG. 13 at 422 using no p-type dopants to form the 65 gallium nitride interlayer 123 over the aluminum nitride layer 120. In one example, the growth …

FIG. 14

FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed using magnesium or other p-type dopants that deposits the p-doped gallium …

FIG. 15

FIG. 15 above) using no p-type dopants to form the gallium nitride interlayer 225 over the p-doped gallium nitride layer 124, and forming the enhancement mode …

FIG. 16

FIG. 16 shows one example, in which an etch process 1600 is performed using a patterned etch mask 1602 to pattern exposed portions of the layers 123, 124 and …

FIG. 17

FIG. 17 is a perspective view of a packaged electronic device fabricated according to the method of

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 18 dependent

1
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is over the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the second gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the third gallium nitride layer has a second peak p-type dopant concentration that is more than 10 times greater than the ﬁrst peak p-type dopant concentration.
1. 2
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 50 nm or less.
2. 3
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 10-20 nm.
3. 4
  Dependent← claim 1GaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the third gallium nitride layer is doped with magnesium (Mg).
4. 5
  Dependent← claim 1AlNAlNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 6
  Dependent← claim 1enhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact is directly on the third gallium nitride layer.
6. 7
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a fourth gallium nitride layer on the third gallium nitride layer, the fourth gallium nitride layer having a third peak p-type dopant concentration that is less than 0.1 times the second peak p-type dopant concentration, wherein the gate contact is directly on the fourth gallium nitride layer.
7. 13
  Dependent← claim 1gate contact metalenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact includes aluminum or copper.
8. 15
  Dependent← claim 1GaNGaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
9. 17
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
10. 18
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer.
8
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is directly on the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the third gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the second gallium nitride layer has a second peak p-type dopant concentration that is more than times greater than the ﬁrst peak p-type dopant concen-tration.
1. 9
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 50 nm or less.
2. 10
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 10-20 nm.
3. 11
  Dependent← claim 8GaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the second gallium nitride layer is doped with magnesium (Mg).
4. 12
  Dependent← claim 8AlNAlNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 14
  Dependent← claim 8gate contact metalenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the gate contact includes aluminum or copper.
6. 16
  Dependent← claim 8GaNGaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
7. 19
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
8. 20
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer. ∗ ∗ ∗ ∗ ∗

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
second GaN layer (interlayer) first peak p-type dopant concentration upper bound	100000000000000000 atoms/cm3	GaN
third GaN layer peak p-type dopant concentration relative to interlayer	—	GaN
second GaN layer thickness upper bound	50 nm	GaN
second GaN layer thickness range	—	GaN
AlN buffer layer thickness	—	AlN
carbon doped GaN layer thickness	—	GaN:C
UID GaN layer thickness	—	GaN
UID GaN layer carbon doping concentration	20000000000000000 atoms/cm3	GaN
carbon doped GaN layer carbon concentration	10000000000000000000 atoms/cm3	GaN:C
Temperature	930–1050 °C	—
Thickness	300–600 nm	—
Thickness	1.4–1.8 µm	—
Thickness	1.4–2 µm	—
Thickness	0.5–2 µm	—
Thickness	0.1–0.5 µm	—
Thickness	10–30 nm	—
Thickness	10–20 nm	—
Thickness	50–200 nm	—
Thickness	60–70 nm	—
Temperature	1000–1150 °C	—
Temperature	900–1100 °C	—
Temperature	1000–1100 °C	—
Thickness	1–2.5 µm	—
Temperature	900–1050 °C	—
Temperature	950–1050 °C	—
Thickness	70–80 nm	—

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 27

US 7,898,002 B27,898,002 B2 * 3/2011 Hikita................. H01L 29/1066examiner
US 8,076,698 B28,076,698 B2 * 12/2011 Ueda..................... H01L 29/739examiner
JP 2015115371 AJP 2015115371 A 6/2015
US 10,797,168 B110,797,168 B1 * 10/2020 Moens.............. H01L 29/66462examiner
US 2007/0278521 A12007/0278521 A1 * 12/2007 Ishida.................. H10D 64/602examiner
US 2008/0149965 A12008/0149965 A1 * 6/2008 Kaibara................ H01L 29/432examiner
US 2008/0210988 A12008/0210988 A1 9/2008 Tynam
US 2009/0194790 A12009/0194790 A1 8/2009 Sato et al.
US 2010/0258841 A12010/0258841 A1 * 10/2010 Lidow............... H01L 29/66462examiner
US 2013/0146890 A12013/0146890 A1 * 6/2013 Hwang.............. H10D 30/4755examiner
US 2014/0302673 A12014/0302673 A1 * 10/2014 Kondo.............. H01L 21/28575examiner
US 2014/0327011 A12014/0327011 A1 11/2014 Pendharkar et al.
US 2015/0236121 A12015/0236121 A1 * 8/2015 Chiu.................... H10D 64/685examiner
US 2016/0218202 A12016/0218202 A1 7/2016 Fareed et al.
US 2016/0293596 A12016/0293596 A1 10/2016 Fareed et al.
US 2016/0359005 A12016/0359005 A1 * 12/2016 Hu........................ H01L 29/365examiner
US 2017/0186859 A12017/0186859 A1 6/2017 Haider et al.
US 2018/0151712 A12018/0151712 A1 * 5/2018 Ningaraju........... H01L 29/7787examiner
US 2018/0166565 A12018/0166565 A1 * 6/2018 Chen.................... H10D 30/015examiner
US 2018/0323297 A12018/0323297 A1 11/2018 Suh et al.
US 2019/0181240 A12019/0181240 A1 6/2019 Fareed et al.
US 2019/0319111 A12019/0319111 A1 10/2019 Suh et al.
US 2020/0044067 A12020/0044067 A1 2/2020 Banerjee et al.
US 2020/0185499 A12020/0185499 A1 6/2020 Lee et al.
US 2020/0185514 A12020/0185514 A1 * 6/2020 Chen................... H01L 29/7786examiner
US 2020/0203520 A12020/0203520 A1 6/2020 Dellas et al.
US 2020/0303535 A12020/0303535 A1 9/2020 Joh et al.

Cited non-patent literature · 1

PCT International Search Report dated Jan. 20, 2022. German Office Action for Corresponding Application No. 1120210057324, dated Aug. 20, 2024.

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a partial sectional side elevation view of an electronic device with an enhancement mode GaN transistor gate structure having a substantially undoped …

FIG. 2

FIG. 2 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 3

FIG. 3 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 4

FIG. 4.

FIG. 5

FIGS. 5-16 are partial sectional side elevation views of the electronic device of

FIG. 6

FIG. 6 shows one example, in which an epitaxial deposition process 600 is performed that deposits the ﬁrst aluminum gallium nitride sublayer 111 over the …

FIG. 7

FIG. 7 shows one example, in which a second epitaxial deposition process 700 is performed that deposits the second aluminum gallium nitride sublayer 112 with …

FIG. 8

FIG. 8 shows one example, in which a third epitaxial deposition process 800 is performed that deposits the third aluminum gallium nitride sublayer 113 with an …

FIG. 9

FIG. 9 shows one example, in which an epitaxial deposition process 900 is performed that depos- its the carbon doped gallium nitride layer 116 (GAN:C) over 15 …

FIG. 10

FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the gallium nitride layer 118 to a 40 thickness 144. In one …

FIG. 11

FIG. 11. 50 In one example, the process 1100 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At …

FIG. 12

FIG. 12. In one example, the process 1200 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. In …

FIG. 13

FIG. 13 at 422 using no p-type dopants to form the 65 gallium nitride interlayer 123 over the aluminum nitride layer 120. In one example, the growth …

FIG. 14

FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed using magnesium or other p-type dopants that deposits the p-doped gallium …

FIG. 15

FIG. 15 above) using no p-type dopants to form the gallium nitride interlayer 225 over the p-doped gallium nitride layer 124, and forming the enhancement mode …

FIG. 16

FIG. 16 shows one example, in which an etch process 1600 is performed using a patterned etch mask 1602 to pattern exposed portions of the layers 123, 124 and …

FIG. 17

FIG. 17 is a perspective view of a packaged electronic device fabricated according to the method of

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 18 dependent

1
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is over the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the second gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the third gallium nitride layer has a second peak p-type dopant concentration that is more than 10 times greater than the ﬁrst peak p-type dopant concentration.
1. 2
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 50 nm or less.
2. 3
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 10-20 nm.
3. 4
  Dependent← claim 1GaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the third gallium nitride layer is doped with magnesium (Mg).
4. 5
  Dependent← claim 1AlNAlNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 6
  Dependent← claim 1enhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact is directly on the third gallium nitride layer.
6. 7
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a fourth gallium nitride layer on the third gallium nitride layer, the fourth gallium nitride layer having a third peak p-type dopant concentration that is less than 0.1 times the second peak p-type dopant concentration, wherein the gate contact is directly on the fourth gallium nitride layer.
7. 13
  Dependent← claim 1gate contact metalenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact includes aluminum or copper.
8. 15
  Dependent← claim 1GaNGaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
9. 17
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
10. 18
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer.
8
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is directly on the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the third gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the second gallium nitride layer has a second peak p-type dopant concentration that is more than times greater than the ﬁrst peak p-type dopant concen-tration.
1. 9
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 50 nm or less.
2. 10
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 10-20 nm.
3. 11
  Dependent← claim 8GaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the second gallium nitride layer is doped with magnesium (Mg).
4. 12
  Dependent← claim 8AlNAlNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 14
  Dependent← claim 8gate contact metalenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the gate contact includes aluminum or copper.
6. 16
  Dependent← claim 8GaNGaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
7. 19
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
8. 20
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer. ∗ ∗ ∗ ∗ ∗

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
second GaN layer (interlayer) first peak p-type dopant concentration upper bound	100000000000000000 atoms/cm3	GaN
third GaN layer peak p-type dopant concentration relative to interlayer	—	GaN
second GaN layer thickness upper bound	50 nm	GaN
second GaN layer thickness range	—	GaN
AlN buffer layer thickness	—	AlN
carbon doped GaN layer thickness	—	GaN:C
UID GaN layer thickness	—	GaN
UID GaN layer carbon doping concentration	20000000000000000 atoms/cm3	GaN
carbon doped GaN layer carbon concentration	10000000000000000000 atoms/cm3	GaN:C
Temperature	930–1050 °C	—
Thickness	300–600 nm	—
Thickness	1.4–1.8 µm	—
Thickness	1.4–2 µm	—
Thickness	0.5–2 µm	—
Thickness	0.1–0.5 µm	—
Thickness	10–30 nm	—
Thickness	10–20 nm	—
Thickness	50–200 nm	—
Thickness	60–70 nm	—
Temperature	1000–1150 °C	—
Temperature	900–1100 °C	—
Temperature	1000–1100 °C	—
Thickness	1–2.5 µm	—
Temperature	900–1050 °C	—
Temperature	950–1050 °C	—
Thickness	70–80 nm	—

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 27

US 7,898,002 B27,898,002 B2 * 3/2011 Hikita................. H01L 29/1066examiner
US 8,076,698 B28,076,698 B2 * 12/2011 Ueda..................... H01L 29/739examiner
JP 2015115371 AJP 2015115371 A 6/2015
US 10,797,168 B110,797,168 B1 * 10/2020 Moens.............. H01L 29/66462examiner
US 2007/0278521 A12007/0278521 A1 * 12/2007 Ishida.................. H10D 64/602examiner
US 2008/0149965 A12008/0149965 A1 * 6/2008 Kaibara................ H01L 29/432examiner
US 2008/0210988 A12008/0210988 A1 9/2008 Tynam
US 2009/0194790 A12009/0194790 A1 8/2009 Sato et al.
US 2010/0258841 A12010/0258841 A1 * 10/2010 Lidow............... H01L 29/66462examiner
US 2013/0146890 A12013/0146890 A1 * 6/2013 Hwang.............. H10D 30/4755examiner
US 2014/0302673 A12014/0302673 A1 * 10/2014 Kondo.............. H01L 21/28575examiner
US 2014/0327011 A12014/0327011 A1 11/2014 Pendharkar et al.
US 2015/0236121 A12015/0236121 A1 * 8/2015 Chiu.................... H10D 64/685examiner
US 2016/0218202 A12016/0218202 A1 7/2016 Fareed et al.
US 2016/0293596 A12016/0293596 A1 10/2016 Fareed et al.
US 2016/0359005 A12016/0359005 A1 * 12/2016 Hu........................ H01L 29/365examiner
US 2017/0186859 A12017/0186859 A1 6/2017 Haider et al.
US 2018/0151712 A12018/0151712 A1 * 5/2018 Ningaraju........... H01L 29/7787examiner
US 2018/0166565 A12018/0166565 A1 * 6/2018 Chen.................... H10D 30/015examiner
US 2018/0323297 A12018/0323297 A1 11/2018 Suh et al.
US 2019/0181240 A12019/0181240 A1 6/2019 Fareed et al.
US 2019/0319111 A12019/0319111 A1 10/2019 Suh et al.
US 2020/0044067 A12020/0044067 A1 2/2020 Banerjee et al.
US 2020/0185499 A12020/0185499 A1 6/2020 Lee et al.
US 2020/0185514 A12020/0185514 A1 * 6/2020 Chen................... H01L 29/7786examiner
US 2020/0203520 A12020/0203520 A1 6/2020 Dellas et al.
US 2020/0303535 A12020/0303535 A1 9/2020 Joh et al.

Cited non-patent literature · 1

PCT International Search Report dated Jan. 20, 2022. German Office Action for Corresponding Application No. 1120210057324, dated Aug. 20, 2024.

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a partial sectional side elevation view of an electronic device with an enhancement mode GaN transistor gate structure having a substantially undoped …

FIG. 2

FIG. 2 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 3

FIG. 3 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 4

FIG. 4.

FIG. 5

FIGS. 5-16 are partial sectional side elevation views of the electronic device of

FIG. 6

FIG. 6 shows one example, in which an epitaxial deposition process 600 is performed that deposits the ﬁrst aluminum gallium nitride sublayer 111 over the …

FIG. 7

FIG. 7 shows one example, in which a second epitaxial deposition process 700 is performed that deposits the second aluminum gallium nitride sublayer 112 with …

FIG. 8

FIG. 8 shows one example, in which a third epitaxial deposition process 800 is performed that deposits the third aluminum gallium nitride sublayer 113 with an …

FIG. 9

FIG. 9 shows one example, in which an epitaxial deposition process 900 is performed that depos- its the carbon doped gallium nitride layer 116 (GAN:C) over 15 …

FIG. 10

FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the gallium nitride layer 118 to a 40 thickness 144. In one …

FIG. 11

FIG. 11. 50 In one example, the process 1100 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At …

FIG. 12

FIG. 12. In one example, the process 1200 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. In …

FIG. 13

FIG. 13 at 422 using no p-type dopants to form the 65 gallium nitride interlayer 123 over the aluminum nitride layer 120. In one example, the growth …

FIG. 14

FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed using magnesium or other p-type dopants that deposits the p-doped gallium …

FIG. 15

FIG. 15 above) using no p-type dopants to form the gallium nitride interlayer 225 over the p-doped gallium nitride layer 124, and forming the enhancement mode …

FIG. 16

FIG. 16 shows one example, in which an etch process 1600 is performed using a patterned etch mask 1602 to pattern exposed portions of the layers 123, 124 and …

FIG. 17

FIG. 17 is a perspective view of a packaged electronic device fabricated according to the method of

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 18 dependent

1
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is over the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the second gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the third gallium nitride layer has a second peak p-type dopant concentration that is more than 10 times greater than the ﬁrst peak p-type dopant concentration.
1. 2
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 50 nm or less.
2. 3
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 10-20 nm.
3. 4
  Dependent← claim 1GaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the third gallium nitride layer is doped with magnesium (Mg).
4. 5
  Dependent← claim 1AlNAlNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 6
  Dependent← claim 1enhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact is directly on the third gallium nitride layer.
6. 7
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a fourth gallium nitride layer on the third gallium nitride layer, the fourth gallium nitride layer having a third peak p-type dopant concentration that is less than 0.1 times the second peak p-type dopant concentration, wherein the gate contact is directly on the fourth gallium nitride layer.
7. 13
  Dependent← claim 1gate contact metalenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact includes aluminum or copper.
8. 15
  Dependent← claim 1GaNGaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
9. 17
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
10. 18
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer.
8
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is directly on the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the third gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the second gallium nitride layer has a second peak p-type dopant concentration that is more than times greater than the ﬁrst peak p-type dopant concen-tration.
1. 9
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 50 nm or less.
2. 10
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 10-20 nm.
3. 11
  Dependent← claim 8GaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the second gallium nitride layer is doped with magnesium (Mg).
4. 12
  Dependent← claim 8AlNAlNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 14
  Dependent← claim 8gate contact metalenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the gate contact includes aluminum or copper.
6. 16
  Dependent← claim 8GaNGaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
7. 19
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
8. 20
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer. ∗ ∗ ∗ ∗ ∗

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
second GaN layer (interlayer) first peak p-type dopant concentration upper bound	100000000000000000 atoms/cm3	GaN
third GaN layer peak p-type dopant concentration relative to interlayer	—	GaN
second GaN layer thickness upper bound	50 nm	GaN
second GaN layer thickness range	—	GaN
AlN buffer layer thickness	—	AlN
carbon doped GaN layer thickness	—	GaN:C
UID GaN layer thickness	—	GaN
UID GaN layer carbon doping concentration	20000000000000000 atoms/cm3	GaN
carbon doped GaN layer carbon concentration	10000000000000000000 atoms/cm3	GaN:C
Temperature	930–1050 °C	—
Thickness	300–600 nm	—
Thickness	1.4–1.8 µm	—
Thickness	1.4–2 µm	—
Thickness	0.5–2 µm	—
Thickness	0.1–0.5 µm	—
Thickness	10–30 nm	—
Thickness	10–20 nm	—
Thickness	50–200 nm	—
Thickness	60–70 nm	—
Temperature	1000–1150 °C	—
Temperature	900–1100 °C	—
Temperature	1000–1100 °C	—
Thickness	1–2.5 µm	—
Temperature	900–1050 °C	—
Temperature	950–1050 °C	—
Thickness	70–80 nm	—

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 27

US 7,898,002 B27,898,002 B2 * 3/2011 Hikita................. H01L 29/1066examiner
US 8,076,698 B28,076,698 B2 * 12/2011 Ueda..................... H01L 29/739examiner
JP 2015115371 AJP 2015115371 A 6/2015
US 10,797,168 B110,797,168 B1 * 10/2020 Moens.............. H01L 29/66462examiner
US 2007/0278521 A12007/0278521 A1 * 12/2007 Ishida.................. H10D 64/602examiner
US 2008/0149965 A12008/0149965 A1 * 6/2008 Kaibara................ H01L 29/432examiner
US 2008/0210988 A12008/0210988 A1 9/2008 Tynam
US 2009/0194790 A12009/0194790 A1 8/2009 Sato et al.
US 2010/0258841 A12010/0258841 A1 * 10/2010 Lidow............... H01L 29/66462examiner
US 2013/0146890 A12013/0146890 A1 * 6/2013 Hwang.............. H10D 30/4755examiner
US 2014/0302673 A12014/0302673 A1 * 10/2014 Kondo.............. H01L 21/28575examiner
US 2014/0327011 A12014/0327011 A1 11/2014 Pendharkar et al.
US 2015/0236121 A12015/0236121 A1 * 8/2015 Chiu.................... H10D 64/685examiner
US 2016/0218202 A12016/0218202 A1 7/2016 Fareed et al.
US 2016/0293596 A12016/0293596 A1 10/2016 Fareed et al.
US 2016/0359005 A12016/0359005 A1 * 12/2016 Hu........................ H01L 29/365examiner
US 2017/0186859 A12017/0186859 A1 6/2017 Haider et al.
US 2018/0151712 A12018/0151712 A1 * 5/2018 Ningaraju........... H01L 29/7787examiner
US 2018/0166565 A12018/0166565 A1 * 6/2018 Chen.................... H10D 30/015examiner
US 2018/0323297 A12018/0323297 A1 11/2018 Suh et al.
US 2019/0181240 A12019/0181240 A1 6/2019 Fareed et al.
US 2019/0319111 A12019/0319111 A1 10/2019 Suh et al.
US 2020/0044067 A12020/0044067 A1 2/2020 Banerjee et al.
US 2020/0185499 A12020/0185499 A1 6/2020 Lee et al.
US 2020/0185514 A12020/0185514 A1 * 6/2020 Chen................... H01L 29/7786examiner
US 2020/0203520 A12020/0203520 A1 6/2020 Dellas et al.
US 2020/0303535 A12020/0303535 A1 9/2020 Joh et al.

Cited non-patent literature · 1

PCT International Search Report dated Jan. 20, 2022. German Office Action for Corresponding Application No. 1120210057324, dated Aug. 20, 2024.

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 is a partial sectional side elevation view of an electronic device with an enhancement mode GaN transistor gate structure having a substantially undoped …

FIG. 2

FIG. 2 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 3

FIG. 3 is a partial sectional side elevation view of another electronic device with an enhancement mode GaN transistor gate structure having a substantially …

FIG. 4

FIG. 4.

FIG. 5

FIGS. 5-16 are partial sectional side elevation views of the electronic device of

FIG. 6

FIG. 6 shows one example, in which an epitaxial deposition process 600 is performed that deposits the ﬁrst aluminum gallium nitride sublayer 111 over the …

FIG. 7

FIG. 7 shows one example, in which a second epitaxial deposition process 700 is performed that deposits the second aluminum gallium nitride sublayer 112 with …

FIG. 8

FIG. 8 shows one example, in which a third epitaxial deposition process 800 is performed that deposits the third aluminum gallium nitride sublayer 113 with an …

FIG. 9

FIG. 9 shows one example, in which an epitaxial deposition process 900 is performed that depos- its the carbon doped gallium nitride layer 116 (GAN:C) over 15 …

FIG. 10

FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the gallium nitride layer 118 to a 40 thickness 144. In one …

FIG. 11

FIG. 11. 50 In one example, the process 1100 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At …

FIG. 12

FIG. 12. In one example, the process 1200 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. In …

FIG. 13

FIG. 13 at 422 using no p-type dopants to form the 65 gallium nitride interlayer 123 over the aluminum nitride layer 120. In one example, the growth …

FIG. 14

FIG. 14 shows one example, in which an epitaxial deposition process 1400 is performed using magnesium or other p-type dopants that deposits the p-doped gallium …

FIG. 15

FIG. 15 above) using no p-type dopants to form the gallium nitride interlayer 225 over the p-doped gallium nitride layer 124, and forming the enhancement mode …

FIG. 16

FIG. 16 shows one example, in which an etch process 1600 is performed using a patterned etch mask 1602 to pattern exposed portions of the layers 123, 124 and …

FIG. 17

FIG. 17 is a perspective view of a packaged electronic device fabricated according to the method of

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

2 independent · 18 dependent

1
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is over the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the second gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the third gallium nitride layer has a second peak p-type dopant concentration that is more than 10 times greater than the ﬁrst peak p-type dopant concentration.
1. 2
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 50 nm or less.
2. 3
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the second gallium nitride layer has a thickness of 10-20 nm.
3. 4
  Dependent← claim 1GaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the third gallium nitride layer is doped with magnesium (Mg).
4. 5
  Dependent← claim 1AlNAlNAlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 6
  Dependent← claim 1enhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact is directly on the third gallium nitride layer.
6. 7
  Dependent← claim 1GaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, further including: a fourth gallium nitride layer on the third gallium nitride layer, the fourth gallium nitride layer having a third peak p-type dopant concentration that is less than 0.1 times the second peak p-type dopant concentration, wherein the gate contact is directly on the fourth gallium nitride layer.
7. 13
  Dependent← claim 1gate contact metalenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the gate contact includes aluminum or copper.
8. 15
  Dependent← claim 1GaNGaNMgenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
9. 17
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
10. 18
  Dependent← claim 1AlGaNenhancement mode GaN transistor (interlayer below p-GaN, claim 1 topology)
  The electronic device of claim 1, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer.
8
IndependentGaNGaNGaNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
An electronic device, comprising: a substrate; a buffer structure over the substrate; a ﬁrst gallium nitride layer over the buffer structure; an aluminum gallium nitride layer on the ﬁrst gallium nitride layer; a gate structure having a second gallium nitride layer, a third gallium nitride layer, and a gate contact, wherein: the second gallium nitride layer is directly on the aluminum gallium nitride layer; the third gallium nitride layer is directly on the second gallium nitride layer; and the gate contact is directly on the third gallium nitride layer; a drain contact spaced apart from the gate contact; and a source contact spaced apart from the gate contact and from the drain contact; wherein the third gallium nitride layer has a ﬁrst peak p-type dopant concentration less than 1×1017 atoms/cm3; and wherein the second gallium nitride layer has a second peak p-type dopant concentration that is more than times greater than the ﬁrst peak p-type dopant concen-tration.
1. 9
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 50 nm or less.
2. 10
  Dependent← claim 8GaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the third gallium nitride layer has a thickness of 10-20 nm.
3. 11
  Dependent← claim 8GaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the second gallium nitride layer is doped with magnesium (Mg).
4. 12
  Dependent← claim 8AlNAlNAlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, further including: a ﬁrst aluminum nitride layer disposed between the ﬁrst gallium nitride layer and the aluminum gallium nitride layer; a second aluminum nitride layer disposed over the substrate; and a second aluminum gallium nitride layer disposed over the second aluminum nitride layer.
5. 14
  Dependent← claim 8gate contact metalenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the gate contact includes aluminum or copper.
6. 16
  Dependent← claim 8GaNGaNMgenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein p-type dopants of the second gallium nitride layer and the third gallium nitride layer include magnesium (Mg).
7. 19
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein the buffer structure includes: a ﬁrst sublayer of a ﬁrst thickness and a ﬁrst aluminum concentration; a second sublayer of a second thickness and a second aluminum concentration contacting and overlaying the ﬁrst sublayer, wherein the second thickness is greater than the ﬁrst thickness, and wherein the second alumi-num concentration is less than the ﬁrst aluminum concentration; and a third sublayer of a third thickness and a third aluminum concentration contacting and overlaying the second sublayer, wherein the third thickness is greater than the second thickness, and wherein the third aluminum concentration is less than the second aluminum con-centration.
8. 20
  Dependent← claim 8AlGaNenhancement mode GaN transistor (p-GaN below interlayer, claim 8 topology)
  The electronic device of claim 8, wherein: a bottom surface of the drain contact is disposed within the aluminum gallium nitride layer; and a bottom surface of the source contact is disposed within the aluminum gallium nitride layer. ∗ ∗ ∗ ∗ ∗

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
second GaN layer (interlayer) first peak p-type dopant concentration upper bound	100000000000000000 atoms/cm3	GaN
third GaN layer peak p-type dopant concentration relative to interlayer	—	GaN
second GaN layer thickness upper bound	50 nm	GaN
second GaN layer thickness range	—	GaN
AlN buffer layer thickness	—	AlN
carbon doped GaN layer thickness	—	GaN:C
UID GaN layer thickness	—	GaN
UID GaN layer carbon doping concentration	20000000000000000 atoms/cm3	GaN
carbon doped GaN layer carbon concentration	10000000000000000000 atoms/cm3	GaN:C
Temperature	930–1050 °C	—
Thickness	300–600 nm	—
Thickness	1.4–1.8 µm	—
Thickness	1.4–2 µm	—
Thickness	0.5–2 µm	—
Thickness	0.1–0.5 µm	—
Thickness	10–30 nm	—
Thickness	10–20 nm	—
Thickness	50–200 nm	—
Thickness	60–70 nm	—
Temperature	1000–1150 °C	—
Temperature	900–1100 °C	—
Temperature	1000–1100 °C	—
Thickness	1–2.5 µm	—
Temperature	900–1050 °C	—
Temperature	950–1050 °C	—
Thickness	70–80 nm	—

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 27

US 7,898,002 B27,898,002 B2 * 3/2011 Hikita................. H01L 29/1066examiner
US 8,076,698 B28,076,698 B2 * 12/2011 Ueda..................... H01L 29/739examiner
JP 2015115371 AJP 2015115371 A 6/2015
US 10,797,168 B110,797,168 B1 * 10/2020 Moens.............. H01L 29/66462examiner
US 2007/0278521 A12007/0278521 A1 * 12/2007 Ishida.................. H10D 64/602examiner
US 2008/0149965 A12008/0149965 A1 * 6/2008 Kaibara................ H01L 29/432examiner
US 2008/0210988 A12008/0210988 A1 9/2008 Tynam
US 2009/0194790 A12009/0194790 A1 8/2009 Sato et al.
US 2010/0258841 A12010/0258841 A1 * 10/2010 Lidow............... H01L 29/66462examiner
US 2013/0146890 A12013/0146890 A1 * 6/2013 Hwang.............. H10D 30/4755examiner
US 2014/0302673 A12014/0302673 A1 * 10/2014 Kondo.............. H01L 21/28575examiner
US 2014/0327011 A12014/0327011 A1 11/2014 Pendharkar et al.
US 2015/0236121 A12015/0236121 A1 * 8/2015 Chiu.................... H10D 64/685examiner
US 2016/0218202 A12016/0218202 A1 7/2016 Fareed et al.
US 2016/0293596 A12016/0293596 A1 10/2016 Fareed et al.
US 2016/0359005 A12016/0359005 A1 * 12/2016 Hu........................ H01L 29/365examiner
US 2017/0186859 A12017/0186859 A1 6/2017 Haider et al.
US 2018/0151712 A12018/0151712 A1 * 5/2018 Ningaraju........... H01L 29/7787examiner
US 2018/0166565 A12018/0166565 A1 * 6/2018 Chen.................... H10D 30/015examiner
US 2018/0323297 A12018/0323297 A1 11/2018 Suh et al.
US 2019/0181240 A12019/0181240 A1 6/2019 Fareed et al.
US 2019/0319111 A12019/0319111 A1 10/2019 Suh et al.
US 2020/0044067 A12020/0044067 A1 2/2020 Banerjee et al.
US 2020/0185499 A12020/0185499 A1 6/2020 Lee et al.
US 2020/0185514 A12020/0185514 A1 * 6/2020 Chen................... H01L 29/7786examiner
US 2020/0203520 A12020/0203520 A1 6/2020 Dellas et al.
US 2020/0303535 A12020/0303535 A1 9/2020 Joh et al.

Cited non-patent literature · 1

PCT International Search Report dated Jan. 20, 2022. German Office Action for Corresponding Application No. 1120210057324, dated Aug. 20, 2024.

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

ELECTRONIC DEVICE WITH ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR, AND METHOD OF MAKING SAME

Drawings

Claims

Device structures

Materials

Process steps

Characterization

Reported properties

Cited prior art

Why these are connected

Drawings

Claims

Device structures

Materials

Process steps

Characterization

Reported properties

Cited prior art

Why these are connected

Drawings

Claims

Device structures

Materials

Process steps

Characterization

Reported properties

Cited prior art

Why these are connected

Drawings

Claims

Device structures

Materials

Process steps

Characterization

Reported properties

Cited prior art

Why these are connected