Patent
US 11,031,493DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE
Mayank SHRIVASTAVA
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,031,493Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary schematic of an AlGaN/GaN HEMT device. [30]
FIG. 2 illustrates the impact of silicon doping concentration on breakdown voltage of the device, when the acceptor trap concentration is fixed. [31] FIGs. 3A …
FIG. 3A illustrates that the free hole density in the GaN buffer that is induced by acceptor traps, is compensated by silicon doping, thus maintaining the buffer …
FIG. 5B illustrates the relation of the electric field profile near the drain edge with silicon doping concentration and ionised acceptor trap density. [35]
FIG. 6 illustrates a relative comparison of influence of silicon doping concentration with that of donor trap concentration on breakdown voltage and source to …
FIG. 7B illustrates an increased leakage current for the cases: when silicon doping is comparable or greater than acceptor trap concentration; and when …
FIG. 9A also illustrates an exemplary structure used for simulating buffer leakage current. [94] In another embodiment, the buffer leakage is orders of magnitude …
FIG. 11 B illustrates the effect of increasing silicon doping concentration on vertical electric field distribution, in the case of the proposed modified doping …
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
FIG. 13B, when t C-C hannel is increa s ed up to appr ox imately 400 nm, a controlled leakage current is observed, which increases exponentially as t C-C hanne …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor with improved breakdown voltage, said transistor having an A l GaN barrier layer and a GaN buffer layer, wherein compensation C- doping is performed in said GaN buffer layer for controlling acceptor trap concentration in said GaN buffer layer, and thereafter an intentional n-type doping is performed in said G aN buffer layer for controlling donor trap concentration in said GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance. Currently amended
The transistor as claimed in claim 1, wherein said transistor is a HEMT transistor. Original
The transistor as claimed in claim 1, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The transistor as claimed in claim 1, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
The transistor as claimed in claim 1, wherein said acceptor trap concentration is minimized while maintaining high breakdown voltage. Original
The transistor as claimed in claim 1, wherein the compensation C-doping is optimized based on any or a combination of Source/Drain leakage and breakdown voltage. Previously presented
The transistor as claimed in claim 1, wherein channel thickness of said transistor is controlled based on impact of the intentional n-type doping on channel mobility. Currently amended
The transistor as claimed in claim 1, wherein said compensation C-doping is optimally reduced so as to not impact the improved breakdown voltage beyond a defined threshold. Previously presented
. Canceled
. Canceled
A method for improving breakdown voltage in a transistor, the method comprising: providing an AlGaN barrier layer and a GaN buffer layer in the transistor; performing compensation C-doping and intentional n-type doping in the GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance; and controlling acceptor trap concentration in [[said]]the GaN buffer layer based on the compensation C-doping and controlling donor trap concentration based on the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the method further comprises: upon the intentional n-type [[of]]doping, changing parasitic electron and hole density in the GaN buffer layer; and modulating, as an ionized dopant, space charge distribution and vertical electrical field in the GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein the improvement in breakdown voltage is dependent on relative concentration of acceptor traps and the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
AlGaN/GaN HEMT
AlGaN/GaN HEMT (exemplary design parameters)
Materials described outside the worked examples.
AlGaN barrier layer
AlGaN
GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source to gate distance (LSG) | 1 µm | — |
gate length (LGate) | 0.7 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,031,493Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary schematic of an AlGaN/GaN HEMT device. [30]
FIG. 2 illustrates the impact of silicon doping concentration on breakdown voltage of the device, when the acceptor trap concentration is fixed. [31] FIGs. 3A …
FIG. 3A illustrates that the free hole density in the GaN buffer that is induced by acceptor traps, is compensated by silicon doping, thus maintaining the buffer …
FIG. 5B illustrates the relation of the electric field profile near the drain edge with silicon doping concentration and ionised acceptor trap density. [35]
FIG. 6 illustrates a relative comparison of influence of silicon doping concentration with that of donor trap concentration on breakdown voltage and source to …
FIG. 7B illustrates an increased leakage current for the cases: when silicon doping is comparable or greater than acceptor trap concentration; and when …
FIG. 9A also illustrates an exemplary structure used for simulating buffer leakage current. [94] In another embodiment, the buffer leakage is orders of magnitude …
FIG. 11 B illustrates the effect of increasing silicon doping concentration on vertical electric field distribution, in the case of the proposed modified doping …
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
FIG. 13B, when t C-C hannel is increa s ed up to appr ox imately 400 nm, a controlled leakage current is observed, which increases exponentially as t C-C hanne …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor with improved breakdown voltage, said transistor having an A l GaN barrier layer and a GaN buffer layer, wherein compensation C- doping is performed in said GaN buffer layer for controlling acceptor trap concentration in said GaN buffer layer, and thereafter an intentional n-type doping is performed in said G aN buffer layer for controlling donor trap concentration in said GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance. Currently amended
The transistor as claimed in claim 1, wherein said transistor is a HEMT transistor. Original
The transistor as claimed in claim 1, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The transistor as claimed in claim 1, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
The transistor as claimed in claim 1, wherein said acceptor trap concentration is minimized while maintaining high breakdown voltage. Original
The transistor as claimed in claim 1, wherein the compensation C-doping is optimized based on any or a combination of Source/Drain leakage and breakdown voltage. Previously presented
The transistor as claimed in claim 1, wherein channel thickness of said transistor is controlled based on impact of the intentional n-type doping on channel mobility. Currently amended
The transistor as claimed in claim 1, wherein said compensation C-doping is optimally reduced so as to not impact the improved breakdown voltage beyond a defined threshold. Previously presented
. Canceled
. Canceled
A method for improving breakdown voltage in a transistor, the method comprising: providing an AlGaN barrier layer and a GaN buffer layer in the transistor; performing compensation C-doping and intentional n-type doping in the GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance; and controlling acceptor trap concentration in [[said]]the GaN buffer layer based on the compensation C-doping and controlling donor trap concentration based on the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the method further comprises: upon the intentional n-type [[of]]doping, changing parasitic electron and hole density in the GaN buffer layer; and modulating, as an ionized dopant, space charge distribution and vertical electrical field in the GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein the improvement in breakdown voltage is dependent on relative concentration of acceptor traps and the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
AlGaN/GaN HEMT
AlGaN/GaN HEMT (exemplary design parameters)
Materials described outside the worked examples.
AlGaN barrier layer
AlGaN
GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source to gate distance (LSG) | 1 µm | — |
gate length (LGate) | 0.7 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,031,493Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary schematic of an AlGaN/GaN HEMT device. [30]
FIG. 2 illustrates the impact of silicon doping concentration on breakdown voltage of the device, when the acceptor trap concentration is fixed. [31] FIGs. 3A …
FIG. 3A illustrates that the free hole density in the GaN buffer that is induced by acceptor traps, is compensated by silicon doping, thus maintaining the buffer …
FIG. 5B illustrates the relation of the electric field profile near the drain edge with silicon doping concentration and ionised acceptor trap density. [35]
FIG. 6 illustrates a relative comparison of influence of silicon doping concentration with that of donor trap concentration on breakdown voltage and source to …
FIG. 7B illustrates an increased leakage current for the cases: when silicon doping is comparable or greater than acceptor trap concentration; and when …
FIG. 9A also illustrates an exemplary structure used for simulating buffer leakage current. [94] In another embodiment, the buffer leakage is orders of magnitude …
FIG. 11 B illustrates the effect of increasing silicon doping concentration on vertical electric field distribution, in the case of the proposed modified doping …
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
FIG. 13B, when t C-C hannel is increa s ed up to appr ox imately 400 nm, a controlled leakage current is observed, which increases exponentially as t C-C hanne …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor with improved breakdown voltage, said transistor having an A l GaN barrier layer and a GaN buffer layer, wherein compensation C- doping is performed in said GaN buffer layer for controlling acceptor trap concentration in said GaN buffer layer, and thereafter an intentional n-type doping is performed in said G aN buffer layer for controlling donor trap concentration in said GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance. Currently amended
The transistor as claimed in claim 1, wherein said transistor is a HEMT transistor. Original
The transistor as claimed in claim 1, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The transistor as claimed in claim 1, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
The transistor as claimed in claim 1, wherein said acceptor trap concentration is minimized while maintaining high breakdown voltage. Original
The transistor as claimed in claim 1, wherein the compensation C-doping is optimized based on any or a combination of Source/Drain leakage and breakdown voltage. Previously presented
The transistor as claimed in claim 1, wherein channel thickness of said transistor is controlled based on impact of the intentional n-type doping on channel mobility. Currently amended
The transistor as claimed in claim 1, wherein said compensation C-doping is optimally reduced so as to not impact the improved breakdown voltage beyond a defined threshold. Previously presented
. Canceled
. Canceled
A method for improving breakdown voltage in a transistor, the method comprising: providing an AlGaN barrier layer and a GaN buffer layer in the transistor; performing compensation C-doping and intentional n-type doping in the GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance; and controlling acceptor trap concentration in [[said]]the GaN buffer layer based on the compensation C-doping and controlling donor trap concentration based on the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the method further comprises: upon the intentional n-type [[of]]doping, changing parasitic electron and hole density in the GaN buffer layer; and modulating, as an ionized dopant, space charge distribution and vertical electrical field in the GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein the improvement in breakdown voltage is dependent on relative concentration of acceptor traps and the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
AlGaN/GaN HEMT
AlGaN/GaN HEMT (exemplary design parameters)
Materials described outside the worked examples.
AlGaN barrier layer
AlGaN
GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source to gate distance (LSG) | 1 µm | — |
gate length (LGate) | 0.7 µm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,031,493Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates an exemplary schematic of an AlGaN/GaN HEMT device. [30]
FIG. 2 illustrates the impact of silicon doping concentration on breakdown voltage of the device, when the acceptor trap concentration is fixed. [31] FIGs. 3A …
FIG. 3A illustrates that the free hole density in the GaN buffer that is induced by acceptor traps, is compensated by silicon doping, thus maintaining the buffer …
FIG. 5B illustrates the relation of the electric field profile near the drain edge with silicon doping concentration and ionised acceptor trap density. [35]
FIG. 6 illustrates a relative comparison of influence of silicon doping concentration with that of donor trap concentration on breakdown voltage and source to …
FIG. 7B illustrates an increased leakage current for the cases: when silicon doping is comparable or greater than acceptor trap concentration; and when …
FIG. 9A also illustrates an exemplary structure used for simulating buffer leakage current. [94] In another embodiment, the buffer leakage is orders of magnitude …
FIG. 11 B illustrates the effect of increasing silicon doping concentration on vertical electric field distribution, in the case of the proposed modified doping …
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
FIG. 13B, when t C-C hannel is increa s ed up to appr ox imately 400 nm, a controlled leakage current is observed, which increases exponentially as t C-C hanne …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor with improved breakdown voltage, said transistor having an A l GaN barrier layer and a GaN buffer layer, wherein compensation C- doping is performed in said GaN buffer layer for controlling acceptor trap concentration in said GaN buffer layer, and thereafter an intentional n-type doping is performed in said G aN buffer layer for controlling donor trap concentration in said GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance. Currently amended
The transistor as claimed in claim 1, wherein said transistor is a HEMT transistor. Original
The transistor as claimed in claim 1, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The transistor as claimed in claim 1, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
The transistor as claimed in claim 1, wherein said acceptor trap concentration is minimized while maintaining high breakdown voltage. Original
The transistor as claimed in claim 1, wherein the compensation C-doping is optimized based on any or a combination of Source/Drain leakage and breakdown voltage. Previously presented
The transistor as claimed in claim 1, wherein channel thickness of said transistor is controlled based on impact of the intentional n-type doping on channel mobility. Currently amended
The transistor as claimed in claim 1, wherein said compensation C-doping is optimally reduced so as to not impact the improved breakdown voltage beyond a defined threshold. Previously presented
. Canceled
. Canceled
A method for improving breakdown voltage in a transistor, the method comprising: providing an AlGaN barrier layer and a GaN buffer layer in the transistor; performing compensation C-doping and intentional n-type doping in the GaN buffer layer, wherein the intentional n-type doping comprises Si-doping, and wherein the Si-doping is optimized based on dynamic ON resistance; and controlling acceptor trap concentration in [[said]]the GaN buffer layer based on the compensation C-doping and controlling donor trap concentration based on the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the method further comprises: upon the intentional n-type [[of]]doping, changing parasitic electron and hole density in the GaN buffer layer; and modulating, as an ionized dopant, space charge distribution and vertical electrical field in the GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein the improvement in breakdown voltage is dependent on relative concentration of acceptor traps and the intentional n-type doping. Currently amended
The method as claimed in claim 11, wherein the intentional n- type doping is performed based on free hole density and ionized acceptor trap density in said GaN buffer layer. Currently amended
The method as claimed in claim 11, wherein a region where the intentional n-type doping is performed at least partially overlaps with an area where the compensation C-doping is performed. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
AlGaN/GaN HEMT
AlGaN/GaN HEMT (exemplary design parameters)
Materials described outside the worked examples.
AlGaN barrier layer
AlGaN
GaN buffer layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12B illustrates the effect of thickness of the silicon doped region on vertical field profile, extracted at the onset of avalanche phenomenon. [46] FIG s. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
source to gate distance (LSG) | 1 µm | — |
gate length (LGate) | 0.7 µm | — |
Related documents with shared materials, methods, properties, or citations.
carbon dopant
C
silicon dopant
Si
gate to drain distance (LGD) |
| 5 µm |
| — |
field plate length (LFP) | 0.6 µm | — |
channel thickness (tChannel) | 35 nm | — |
carbon doping region thickness (tC-Doped) | 1.5 µm | C |
GaN buffer unintentional n-type doping concentration | 1000000000000000 cm⁻³ | GaN |
carbon dopant
C
silicon dopant
Si
gate to drain distance (LGD) |
| 5 µm |
| — |
field plate length (LFP) | 0.6 µm | — |
channel thickness (tChannel) | 35 nm | — |
carbon doping region thickness (tC-Doped) | 1.5 µm | C |
GaN buffer unintentional n-type doping concentration | 1000000000000000 cm⁻³ | GaN |
carbon dopant
C
silicon dopant
Si
gate to drain distance (LGD) |
| 5 µm |
| — |
field plate length (LFP) | 0.6 µm | — |
channel thickness (tChannel) | 35 nm | — |
carbon doping region thickness (tC-Doped) | 1.5 µm | C |
GaN buffer unintentional n-type doping concentration | 1000000000000000 cm⁻³ | GaN |
carbon dopant
C
silicon dopant
Si
gate to drain distance (LGD) |
| 5 µm |
| — |
field plate length (LFP) | 0.6 µm | — |
channel thickness (tChannel) | 35 nm | — |
carbon doping region thickness (tC-Doped) | 1.5 µm | C |
GaN buffer unintentional n-type doping concentration | 1000000000000000 cm⁻³ | GaN |