Patent
US 12,261,206 B2METHOD OF FORMING VIAS IN A GAN/DIAMOND WAFER
Won Sang Lee
RFHIC Corporation, Anyang-si (KR)·Mar. 25, 2025·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,261,206 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 show an exemplary process for fabricating a wafer that includes two diamond layers and a III-Nitride layer according to embodiments of the present …
FIG. 2B shows another exemplary III-Nitride layer 106-2 that includes only one GaN buffer layer 106-22. In embodiments, the protection layer 108 may protect …
FIG. 3 shows a process of bonding a carrier wafer 110 to the wafer 109 according to embodiments of the present disclosure. As depicted, the carrier wafer 110 …
FIG. 4 shows a wafer 118 that include the silicon carrier wafer 110 bonded to the wafer 109 by the glass bonding process, where the bonding layer 115 may be …
FIG. 5, the silicon sub- strate 102, AlN layer 104 and a portion of the III-Nitride layer 106 in the wafer 118 may be removed to form the wafer 120. In …
FIG. 6, an intermediate layer 124 may be formed on the III-Nitride layer 107, where the intermediate layer 124 may include a first intermediate layer and a …
FIG. 7. In embodiments, the diamond layer 128 may be formed by 10 chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. …
FIG. 8, the wafer 130 may include a diamond layer 132 that has a top surface with enhanced flatness by the lapping process. In embodiments, the silicon carrier …
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
FIG. 10.
FIG. 11 shows a wafer 150 that includes the support wafer 140 bonded to the wafer 136 by the glass bonding process. As discussed above in conjunction with
FIG. 12 to fabricate HEMTs according to embodiments of the present disclosure.
FIGS. 13-17 show an exemplary process for device pro- cessing the wafer in
FIG. 14, the wafer 174 may include one or more vias 176 formed by a laser drilling technique or any other suitable technique. In the conven- tional techniques, …
FIG. 15, a chemical or electrochemical gold plating technique may be used to deposit a thin layer of gold 180 on the metal layer 172 and in a top portion of …
FIG. 16. In embodiments, the bottom surface of the diamond layer 132 may be further cleaned by a dry etching technique so as to remove remaining glass material …
FIG. 17, the wafer 200 may include a metal layer 202 that is deposited on the bottom surface of the diamond layer 132 and the side surfaces of the one or more …
FIG. 18 shows a flowchart of an exemplary process for fabricating a semiconductor wafer according to embodi- ments of the present disclosure.
FIG. 19 shows a flowchart of an exemplary process for processing a semiconductor wafer according to embodi- ments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for processing a semiconductor wafer, com-prising: disposing and patterning a first metal layer on a semicon-ductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support layer, a bond-ing layer, a first diamond layer, an intermediate layer and the semiconductor layer; drilling one or more holes from the first metal layer toward the support layer to thereby form one or more vias that extend from the first metal layer into the support layer; disposing a second metal layer on the first metal layer and in a portion of the one or more vias; and removing the support layer and the bonding layer to expose a surface of the first diamond layer, wherein the support layer includes a second diamond layer, a silicon substrate, and a protection layer.
The method of claim 1, further comprising: cleaning the exposed surface of the first diamond layer.
The method of claim 1, further comprising: disposing a third metal layer on the exposed surface of the first diamond layer and a side surface of the one or more vias, wherein the third metal layer electrically contacts the second metal layer.
The method of claim 1, wherein the protection layer is formed of a material that includes one or more of SiN, poly-Si, Al₂O3, AlN and GaN.
The method of claim 1, wherein the bonding layer is formed of glass.
The method of claim 1, further comprising: prior to the step of disposing and patterning the first metal layer, forming one or more semiconductor devices in the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/diamond semiconductor wafer with through-vias
Materials described outside the worked examples.
first diamond layer
C
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 12,261,206 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 show an exemplary process for fabricating a wafer that includes two diamond layers and a III-Nitride layer according to embodiments of the present …
FIG. 2B shows another exemplary III-Nitride layer 106-2 that includes only one GaN buffer layer 106-22. In embodiments, the protection layer 108 may protect …
FIG. 3 shows a process of bonding a carrier wafer 110 to the wafer 109 according to embodiments of the present disclosure. As depicted, the carrier wafer 110 …
FIG. 4 shows a wafer 118 that include the silicon carrier wafer 110 bonded to the wafer 109 by the glass bonding process, where the bonding layer 115 may be …
FIG. 5, the silicon sub- strate 102, AlN layer 104 and a portion of the III-Nitride layer 106 in the wafer 118 may be removed to form the wafer 120. In …
FIG. 6, an intermediate layer 124 may be formed on the III-Nitride layer 107, where the intermediate layer 124 may include a first intermediate layer and a …
FIG. 7. In embodiments, the diamond layer 128 may be formed by 10 chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. …
FIG. 8, the wafer 130 may include a diamond layer 132 that has a top surface with enhanced flatness by the lapping process. In embodiments, the silicon carrier …
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
FIG. 10.
FIG. 11 shows a wafer 150 that includes the support wafer 140 bonded to the wafer 136 by the glass bonding process. As discussed above in conjunction with
FIG. 12 to fabricate HEMTs according to embodiments of the present disclosure.
FIGS. 13-17 show an exemplary process for device pro- cessing the wafer in
FIG. 14, the wafer 174 may include one or more vias 176 formed by a laser drilling technique or any other suitable technique. In the conven- tional techniques, …
FIG. 15, a chemical or electrochemical gold plating technique may be used to deposit a thin layer of gold 180 on the metal layer 172 and in a top portion of …
FIG. 16. In embodiments, the bottom surface of the diamond layer 132 may be further cleaned by a dry etching technique so as to remove remaining glass material …
FIG. 17, the wafer 200 may include a metal layer 202 that is deposited on the bottom surface of the diamond layer 132 and the side surfaces of the one or more …
FIG. 18 shows a flowchart of an exemplary process for fabricating a semiconductor wafer according to embodi- ments of the present disclosure.
FIG. 19 shows a flowchart of an exemplary process for processing a semiconductor wafer according to embodi- ments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for processing a semiconductor wafer, com-prising: disposing and patterning a first metal layer on a semicon-ductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support layer, a bond-ing layer, a first diamond layer, an intermediate layer and the semiconductor layer; drilling one or more holes from the first metal layer toward the support layer to thereby form one or more vias that extend from the first metal layer into the support layer; disposing a second metal layer on the first metal layer and in a portion of the one or more vias; and removing the support layer and the bonding layer to expose a surface of the first diamond layer, wherein the support layer includes a second diamond layer, a silicon substrate, and a protection layer.
The method of claim 1, further comprising: cleaning the exposed surface of the first diamond layer.
The method of claim 1, further comprising: disposing a third metal layer on the exposed surface of the first diamond layer and a side surface of the one or more vias, wherein the third metal layer electrically contacts the second metal layer.
The method of claim 1, wherein the protection layer is formed of a material that includes one or more of SiN, poly-Si, Al₂O3, AlN and GaN.
The method of claim 1, wherein the bonding layer is formed of glass.
The method of claim 1, further comprising: prior to the step of disposing and patterning the first metal layer, forming one or more semiconductor devices in the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/diamond semiconductor wafer with through-vias
Materials described outside the worked examples.
first diamond layer
C
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,206 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 show an exemplary process for fabricating a wafer that includes two diamond layers and a III-Nitride layer according to embodiments of the present …
FIG. 2B shows another exemplary III-Nitride layer 106-2 that includes only one GaN buffer layer 106-22. In embodiments, the protection layer 108 may protect …
FIG. 3 shows a process of bonding a carrier wafer 110 to the wafer 109 according to embodiments of the present disclosure. As depicted, the carrier wafer 110 …
FIG. 4 shows a wafer 118 that include the silicon carrier wafer 110 bonded to the wafer 109 by the glass bonding process, where the bonding layer 115 may be …
FIG. 5, the silicon sub- strate 102, AlN layer 104 and a portion of the III-Nitride layer 106 in the wafer 118 may be removed to form the wafer 120. In …
FIG. 6, an intermediate layer 124 may be formed on the III-Nitride layer 107, where the intermediate layer 124 may include a first intermediate layer and a …
FIG. 7. In embodiments, the diamond layer 128 may be formed by 10 chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. …
FIG. 8, the wafer 130 may include a diamond layer 132 that has a top surface with enhanced flatness by the lapping process. In embodiments, the silicon carrier …
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
FIG. 10.
FIG. 11 shows a wafer 150 that includes the support wafer 140 bonded to the wafer 136 by the glass bonding process. As discussed above in conjunction with
FIG. 12 to fabricate HEMTs according to embodiments of the present disclosure.
FIGS. 13-17 show an exemplary process for device pro- cessing the wafer in
FIG. 14, the wafer 174 may include one or more vias 176 formed by a laser drilling technique or any other suitable technique. In the conven- tional techniques, …
FIG. 15, a chemical or electrochemical gold plating technique may be used to deposit a thin layer of gold 180 on the metal layer 172 and in a top portion of …
FIG. 16. In embodiments, the bottom surface of the diamond layer 132 may be further cleaned by a dry etching technique so as to remove remaining glass material …
FIG. 17, the wafer 200 may include a metal layer 202 that is deposited on the bottom surface of the diamond layer 132 and the side surfaces of the one or more …
FIG. 18 shows a flowchart of an exemplary process for fabricating a semiconductor wafer according to embodi- ments of the present disclosure.
FIG. 19 shows a flowchart of an exemplary process for processing a semiconductor wafer according to embodi- ments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for processing a semiconductor wafer, com-prising: disposing and patterning a first metal layer on a semicon-ductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support layer, a bond-ing layer, a first diamond layer, an intermediate layer and the semiconductor layer; drilling one or more holes from the first metal layer toward the support layer to thereby form one or more vias that extend from the first metal layer into the support layer; disposing a second metal layer on the first metal layer and in a portion of the one or more vias; and removing the support layer and the bonding layer to expose a surface of the first diamond layer, wherein the support layer includes a second diamond layer, a silicon substrate, and a protection layer.
The method of claim 1, further comprising: cleaning the exposed surface of the first diamond layer.
The method of claim 1, further comprising: disposing a third metal layer on the exposed surface of the first diamond layer and a side surface of the one or more vias, wherein the third metal layer electrically contacts the second metal layer.
The method of claim 1, wherein the protection layer is formed of a material that includes one or more of SiN, poly-Si, Al₂O3, AlN and GaN.
The method of claim 1, wherein the bonding layer is formed of glass.
The method of claim 1, further comprising: prior to the step of disposing and patterning the first metal layer, forming one or more semiconductor devices in the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/diamond semiconductor wafer with through-vias
Materials described outside the worked examples.
first diamond layer
C
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,261,206 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-12 show an exemplary process for fabricating a wafer that includes two diamond layers and a III-Nitride layer according to embodiments of the present …
FIG. 2B shows another exemplary III-Nitride layer 106-2 that includes only one GaN buffer layer 106-22. In embodiments, the protection layer 108 may protect …
FIG. 3 shows a process of bonding a carrier wafer 110 to the wafer 109 according to embodiments of the present disclosure. As depicted, the carrier wafer 110 …
FIG. 4 shows a wafer 118 that include the silicon carrier wafer 110 bonded to the wafer 109 by the glass bonding process, where the bonding layer 115 may be …
FIG. 5, the silicon sub- strate 102, AlN layer 104 and a portion of the III-Nitride layer 106 in the wafer 118 may be removed to form the wafer 120. In …
FIG. 6, an intermediate layer 124 may be formed on the III-Nitride layer 107, where the intermediate layer 124 may include a first intermediate layer and a …
FIG. 7. In embodiments, the diamond layer 128 may be formed by 10 chemical vapor deposition (CVD) technique, even though other suitable techniques may be used. …
FIG. 8, the wafer 130 may include a diamond layer 132 that has a top surface with enhanced flatness by the lapping process. In embodiments, the silicon carrier …
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
FIG. 10.
FIG. 11 shows a wafer 150 that includes the support wafer 140 bonded to the wafer 136 by the glass bonding process. As discussed above in conjunction with
FIG. 12 to fabricate HEMTs according to embodiments of the present disclosure.
FIGS. 13-17 show an exemplary process for device pro- cessing the wafer in
FIG. 14, the wafer 174 may include one or more vias 176 formed by a laser drilling technique or any other suitable technique. In the conven- tional techniques, …
FIG. 15, a chemical or electrochemical gold plating technique may be used to deposit a thin layer of gold 180 on the metal layer 172 and in a top portion of …
FIG. 16. In embodiments, the bottom surface of the diamond layer 132 may be further cleaned by a dry etching technique so as to remove remaining glass material …
FIG. 17, the wafer 200 may include a metal layer 202 that is deposited on the bottom surface of the diamond layer 132 and the side surfaces of the one or more …
FIG. 18 shows a flowchart of an exemplary process for fabricating a semiconductor wafer according to embodi- ments of the present disclosure.
FIG. 19 shows a flowchart of an exemplary process for processing a semiconductor wafer according to embodi- ments of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for processing a semiconductor wafer, com-prising: disposing and patterning a first metal layer on a semicon-ductor layer of a semiconductor wafer, wherein the semiconductor wafer includes a support layer, a bond-ing layer, a first diamond layer, an intermediate layer and the semiconductor layer; drilling one or more holes from the first metal layer toward the support layer to thereby form one or more vias that extend from the first metal layer into the support layer; disposing a second metal layer on the first metal layer and in a portion of the one or more vias; and removing the support layer and the bonding layer to expose a surface of the first diamond layer, wherein the support layer includes a second diamond layer, a silicon substrate, and a protection layer.
The method of claim 1, further comprising: cleaning the exposed surface of the first diamond layer.
The method of claim 1, further comprising: disposing a third metal layer on the exposed surface of the first diamond layer and a side surface of the one or more vias, wherein the third metal layer electrically contacts the second metal layer.
The method of claim 1, wherein the protection layer is formed of a material that includes one or more of SiN, poly-Si, Al₂O3, AlN and GaN.
The method of claim 1, wherein the bonding layer is formed of glass.
The method of claim 1, further comprising: prior to the step of disposing and patterning the first metal layer, forming one or more semiconductor devices in the semiconductor layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN/diamond semiconductor wafer with through-vias
Materials described outside the worked examples.
first diamond layer
C
silicon substrate
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 9. In embodiments, 20 the thickness of the wafer 134 may be so thin that the wafer 134 may not have sufficient mechanical strength to with- stand the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 900–1000 °C | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 39
Related documents with shared materials, methods, properties, or citations.
high electron mobility transistor (HEMT)
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