Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of an epitaxial buffer layer, a GaN channel layer and an AlyGa0.75-yN barrier layer sequentially grown on an epitaxial …
FIG. 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention after a gate electrode, a source electrode …
FIG. 3 is a schematic structural diagram of a wafer substrate etched with epitaxial buffer layer after transfer according to an embodiment of the present …
FIG. 4 is a schematic cross-sectional diagram of a lead electrode and a HEMT device with a sandwich structure prepared after through-hole etching according to …
FIG. 5 is a partial three-dimensional schematic diagram of a HEMT device with a sandwich structure according to an embodiment of the present invention; In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN-HEMT device with a sandwich structure, wherein the GaN-HEMT device com-prises an epitaxial layer and electrodes, wherein the epitaxial layer comprises a GaN channel layer and an AlyGa₁-y barrier layer, and y is 0.2 to 0.3; the GaN channel layer and the AlyGa₁-y barrier layer are arranged from top to bottom; the electrodes comprise a gate electrode, a source electrode, a drain electrode and a field plate electrode, wherein the field plate electrode and the gate electrode are respectively fab-ricated on an upper surface and a lower surface of the epitaxial layer, and the field plate electrode extends to a region beyond the epitaxial layer and is connected with the gate electrode to form the sandwich structure, and the source electrode and the drain electrode are respectively located at two ends of the epitaxial layer, wherein the method comprises following steps: (1) sequentially growing an epitaxial buffer layer, a GaN channel layer and an AlyGa₁-y barrier layer on an epitaxial silicon substrate by using MOCVD to obtain an epitaxial wafer; (2) using photoetching and ICP etching technology to prepare alignment marks required by multilayer pho-toetching steps on a surface of the epitaxial wafer to obtain etched mark points; (3) according to the etched mark points, photoetching HEMT source electrode and drain electrode patterns in corresponding regions on the surface of the epitaxial wafer, depositing Ti/Al/Ni/Au metal electrodes by using a method of electron beam evaporation coating, and then performing rapid high-temperature annealing on the epitaxial wafer to prepare a source electrode and 5 a drain electrode to form an ohmic contact electrode, wherein an annealing temperature is 830 to 850° C. and an annealing time is 30 to 60 s; (4) photoetching the epitaxial wafer with the ohmic contact electrode prepared in the step (3), covering a device region with photoresist, and then performing mesa isolation on the GaN-HEMT device region by using the method of ICP etching; (5) photoetching a gate electrode region of HEMT in corresponding region of the surface of epitaxial wafer after mesa isolation, and depositing a Ni/Au metal electrode by using the method of electron beam evapo-ration coating to prepare a gate electrode, thereby forming a Schottky electrode to obtain a wafer of the gate electrode; (6) by using a method of PECVD, growing one layer of silicon dioxide passivation film layer on the surface of the wafer with the gate electrode prepared, so as to obtain a passivation wafer; (7) bonding the passivation wafer with a bonded silicon substrate together in a metal hot-press bonding mode, wherein specific steps are as follows: depositing a Ni/Au/Sn/Au multi-metal layer on a surface of the passivation wafer where the silicon dioxide passivation film layer is grown, depositing a Ti/Au/Sn/Au multimetal layer on a surface of the bonded silicon substrate, and then adhering the two metal layers together, and putting them into a hot-press bonding machine for hot-press cementing to obtain a bonded wafer; (8) putting the bonded wafer into a mechanical thinning machine, grinding and thinning the epitaxial silicon substrate, controlling a thinning thickness, and leaving the epitaxial silicon substrate with a thickness of 30 to 50 µm, and then soaking the bonded wafer in a nitric acid/hydrofluoric acid/acetic acid mixed acid solution with a volume ratio of 3: 1: 1 to 3: 1: 2 for 5 to 10 minutes to completely remove the epitaxial silicon substrate and expose AIN of the epitaxial buffer layer; etching the exposed AIN of the epitaxial buffer layer to a C-doped high-resistance GaN layer by using ICP to obtain a wafer with the epitaxial buffer layer etched; (9) performing photoetching on the wafer with the epi-taxial buffer layer etched, and exposing an opening etching region in the corresponding regions of the source electrode, the drain electrode and the gate elec-B₂ trode, performing electrode opening etching by using ICP technology, and then depositing a Ni/Au lead electrode by using the method of the electron beam evaporation coating, and depositing the Ni/Au metal layer at a position, opposite to gate electrode, on an upper surface of the epitaxial layer at the same time, so as to prepare a field plate electrode and form an inverted GaN-HEMT device with a sandwich structure.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein the epitaxial buffer layer in the step (1) comprises 100 to 200 nm of AIN and 1 to 2 µm of C-doped high-resistance GaN layer; a thickness of the GaN channel layer is 100 to 300 nm; and a thickness of the AlyGa₁-y barrier layer is 20 to 30 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the etched mark points in the step (2) is greater than 600 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the mesa isolation in the step (4) is 100 to 200 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the silicon dioxide passivation film layer in the step (6) is 1 to 2 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a bonding air pressure in the hot-press bonding machine in the step (7) is 1E-3 to 2E-3 Pa, a bonding temperature is 280 to 300° C., a bonding pressure is 3 to 4 kBar, and a bonding time is 10 to 20 min.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein when etching the epitaxial buffer layer by ICP in the step (8), the C-doped high-resistance GaN layer remained is 0.5 to 1 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein in the Ti/Al/Ni/Au metal electrodes in the step (3), a thickness of the Ti metal layer is 10 to 20 nm, a thickness of the Al metal layer is 60 to 150 nm, a thickness of the Ni metal layer is to 60 nm, and a thickness of the Au metal layer is 50 to 100 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the Ni metal layer of the Ni/Au metal electrode in the step (5) is 30 to 100 nm, and a thickness of the Au metal layer is 50 to 100 nm. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
8 materials5 process steps
A GaN-HEMT device with a sandwich structure is prepared using: a 150 nm GaN channel layer and a 25 nm Al0.25Ga0.75N barrier layer as the epitaxial layer; an epitaxial buffer layer of 150 nm AlN and 1.5 µm C-doped high-resistance GaN; Ti(15nm)/Al(100nm)/Ni(45nm)/Au(60nm) ohmic contact electrodes for source and drain; Ni(60nm)/Au(100nm) Schottky gate electrode; Ni(100nm)/Au(100nm) field plate electrode on GaN channel layer. Process steps include MOCVD growth, ICP etching alignment marks at 700 nm depth, annealing at 840°C for 30 s, mesa isolation at 150 nm depth, PECVD SiO₂ passivation, metal hot-press bonding, substrate thinning and removal, and field plate electrode deposition.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-HEMT with sandwich structure
Materials described outside the worked examples.
Ti/Au/Sn/Au multi-metal layer (bonded substrate)
Ni/Au lead electrode
epitaxial silicon substrate
Si
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 530–650 V | — |
Voltage | 3–6 V | — |
Voltage | 530–589 V | — |
Voltage | 3–5.8 V | — |
Voltage | 530–670 V | — |
Voltage | 3–5.7 V | — |
Temperature | 830–850 °C | — |
Thickness | 30–50 µm | — |
Duration | 5–10 minutes | — |
Thickness | 100–200 nm | — |
Thickness | 1–2 µm | — |
Thickness | 100–300 nm | — |
Thickness | 20–30 nm | — |
Temperature | 280–300 °C | — |
Duration | 10–20 min | — |
Thickness | 0.5–1 µm | — |
Thickness | 10–20 nm | — |
Thickness | 60–150 nm | — |
Thickness | 30–60 nm | — |
Thickness | 50–100 nm | — |
Thickness | 30–100 nm | — |
Thickness | ≥ 600 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
GAN-BASED FIELD EFFECT TRANSISTOR
LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
GALLIUM NITRIDE WAFER SUBSTRATE FOR SOLID STATE LIGHTING DEVICES AND ASSOCIATED SYSTEMS
GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION
INGAN/GAN MULTIPLE QUANTUM WELL BLUE LIGHT DETECTOR COMBINED WITH EMBEDDED ELECTRODE AND PASSIVATION LAYER STRUCTURE AND PREPARATION METHOD AND APPLICATION THEREOF
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
METHOD OF FORMING VIAS IN A GaN/DIAMOND WAFER
VACANCY-RICH SILICON FOR USE WITH A GALLIUM NITRIDE EPITAXIAL LAYER
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of an epitaxial buffer layer, a GaN channel layer and an AlyGa0.75-yN barrier layer sequentially grown on an epitaxial …
FIG. 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention after a gate electrode, a source electrode …
FIG. 3 is a schematic structural diagram of a wafer substrate etched with epitaxial buffer layer after transfer according to an embodiment of the present …
FIG. 4 is a schematic cross-sectional diagram of a lead electrode and a HEMT device with a sandwich structure prepared after through-hole etching according to …
FIG. 5 is a partial three-dimensional schematic diagram of a HEMT device with a sandwich structure according to an embodiment of the present invention; In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN-HEMT device with a sandwich structure, wherein the GaN-HEMT device com-prises an epitaxial layer and electrodes, wherein the epitaxial layer comprises a GaN channel layer and an AlyGa₁-y barrier layer, and y is 0.2 to 0.3; the GaN channel layer and the AlyGa₁-y barrier layer are arranged from top to bottom; the electrodes comprise a gate electrode, a source electrode, a drain electrode and a field plate electrode, wherein the field plate electrode and the gate electrode are respectively fab-ricated on an upper surface and a lower surface of the epitaxial layer, and the field plate electrode extends to a region beyond the epitaxial layer and is connected with the gate electrode to form the sandwich structure, and the source electrode and the drain electrode are respectively located at two ends of the epitaxial layer, wherein the method comprises following steps: (1) sequentially growing an epitaxial buffer layer, a GaN channel layer and an AlyGa₁-y barrier layer on an epitaxial silicon substrate by using MOCVD to obtain an epitaxial wafer; (2) using photoetching and ICP etching technology to prepare alignment marks required by multilayer pho-toetching steps on a surface of the epitaxial wafer to obtain etched mark points; (3) according to the etched mark points, photoetching HEMT source electrode and drain electrode patterns in corresponding regions on the surface of the epitaxial wafer, depositing Ti/Al/Ni/Au metal electrodes by using a method of electron beam evaporation coating, and then performing rapid high-temperature annealing on the epitaxial wafer to prepare a source electrode and 5 a drain electrode to form an ohmic contact electrode, wherein an annealing temperature is 830 to 850° C. and an annealing time is 30 to 60 s; (4) photoetching the epitaxial wafer with the ohmic contact electrode prepared in the step (3), covering a device region with photoresist, and then performing mesa isolation on the GaN-HEMT device region by using the method of ICP etching; (5) photoetching a gate electrode region of HEMT in corresponding region of the surface of epitaxial wafer after mesa isolation, and depositing a Ni/Au metal electrode by using the method of electron beam evapo-ration coating to prepare a gate electrode, thereby forming a Schottky electrode to obtain a wafer of the gate electrode; (6) by using a method of PECVD, growing one layer of silicon dioxide passivation film layer on the surface of the wafer with the gate electrode prepared, so as to obtain a passivation wafer; (7) bonding the passivation wafer with a bonded silicon substrate together in a metal hot-press bonding mode, wherein specific steps are as follows: depositing a Ni/Au/Sn/Au multi-metal layer on a surface of the passivation wafer where the silicon dioxide passivation film layer is grown, depositing a Ti/Au/Sn/Au multimetal layer on a surface of the bonded silicon substrate, and then adhering the two metal layers together, and putting them into a hot-press bonding machine for hot-press cementing to obtain a bonded wafer; (8) putting the bonded wafer into a mechanical thinning machine, grinding and thinning the epitaxial silicon substrate, controlling a thinning thickness, and leaving the epitaxial silicon substrate with a thickness of 30 to 50 µm, and then soaking the bonded wafer in a nitric acid/hydrofluoric acid/acetic acid mixed acid solution with a volume ratio of 3: 1: 1 to 3: 1: 2 for 5 to 10 minutes to completely remove the epitaxial silicon substrate and expose AIN of the epitaxial buffer layer; etching the exposed AIN of the epitaxial buffer layer to a C-doped high-resistance GaN layer by using ICP to obtain a wafer with the epitaxial buffer layer etched; (9) performing photoetching on the wafer with the epi-taxial buffer layer etched, and exposing an opening etching region in the corresponding regions of the source electrode, the drain electrode and the gate elec-B₂ trode, performing electrode opening etching by using ICP technology, and then depositing a Ni/Au lead electrode by using the method of the electron beam evaporation coating, and depositing the Ni/Au metal layer at a position, opposite to gate electrode, on an upper surface of the epitaxial layer at the same time, so as to prepare a field plate electrode and form an inverted GaN-HEMT device with a sandwich structure.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein the epitaxial buffer layer in the step (1) comprises 100 to 200 nm of AIN and 1 to 2 µm of C-doped high-resistance GaN layer; a thickness of the GaN channel layer is 100 to 300 nm; and a thickness of the AlyGa₁-y barrier layer is 20 to 30 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the etched mark points in the step (2) is greater than 600 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the mesa isolation in the step (4) is 100 to 200 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the silicon dioxide passivation film layer in the step (6) is 1 to 2 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a bonding air pressure in the hot-press bonding machine in the step (7) is 1E-3 to 2E-3 Pa, a bonding temperature is 280 to 300° C., a bonding pressure is 3 to 4 kBar, and a bonding time is 10 to 20 min.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein when etching the epitaxial buffer layer by ICP in the step (8), the C-doped high-resistance GaN layer remained is 0.5 to 1 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein in the Ti/Al/Ni/Au metal electrodes in the step (3), a thickness of the Ti metal layer is 10 to 20 nm, a thickness of the Al metal layer is 60 to 150 nm, a thickness of the Ni metal layer is to 60 nm, and a thickness of the Au metal layer is 50 to 100 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the Ni metal layer of the Ni/Au metal electrode in the step (5) is 30 to 100 nm, and a thickness of the Au metal layer is 50 to 100 nm. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
8 materials5 process steps
A GaN-HEMT device with a sandwich structure is prepared using: a 150 nm GaN channel layer and a 25 nm Al0.25Ga0.75N barrier layer as the epitaxial layer; an epitaxial buffer layer of 150 nm AlN and 1.5 µm C-doped high-resistance GaN; Ti(15nm)/Al(100nm)/Ni(45nm)/Au(60nm) ohmic contact electrodes for source and drain; Ni(60nm)/Au(100nm) Schottky gate electrode; Ni(100nm)/Au(100nm) field plate electrode on GaN channel layer. Process steps include MOCVD growth, ICP etching alignment marks at 700 nm depth, annealing at 840°C for 30 s, mesa isolation at 150 nm depth, PECVD SiO₂ passivation, metal hot-press bonding, substrate thinning and removal, and field plate electrode deposition.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-HEMT with sandwich structure
Materials described outside the worked examples.
Ti/Au/Sn/Au multi-metal layer (bonded substrate)
Ni/Au lead electrode
epitaxial silicon substrate
Si
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 530–650 V | — |
Voltage | 3–6 V | — |
Voltage | 530–589 V | — |
Voltage | 3–5.8 V | — |
Voltage | 530–670 V | — |
Voltage | 3–5.7 V | — |
Temperature | 830–850 °C | — |
Thickness | 30–50 µm | — |
Duration | 5–10 minutes | — |
Thickness | 100–200 nm | — |
Thickness | 1–2 µm | — |
Thickness | 100–300 nm | — |
Thickness | 20–30 nm | — |
Temperature | 280–300 °C | — |
Duration | 10–20 min | — |
Thickness | 0.5–1 µm | — |
Thickness | 10–20 nm | — |
Thickness | 60–150 nm | — |
Thickness | 30–60 nm | — |
Thickness | 50–100 nm | — |
Thickness | 30–100 nm | — |
Thickness | ≥ 600 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
GAN-BASED FIELD EFFECT TRANSISTOR
LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
GALLIUM NITRIDE WAFER SUBSTRATE FOR SOLID STATE LIGHTING DEVICES AND ASSOCIATED SYSTEMS
GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION
INGAN/GAN MULTIPLE QUANTUM WELL BLUE LIGHT DETECTOR COMBINED WITH EMBEDDED ELECTRODE AND PASSIVATION LAYER STRUCTURE AND PREPARATION METHOD AND APPLICATION THEREOF
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
METHOD OF FORMING VIAS IN A GaN/DIAMOND WAFER
VACANCY-RICH SILICON FOR USE WITH A GALLIUM NITRIDE EPITAXIAL LAYER
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of an epitaxial buffer layer, a GaN channel layer and an AlyGa0.75-yN barrier layer sequentially grown on an epitaxial …
FIG. 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention after a gate electrode, a source electrode …
FIG. 3 is a schematic structural diagram of a wafer substrate etched with epitaxial buffer layer after transfer according to an embodiment of the present …
FIG. 4 is a schematic cross-sectional diagram of a lead electrode and a HEMT device with a sandwich structure prepared after through-hole etching according to …
FIG. 5 is a partial three-dimensional schematic diagram of a HEMT device with a sandwich structure according to an embodiment of the present invention; In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN-HEMT device with a sandwich structure, wherein the GaN-HEMT device com-prises an epitaxial layer and electrodes, wherein the epitaxial layer comprises a GaN channel layer and an AlyGa₁-y barrier layer, and y is 0.2 to 0.3; the GaN channel layer and the AlyGa₁-y barrier layer are arranged from top to bottom; the electrodes comprise a gate electrode, a source electrode, a drain electrode and a field plate electrode, wherein the field plate electrode and the gate electrode are respectively fab-ricated on an upper surface and a lower surface of the epitaxial layer, and the field plate electrode extends to a region beyond the epitaxial layer and is connected with the gate electrode to form the sandwich structure, and the source electrode and the drain electrode are respectively located at two ends of the epitaxial layer, wherein the method comprises following steps: (1) sequentially growing an epitaxial buffer layer, a GaN channel layer and an AlyGa₁-y barrier layer on an epitaxial silicon substrate by using MOCVD to obtain an epitaxial wafer; (2) using photoetching and ICP etching technology to prepare alignment marks required by multilayer pho-toetching steps on a surface of the epitaxial wafer to obtain etched mark points; (3) according to the etched mark points, photoetching HEMT source electrode and drain electrode patterns in corresponding regions on the surface of the epitaxial wafer, depositing Ti/Al/Ni/Au metal electrodes by using a method of electron beam evaporation coating, and then performing rapid high-temperature annealing on the epitaxial wafer to prepare a source electrode and 5 a drain electrode to form an ohmic contact electrode, wherein an annealing temperature is 830 to 850° C. and an annealing time is 30 to 60 s; (4) photoetching the epitaxial wafer with the ohmic contact electrode prepared in the step (3), covering a device region with photoresist, and then performing mesa isolation on the GaN-HEMT device region by using the method of ICP etching; (5) photoetching a gate electrode region of HEMT in corresponding region of the surface of epitaxial wafer after mesa isolation, and depositing a Ni/Au metal electrode by using the method of electron beam evapo-ration coating to prepare a gate electrode, thereby forming a Schottky electrode to obtain a wafer of the gate electrode; (6) by using a method of PECVD, growing one layer of silicon dioxide passivation film layer on the surface of the wafer with the gate electrode prepared, so as to obtain a passivation wafer; (7) bonding the passivation wafer with a bonded silicon substrate together in a metal hot-press bonding mode, wherein specific steps are as follows: depositing a Ni/Au/Sn/Au multi-metal layer on a surface of the passivation wafer where the silicon dioxide passivation film layer is grown, depositing a Ti/Au/Sn/Au multimetal layer on a surface of the bonded silicon substrate, and then adhering the two metal layers together, and putting them into a hot-press bonding machine for hot-press cementing to obtain a bonded wafer; (8) putting the bonded wafer into a mechanical thinning machine, grinding and thinning the epitaxial silicon substrate, controlling a thinning thickness, and leaving the epitaxial silicon substrate with a thickness of 30 to 50 µm, and then soaking the bonded wafer in a nitric acid/hydrofluoric acid/acetic acid mixed acid solution with a volume ratio of 3: 1: 1 to 3: 1: 2 for 5 to 10 minutes to completely remove the epitaxial silicon substrate and expose AIN of the epitaxial buffer layer; etching the exposed AIN of the epitaxial buffer layer to a C-doped high-resistance GaN layer by using ICP to obtain a wafer with the epitaxial buffer layer etched; (9) performing photoetching on the wafer with the epi-taxial buffer layer etched, and exposing an opening etching region in the corresponding regions of the source electrode, the drain electrode and the gate elec-B₂ trode, performing electrode opening etching by using ICP technology, and then depositing a Ni/Au lead electrode by using the method of the electron beam evaporation coating, and depositing the Ni/Au metal layer at a position, opposite to gate electrode, on an upper surface of the epitaxial layer at the same time, so as to prepare a field plate electrode and form an inverted GaN-HEMT device with a sandwich structure.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein the epitaxial buffer layer in the step (1) comprises 100 to 200 nm of AIN and 1 to 2 µm of C-doped high-resistance GaN layer; a thickness of the GaN channel layer is 100 to 300 nm; and a thickness of the AlyGa₁-y barrier layer is 20 to 30 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the etched mark points in the step (2) is greater than 600 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the mesa isolation in the step (4) is 100 to 200 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the silicon dioxide passivation film layer in the step (6) is 1 to 2 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a bonding air pressure in the hot-press bonding machine in the step (7) is 1E-3 to 2E-3 Pa, a bonding temperature is 280 to 300° C., a bonding pressure is 3 to 4 kBar, and a bonding time is 10 to 20 min.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein when etching the epitaxial buffer layer by ICP in the step (8), the C-doped high-resistance GaN layer remained is 0.5 to 1 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein in the Ti/Al/Ni/Au metal electrodes in the step (3), a thickness of the Ti metal layer is 10 to 20 nm, a thickness of the Al metal layer is 60 to 150 nm, a thickness of the Ni metal layer is to 60 nm, and a thickness of the Au metal layer is 50 to 100 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the Ni metal layer of the Ni/Au metal electrode in the step (5) is 30 to 100 nm, and a thickness of the Au metal layer is 50 to 100 nm. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
8 materials5 process steps
A GaN-HEMT device with a sandwich structure is prepared using: a 150 nm GaN channel layer and a 25 nm Al0.25Ga0.75N barrier layer as the epitaxial layer; an epitaxial buffer layer of 150 nm AlN and 1.5 µm C-doped high-resistance GaN; Ti(15nm)/Al(100nm)/Ni(45nm)/Au(60nm) ohmic contact electrodes for source and drain; Ni(60nm)/Au(100nm) Schottky gate electrode; Ni(100nm)/Au(100nm) field plate electrode on GaN channel layer. Process steps include MOCVD growth, ICP etching alignment marks at 700 nm depth, annealing at 840°C for 30 s, mesa isolation at 150 nm depth, PECVD SiO₂ passivation, metal hot-press bonding, substrate thinning and removal, and field plate electrode deposition.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-HEMT with sandwich structure
Materials described outside the worked examples.
Ti/Au/Sn/Au multi-metal layer (bonded substrate)
Ni/Au lead electrode
epitaxial silicon substrate
Si
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 530–650 V | — |
Voltage | 3–6 V | — |
Voltage | 530–589 V | — |
Voltage | 3–5.8 V | — |
Voltage | 530–670 V | — |
Voltage | 3–5.7 V | — |
Temperature | 830–850 °C | — |
Thickness | 30–50 µm | — |
Duration | 5–10 minutes | — |
Thickness | 100–200 nm | — |
Thickness | 1–2 µm | — |
Thickness | 100–300 nm | — |
Thickness | 20–30 nm | — |
Temperature | 280–300 °C | — |
Duration | 10–20 min | — |
Thickness | 0.5–1 µm | — |
Thickness | 10–20 nm | — |
Thickness | 60–150 nm | — |
Thickness | 30–60 nm | — |
Thickness | 50–100 nm | — |
Thickness | 30–100 nm | — |
Thickness | ≥ 600 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
GAN-BASED FIELD EFFECT TRANSISTOR
LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
GALLIUM NITRIDE WAFER SUBSTRATE FOR SOLID STATE LIGHTING DEVICES AND ASSOCIATED SYSTEMS
GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION
INGAN/GAN MULTIPLE QUANTUM WELL BLUE LIGHT DETECTOR COMBINED WITH EMBEDDED ELECTRODE AND PASSIVATION LAYER STRUCTURE AND PREPARATION METHOD AND APPLICATION THEREOF
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
METHOD OF FORMING VIAS IN A GaN/DIAMOND WAFER
VACANCY-RICH SILICON FOR USE WITH A GALLIUM NITRIDE EPITAXIAL LAYER
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of an epitaxial buffer layer, a GaN channel layer and an AlyGa0.75-yN barrier layer sequentially grown on an epitaxial …
FIG. 2 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the present invention after a gate electrode, a source electrode …
FIG. 3 is a schematic structural diagram of a wafer substrate etched with epitaxial buffer layer after transfer according to an embodiment of the present …
FIG. 4 is a schematic cross-sectional diagram of a lead electrode and a HEMT device with a sandwich structure prepared after through-hole etching according to …
FIG. 5 is a partial three-dimensional schematic diagram of a HEMT device with a sandwich structure according to an embodiment of the present invention; In the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for preparing a GaN-HEMT device with a sandwich structure, wherein the GaN-HEMT device com-prises an epitaxial layer and electrodes, wherein the epitaxial layer comprises a GaN channel layer and an AlyGa₁-y barrier layer, and y is 0.2 to 0.3; the GaN channel layer and the AlyGa₁-y barrier layer are arranged from top to bottom; the electrodes comprise a gate electrode, a source electrode, a drain electrode and a field plate electrode, wherein the field plate electrode and the gate electrode are respectively fab-ricated on an upper surface and a lower surface of the epitaxial layer, and the field plate electrode extends to a region beyond the epitaxial layer and is connected with the gate electrode to form the sandwich structure, and the source electrode and the drain electrode are respectively located at two ends of the epitaxial layer, wherein the method comprises following steps: (1) sequentially growing an epitaxial buffer layer, a GaN channel layer and an AlyGa₁-y barrier layer on an epitaxial silicon substrate by using MOCVD to obtain an epitaxial wafer; (2) using photoetching and ICP etching technology to prepare alignment marks required by multilayer pho-toetching steps on a surface of the epitaxial wafer to obtain etched mark points; (3) according to the etched mark points, photoetching HEMT source electrode and drain electrode patterns in corresponding regions on the surface of the epitaxial wafer, depositing Ti/Al/Ni/Au metal electrodes by using a method of electron beam evaporation coating, and then performing rapid high-temperature annealing on the epitaxial wafer to prepare a source electrode and 5 a drain electrode to form an ohmic contact electrode, wherein an annealing temperature is 830 to 850° C. and an annealing time is 30 to 60 s; (4) photoetching the epitaxial wafer with the ohmic contact electrode prepared in the step (3), covering a device region with photoresist, and then performing mesa isolation on the GaN-HEMT device region by using the method of ICP etching; (5) photoetching a gate electrode region of HEMT in corresponding region of the surface of epitaxial wafer after mesa isolation, and depositing a Ni/Au metal electrode by using the method of electron beam evapo-ration coating to prepare a gate electrode, thereby forming a Schottky electrode to obtain a wafer of the gate electrode; (6) by using a method of PECVD, growing one layer of silicon dioxide passivation film layer on the surface of the wafer with the gate electrode prepared, so as to obtain a passivation wafer; (7) bonding the passivation wafer with a bonded silicon substrate together in a metal hot-press bonding mode, wherein specific steps are as follows: depositing a Ni/Au/Sn/Au multi-metal layer on a surface of the passivation wafer where the silicon dioxide passivation film layer is grown, depositing a Ti/Au/Sn/Au multimetal layer on a surface of the bonded silicon substrate, and then adhering the two metal layers together, and putting them into a hot-press bonding machine for hot-press cementing to obtain a bonded wafer; (8) putting the bonded wafer into a mechanical thinning machine, grinding and thinning the epitaxial silicon substrate, controlling a thinning thickness, and leaving the epitaxial silicon substrate with a thickness of 30 to 50 µm, and then soaking the bonded wafer in a nitric acid/hydrofluoric acid/acetic acid mixed acid solution with a volume ratio of 3: 1: 1 to 3: 1: 2 for 5 to 10 minutes to completely remove the epitaxial silicon substrate and expose AIN of the epitaxial buffer layer; etching the exposed AIN of the epitaxial buffer layer to a C-doped high-resistance GaN layer by using ICP to obtain a wafer with the epitaxial buffer layer etched; (9) performing photoetching on the wafer with the epi-taxial buffer layer etched, and exposing an opening etching region in the corresponding regions of the source electrode, the drain electrode and the gate elec-B₂ trode, performing electrode opening etching by using ICP technology, and then depositing a Ni/Au lead electrode by using the method of the electron beam evaporation coating, and depositing the Ni/Au metal layer at a position, opposite to gate electrode, on an upper surface of the epitaxial layer at the same time, so as to prepare a field plate electrode and form an inverted GaN-HEMT device with a sandwich structure.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein the epitaxial buffer layer in the step (1) comprises 100 to 200 nm of AIN and 1 to 2 µm of C-doped high-resistance GaN layer; a thickness of the GaN channel layer is 100 to 300 nm; and a thickness of the AlyGa₁-y barrier layer is 20 to 30 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the etched mark points in the step (2) is greater than 600 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein an etching depth of the mesa isolation in the step (4) is 100 to 200 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the silicon dioxide passivation film layer in the step (6) is 1 to 2 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a bonding air pressure in the hot-press bonding machine in the step (7) is 1E-3 to 2E-3 Pa, a bonding temperature is 280 to 300° C., a bonding pressure is 3 to 4 kBar, and a bonding time is 10 to 20 min.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein when etching the epitaxial buffer layer by ICP in the step (8), the C-doped high-resistance GaN layer remained is 0.5 to 1 µm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein in the Ti/Al/Ni/Au metal electrodes in the step (3), a thickness of the Ti metal layer is 10 to 20 nm, a thickness of the Al metal layer is 60 to 150 nm, a thickness of the Ni metal layer is to 60 nm, and a thickness of the Au metal layer is 50 to 100 nm.
The method for preparing the GaN-HEMT device with the sandwich structure according to claim 1, wherein a thickness of the Ni metal layer of the Ni/Au metal electrode in the step (5) is 30 to 100 nm, and a thickness of the Au metal layer is 50 to 100 nm. ∗ ∗ ∗ ∗ ∗
Embodiments described in the patent, grouped by the materials and process steps they use.
8 materials5 process steps
A GaN-HEMT device with a sandwich structure is prepared using: a 150 nm GaN channel layer and a 25 nm Al0.25Ga0.75N barrier layer as the epitaxial layer; an epitaxial buffer layer of 150 nm AlN and 1.5 µm C-doped high-resistance GaN; Ti(15nm)/Al(100nm)/Ni(45nm)/Au(60nm) ohmic contact electrodes for source and drain; Ni(60nm)/Au(100nm) Schottky gate electrode; Ni(100nm)/Au(100nm) field plate electrode on GaN channel layer. Process steps include MOCVD growth, ICP etching alignment marks at 700 nm depth, annealing at 840°C for 30 s, mesa isolation at 150 nm depth, PECVD SiO₂ passivation, metal hot-press bonding, substrate thinning and removal, and field plate electrode deposition.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-HEMT with sandwich structure
Materials described outside the worked examples.
Ti/Au/Sn/Au multi-metal layer (bonded substrate)
Ni/Au lead electrode
epitaxial silicon substrate
Si
Al0.25Ga0.75N barrier layer
Al0.25Ga0.75N
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 530–650 V | — |
Voltage | 3–6 V | — |
Voltage | 530–589 V | — |
Voltage | 3–5.8 V | — |
Voltage | 530–670 V | — |
Voltage | 3–5.7 V | — |
Temperature | 830–850 °C | — |
Thickness | 30–50 µm | — |
Duration | 5–10 minutes | — |
Thickness | 100–200 nm | — |
Thickness | 1–2 µm | — |
Thickness | 100–300 nm | — |
Thickness | 20–30 nm | — |
Temperature | 280–300 °C | — |
Duration | 10–20 min | — |
Thickness | 0.5–1 µm | — |
Thickness | 10–20 nm | — |
Thickness | 60–150 nm | — |
Thickness | 30–60 nm | — |
Thickness | 50–100 nm | — |
Thickness | 30–100 nm | — |
Thickness | ≥ 600 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 4
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
GAN-BASED FIELD EFFECT TRANSISTOR
LOW GATE-LEAKAGE STRUCTURE AND METHOD FOR GALLIUM NITRIDE ENHANCEMENT MODE TRANSISTOR
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
GALLIUM NITRIDE WAFER SUBSTRATE FOR SOLID STATE LIGHTING DEVICES AND ASSOCIATED SYSTEMS
GaN HEMT DEVICE STRUCTURE AND METHOD OF FABRICATION
INGAN/GAN MULTIPLE QUANTUM WELL BLUE LIGHT DETECTOR COMBINED WITH EMBEDDED ELECTRODE AND PASSIVATION LAYER STRUCTURE AND PREPARATION METHOD AND APPLICATION THEREOF
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
METHOD OF FORMING VIAS IN A GaN/DIAMOND WAFER
VACANCY-RICH SILICON FOR USE WITH A GALLIUM NITRIDE EPITAXIAL LAYER
