Patent
US 9,048,173DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
Can Bayram
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,048,173Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating a (100) silicon substrate that can be employed in one embodiment of the …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the silicon substrate of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 after forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each patterned …
FIG. 6 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 11 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 12 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 13 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 14 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 18 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 19 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 20 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 21 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 22 is a pictorial representation (through a cross sectional view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for selectively forming a dual phase gallium nitride material on a silicon substrate, said method comprising: forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate; patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate; forming a contiguous A l N buffer layer on exposed surfaces of each of said patterned dielectric material st-ruetur e structures and on exposed surfaces of the silicon substrate; and forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each of said patterned dielectric material strucufe structures, wherein said dual phase gallium nitride material comprises a wurtzite phase and a cubic phase, wherein the cubic phase defines at least a portion of an uppermost surface of the gallium nitride material. 2 I:\IBM\ 1 05\29444\AMEN D \29444.am l.doc
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from 200 nm to 500 nm.
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from greater than 500 nm and up to 5000 nm.
The method of Claim 1, further comprising heating the etched silicon substrate including said plurality of patterned dielectric material structures in an atmosphere of hydrogen and prealuminizing the exposed surfaces of the silicon substrate.
The method of Claim 1, wherein said forming the contiguous A l N buffer layer comprises introducing an organoaluminum precursor and a nitride precursor and depositing said precursors at a temperature of 600 ± °C or greater.
The method of Claim 1, wherein said forming said dual phase gallium nitride material comprises metalorganic chemical vapor deposition (MOC V D), and said MOCVD is performed at a temperature from 850 ± °C or greater.
The method of Claim 1, wherein said cubic phase of said dual phase gallium nitride material has a shape of an inverted triangular and wherein a base of said inverted 3 I:\IBM\10 5\29444\AMEND\29444. aml.doc triangular constitutes the entirety of the uppermost surface of the dual phase gallium nitride material.
The method of Claim 1, further comprising forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising: forming another dielectric material on exposed surfaces of the contiguous A l N buffer layer, exposed surfaces of the dual phase gallium nitride material and exposed surfaces of the (100) silicon substrate; planarizing the another dielectric material to provide a planar structure in which uppermost surfaces of the dual gallium nitride material, remaining A l N buffer layer, remaining portion of the another dielectric material and the patterned dielectric structures are coplanar with each other; and forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising forming a photonic device via placing contacts on an exposed bottommost surface of the (100) silicon substrate.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising: 4 I:\I BM\ 1 05\29444\AMEND\29444.am l.doc -removing a horizontal portion of said contiguous A I N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmete structures is exposed; removing each of said patterned dielectric material stiuetua e structures to expose a portion of the uppermost surface of the (100) silicon substrate; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Cu rr ently Amended) The method of Claim 1, further comprising: removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmeture structures is exposed; removing each of said patterned dielectric material stmetare structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate, wherein a gap is present between the semiconductor material and the exposed portion of the sidewall surface of said dual phase gallium nitride material; and 5 I:\IBM\105\29444\ AME ND\29444.am l.do c forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric simcue structures is exposed; removing each of said patterned dielectric material s t1etu e structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; forming a dielectric spacer on each exposed sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material. 14.-28.
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Layer stacks claimed or described, ordered top of device to substrate.
dual phase GaN on (100) Si structure
Materials described outside the worked examples.
dual phase gallium nitride
GaN
AlN buffer layer
AlN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50000–20000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,048,173Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating a (100) silicon substrate that can be employed in one embodiment of the …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the silicon substrate of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 after forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each patterned …
FIG. 6 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 11 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 12 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 13 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 14 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 18 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 19 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 20 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 21 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 22 is a pictorial representation (through a cross sectional view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for selectively forming a dual phase gallium nitride material on a silicon substrate, said method comprising: forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate; patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate; forming a contiguous A l N buffer layer on exposed surfaces of each of said patterned dielectric material st-ruetur e structures and on exposed surfaces of the silicon substrate; and forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each of said patterned dielectric material strucufe structures, wherein said dual phase gallium nitride material comprises a wurtzite phase and a cubic phase, wherein the cubic phase defines at least a portion of an uppermost surface of the gallium nitride material. 2 I:\IBM\ 1 05\29444\AMEN D \29444.am l.doc
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from 200 nm to 500 nm.
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from greater than 500 nm and up to 5000 nm.
The method of Claim 1, further comprising heating the etched silicon substrate including said plurality of patterned dielectric material structures in an atmosphere of hydrogen and prealuminizing the exposed surfaces of the silicon substrate.
The method of Claim 1, wherein said forming the contiguous A l N buffer layer comprises introducing an organoaluminum precursor and a nitride precursor and depositing said precursors at a temperature of 600 ± °C or greater.
The method of Claim 1, wherein said forming said dual phase gallium nitride material comprises metalorganic chemical vapor deposition (MOC V D), and said MOCVD is performed at a temperature from 850 ± °C or greater.
The method of Claim 1, wherein said cubic phase of said dual phase gallium nitride material has a shape of an inverted triangular and wherein a base of said inverted 3 I:\IBM\10 5\29444\AMEND\29444. aml.doc triangular constitutes the entirety of the uppermost surface of the dual phase gallium nitride material.
The method of Claim 1, further comprising forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising: forming another dielectric material on exposed surfaces of the contiguous A l N buffer layer, exposed surfaces of the dual phase gallium nitride material and exposed surfaces of the (100) silicon substrate; planarizing the another dielectric material to provide a planar structure in which uppermost surfaces of the dual gallium nitride material, remaining A l N buffer layer, remaining portion of the another dielectric material and the patterned dielectric structures are coplanar with each other; and forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising forming a photonic device via placing contacts on an exposed bottommost surface of the (100) silicon substrate.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising: 4 I:\I BM\ 1 05\29444\AMEND\29444.am l.doc -removing a horizontal portion of said contiguous A I N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmete structures is exposed; removing each of said patterned dielectric material stiuetua e structures to expose a portion of the uppermost surface of the (100) silicon substrate; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Cu rr ently Amended) The method of Claim 1, further comprising: removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmeture structures is exposed; removing each of said patterned dielectric material stmetare structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate, wherein a gap is present between the semiconductor material and the exposed portion of the sidewall surface of said dual phase gallium nitride material; and 5 I:\IBM\105\29444\ AME ND\29444.am l.do c forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric simcue structures is exposed; removing each of said patterned dielectric material s t1etu e structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; forming a dielectric spacer on each exposed sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material. 14.-28.
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Layer stacks claimed or described, ordered top of device to substrate.
dual phase GaN on (100) Si structure
Materials described outside the worked examples.
dual phase gallium nitride
GaN
AlN buffer layer
AlN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50000–20000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,048,173Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating a (100) silicon substrate that can be employed in one embodiment of the …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the silicon substrate of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 after forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each patterned …
FIG. 6 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 11 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 12 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 13 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 14 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 18 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 19 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 20 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 21 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 22 is a pictorial representation (through a cross sectional view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for selectively forming a dual phase gallium nitride material on a silicon substrate, said method comprising: forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate; patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate; forming a contiguous A l N buffer layer on exposed surfaces of each of said patterned dielectric material st-ruetur e structures and on exposed surfaces of the silicon substrate; and forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each of said patterned dielectric material strucufe structures, wherein said dual phase gallium nitride material comprises a wurtzite phase and a cubic phase, wherein the cubic phase defines at least a portion of an uppermost surface of the gallium nitride material. 2 I:\IBM\ 1 05\29444\AMEN D \29444.am l.doc
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from 200 nm to 500 nm.
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from greater than 500 nm and up to 5000 nm.
The method of Claim 1, further comprising heating the etched silicon substrate including said plurality of patterned dielectric material structures in an atmosphere of hydrogen and prealuminizing the exposed surfaces of the silicon substrate.
The method of Claim 1, wherein said forming the contiguous A l N buffer layer comprises introducing an organoaluminum precursor and a nitride precursor and depositing said precursors at a temperature of 600 ± °C or greater.
The method of Claim 1, wherein said forming said dual phase gallium nitride material comprises metalorganic chemical vapor deposition (MOC V D), and said MOCVD is performed at a temperature from 850 ± °C or greater.
The method of Claim 1, wherein said cubic phase of said dual phase gallium nitride material has a shape of an inverted triangular and wherein a base of said inverted 3 I:\IBM\10 5\29444\AMEND\29444. aml.doc triangular constitutes the entirety of the uppermost surface of the dual phase gallium nitride material.
The method of Claim 1, further comprising forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising: forming another dielectric material on exposed surfaces of the contiguous A l N buffer layer, exposed surfaces of the dual phase gallium nitride material and exposed surfaces of the (100) silicon substrate; planarizing the another dielectric material to provide a planar structure in which uppermost surfaces of the dual gallium nitride material, remaining A l N buffer layer, remaining portion of the another dielectric material and the patterned dielectric structures are coplanar with each other; and forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising forming a photonic device via placing contacts on an exposed bottommost surface of the (100) silicon substrate.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising: 4 I:\I BM\ 1 05\29444\AMEND\29444.am l.doc -removing a horizontal portion of said contiguous A I N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmete structures is exposed; removing each of said patterned dielectric material stiuetua e structures to expose a portion of the uppermost surface of the (100) silicon substrate; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Cu rr ently Amended) The method of Claim 1, further comprising: removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmeture structures is exposed; removing each of said patterned dielectric material stmetare structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate, wherein a gap is present between the semiconductor material and the exposed portion of the sidewall surface of said dual phase gallium nitride material; and 5 I:\IBM\105\29444\ AME ND\29444.am l.do c forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric simcue structures is exposed; removing each of said patterned dielectric material s t1etu e structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; forming a dielectric spacer on each exposed sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material. 14.-28.
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Layer stacks claimed or described, ordered top of device to substrate.
dual phase GaN on (100) Si structure
Materials described outside the worked examples.
dual phase gallium nitride
GaN
AlN buffer layer
AlN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50000–20000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,048,173Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating a (100) silicon substrate that can be employed in one embodiment of the …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the silicon substrate of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 after forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each patterned …
FIG. 6 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
FIG. 8 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 9 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 11 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 12 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 13 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 14 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 15 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 16 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 17 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 18 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 19 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 20 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 21 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 22 is a pictorial representation (through a cross sectional view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for selectively forming a dual phase gallium nitride material on a silicon substrate, said method comprising: forming a blanket layer of dielectric material on an uppermost surface of a (100) silicon substrate; patterning said blanket layer of dielectric material forming a plurality of patterned dielectric material structures on portions of the uppermost surface of the (100) silicon substrate and exposing other portions of the uppermost surface of the (100) silicon substrate; etching said exposed other portions of the uppermost surface of the (100) silicon substrate to expose a surface having a (111) crystal plane within the (100) silicon substrate; forming a contiguous A l N buffer layer on exposed surfaces of each of said patterned dielectric material st-ruetur e structures and on exposed surfaces of the silicon substrate; and forming a dual phase gallium nitride material on a portion of the contiguous A l N buffer layer and surrounding each sidewall of each of said patterned dielectric material strucufe structures, wherein said dual phase gallium nitride material comprises a wurtzite phase and a cubic phase, wherein the cubic phase defines at least a portion of an uppermost surface of the gallium nitride material. 2 I:\IBM\ 1 05\29444\AMEN D \29444.am l.doc
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from 200 nm to 500 nm.
The method of Claim 1, wherein a distance from a sidewall surface of one patterned dielectric material structure to a sidewall surface of a neighboring patterned dielectric material structure is from greater than 500 nm and up to 5000 nm.
The method of Claim 1, further comprising heating the etched silicon substrate including said plurality of patterned dielectric material structures in an atmosphere of hydrogen and prealuminizing the exposed surfaces of the silicon substrate.
The method of Claim 1, wherein said forming the contiguous A l N buffer layer comprises introducing an organoaluminum precursor and a nitride precursor and depositing said precursors at a temperature of 600 ± °C or greater.
The method of Claim 1, wherein said forming said dual phase gallium nitride material comprises metalorganic chemical vapor deposition (MOC V D), and said MOCVD is performed at a temperature from 850 ± °C or greater.
The method of Claim 1, wherein said cubic phase of said dual phase gallium nitride material has a shape of an inverted triangular and wherein a base of said inverted 3 I:\IBM\10 5\29444\AMEND\29444. aml.doc triangular constitutes the entirety of the uppermost surface of the dual phase gallium nitride material.
The method of Claim 1, further comprising forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising: forming another dielectric material on exposed surfaces of the contiguous A l N buffer layer, exposed surfaces of the dual phase gallium nitride material and exposed surfaces of the (100) silicon substrate; planarizing the another dielectric material to provide a planar structure in which uppermost surfaces of the dual gallium nitride material, remaining A l N buffer layer, remaining portion of the another dielectric material and the patterned dielectric structures are coplanar with each other; and forming at least one semiconductor device upon and within said dual phase gallium nitride material.
The method of Claim 1, further comprising forming a photonic device via placing contacts on an exposed bottommost surface of the (100) silicon substrate.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising: 4 I:\I BM\ 1 05\29444\AMEND\29444.am l.doc -removing a horizontal portion of said contiguous A I N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmete structures is exposed; removing each of said patterned dielectric material stiuetua e structures to expose a portion of the uppermost surface of the (100) silicon substrate; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Cu rr ently Amended) The method of Claim 1, further comprising: removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric stmeture structures is exposed; removing each of said patterned dielectric material stmetare structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate, wherein a gap is present between the semiconductor material and the exposed portion of the sidewall surface of said dual phase gallium nitride material; and 5 I:\IBM\105\29444\ AME ND\29444.am l.do c forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material.
(Withdrawn and Currently Amended) The method of Claim 1, further comprising removing a horizontal portion of said contiguous A l N buffer layer from atop each of [[the]] said patterned dielectric material structures, wherein an uppermost surface of each of said patterned dielectric simcue structures is exposed; removing each of said patterned dielectric material s t1etu e structures to expose a portion of the uppermost surface of the (100) silicon substrate; removing exposed portions of a remaining portion of the contiguous A l N buffer layer exposing a portion of a sidewall surface of said dual phase gallium nitride material; forming a dielectric spacer on each exposed sidewall surface of said dual phase gallium nitride material; epitaxially growing a semiconductor material on said exposed portion of the uppermost surface of the (100) silicon substrate; and forming semiconductor devices upon and within the dual phase gallium nitride material and upon within said semiconductor material. 14.-28.
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Layer stacks claimed or described, ordered top of device to substrate.
dual phase GaN on (100) Si structure
Materials described outside the worked examples.
dual phase gallium nitride
GaN
AlN buffer layer
AlN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7 is a scanning electron micrograph (SEM) of a structure including a dual phase gallium nitride material integrated on a (100) silicon substrate that is …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50000–20000000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
silicon substrate (100)
Si
epitaxial semiconductor material
| — |
Temperature | 500–600 °C | — |
Temperature | 600–900 °C | — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 100–10000 nm | — |
Thickness | 2000–4000 nm | — |
Thickness | 2–5 nm | — |
Pressure | ≤ 10 bar | — |
Pressure | ≤ 1 bar | — |
Thickness | ≥ 500 nm | — |
silicon substrate (100)
Si
epitaxial semiconductor material
| — |
Temperature | 500–600 °C | — |
Temperature | 600–900 °C | — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 100–10000 nm | — |
Thickness | 2000–4000 nm | — |
Thickness | 2–5 nm | — |
Pressure | ≤ 10 bar | — |
Pressure | ≤ 1 bar | — |
Thickness | ≥ 500 nm | — |
silicon substrate (100)
Si
epitaxial semiconductor material
| — |
Temperature | 500–600 °C | — |
Temperature | 600–900 °C | — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 100–10000 nm | — |
Thickness | 2000–4000 nm | — |
Thickness | 2–5 nm | — |
Pressure | ≤ 10 bar | — |
Pressure | ≤ 1 bar | — |
Thickness | ≥ 500 nm | — |
silicon substrate (100)
Si
epitaxial semiconductor material
| — |
Temperature | 500–600 °C | — |
Temperature | 600–900 °C | — |
Duration | 5–20 minutes | — |
Duration | 5–120 seconds | — |
Duration | 1–20 minutes | — |
Thickness | 10–250 nm | — |
Thickness | 60–80 nm | — |
Duration | 60–7200 s | — |
Thickness | 100–5000 nm | — |
Thickness | 500–1000 nm | — |
Thickness | 100–10000 nm | — |
Thickness | 2000–4000 nm | — |
Thickness | 2–5 nm | — |
Pressure | ≤ 10 bar | — |
Pressure | ≤ 1 bar | — |
Thickness | ≥ 500 nm | — |