Patent
US 8,361,816OF THE INVENTION
Jae Hoon Lee
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,361,816Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a vertical GaN-based LED comprising: forming a nitride-based buffer layer on a silicon substrate; forming a p type GaN layer on the nitride-based buffer layer by -silieen-atems ac;eptor, w i th o ut do p i ng; sequentially forming an active layer, and an n-type GaN layer on the p-type GaN layer; forming an n-electrode on the n-type GaN layer; forrning a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed, wherein the removing the silicon substrate and the forming roughness on the surface of the p-type GaN layer are performed in a single etching process of wet-etching, and wherein the p-type GaN layer has a thickness of more than 500nm, and wherein the n-electrode is formed of Ta, Ti, Al, Ni and Au.
The method according to claim 1, wherein the nitride-based buffer layer is formed of AIN.
The method according to claim 1, wherein the p-type GaN layer is formed to have a thickness of 1/4 of wavelength of light emitted in the 2 DM US 30632846-1. 069576.0655 Application No.: 11/634,106 active layer.
The method according to claim 1, wherein the wet-etching for removing the silicon substrate is performed by using a KOH solution as etching liquid.
The method according to claim 1 further including forming a transparent conductive layer on the p-type GaN layer having the roughness formed, prior to the forming of the p-electrode.
The method according to claim 1, wherein the n-electrode is formed of Ta/Ti/Al/Ni/Au or A l/Ti.
The method according to claim 1, wherein the
The method according to claim 1, wherein the
The method according to claim 1, wherein the electroplating or non-electroplating using any one and Cu.
The method according to claim 1, wherein the 100 0C
The method according to claim 1, wherein the and Au in that order. p-electrode is formed of Ni/Au. plating seed layer is formed of Cr/Au. structure supporting layer is formed by selected from a group consisting of Ni, A u, roughness is formed at temperature of 75 ° C to n-electrode is formed by stacking Ta, Ti, Al, Ni
5.
13.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based LED
Materials described outside the worked examples.
silicon substrate
Si
AlN buffer layer
AlN
p-type GaN layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,361,816Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a vertical GaN-based LED comprising: forming a nitride-based buffer layer on a silicon substrate; forming a p type GaN layer on the nitride-based buffer layer by -silieen-atems ac;eptor, w i th o ut do p i ng; sequentially forming an active layer, and an n-type GaN layer on the p-type GaN layer; forming an n-electrode on the n-type GaN layer; forrning a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed, wherein the removing the silicon substrate and the forming roughness on the surface of the p-type GaN layer are performed in a single etching process of wet-etching, and wherein the p-type GaN layer has a thickness of more than 500nm, and wherein the n-electrode is formed of Ta, Ti, Al, Ni and Au.
The method according to claim 1, wherein the nitride-based buffer layer is formed of AIN.
The method according to claim 1, wherein the p-type GaN layer is formed to have a thickness of 1/4 of wavelength of light emitted in the 2 DM US 30632846-1. 069576.0655 Application No.: 11/634,106 active layer.
The method according to claim 1, wherein the wet-etching for removing the silicon substrate is performed by using a KOH solution as etching liquid.
The method according to claim 1 further including forming a transparent conductive layer on the p-type GaN layer having the roughness formed, prior to the forming of the p-electrode.
The method according to claim 1, wherein the n-electrode is formed of Ta/Ti/Al/Ni/Au or A l/Ti.
The method according to claim 1, wherein the
The method according to claim 1, wherein the
The method according to claim 1, wherein the electroplating or non-electroplating using any one and Cu.
The method according to claim 1, wherein the 100 0C
The method according to claim 1, wherein the and Au in that order. p-electrode is formed of Ni/Au. plating seed layer is formed of Cr/Au. structure supporting layer is formed by selected from a group consisting of Ni, A u, roughness is formed at temperature of 75 ° C to n-electrode is formed by stacking Ta, Ti, Al, Ni
5.
13.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based LED
Materials described outside the worked examples.
silicon substrate
Si
AlN buffer layer
AlN
p-type GaN layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,361,816Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a vertical GaN-based LED comprising: forming a nitride-based buffer layer on a silicon substrate; forming a p type GaN layer on the nitride-based buffer layer by -silieen-atems ac;eptor, w i th o ut do p i ng; sequentially forming an active layer, and an n-type GaN layer on the p-type GaN layer; forming an n-electrode on the n-type GaN layer; forrning a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed, wherein the removing the silicon substrate and the forming roughness on the surface of the p-type GaN layer are performed in a single etching process of wet-etching, and wherein the p-type GaN layer has a thickness of more than 500nm, and wherein the n-electrode is formed of Ta, Ti, Al, Ni and Au.
The method according to claim 1, wherein the nitride-based buffer layer is formed of AIN.
The method according to claim 1, wherein the p-type GaN layer is formed to have a thickness of 1/4 of wavelength of light emitted in the 2 DM US 30632846-1. 069576.0655 Application No.: 11/634,106 active layer.
The method according to claim 1, wherein the wet-etching for removing the silicon substrate is performed by using a KOH solution as etching liquid.
The method according to claim 1 further including forming a transparent conductive layer on the p-type GaN layer having the roughness formed, prior to the forming of the p-electrode.
The method according to claim 1, wherein the n-electrode is formed of Ta/Ti/Al/Ni/Au or A l/Ti.
The method according to claim 1, wherein the
The method according to claim 1, wherein the
The method according to claim 1, wherein the electroplating or non-electroplating using any one and Cu.
The method according to claim 1, wherein the 100 0C
The method according to claim 1, wherein the and Au in that order. p-electrode is formed of Ni/Au. plating seed layer is formed of Cr/Au. structure supporting layer is formed by selected from a group consisting of Ni, A u, roughness is formed at temperature of 75 ° C to n-electrode is formed by stacking Ta, Ti, Al, Ni
5.
13.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based LED
Materials described outside the worked examples.
silicon substrate
Si
AlN buffer layer
AlN
p-type GaN layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,361,816Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of manufacturing a vertical GaN-based LED comprising: forming a nitride-based buffer layer on a silicon substrate; forming a p type GaN layer on the nitride-based buffer layer by -silieen-atems ac;eptor, w i th o ut do p i ng; sequentially forming an active layer, and an n-type GaN layer on the p-type GaN layer; forming an n-electrode on the n-type GaN layer; forrning a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed, wherein the removing the silicon substrate and the forming roughness on the surface of the p-type GaN layer are performed in a single etching process of wet-etching, and wherein the p-type GaN layer has a thickness of more than 500nm, and wherein the n-electrode is formed of Ta, Ti, Al, Ni and Au.
The method according to claim 1, wherein the nitride-based buffer layer is formed of AIN.
The method according to claim 1, wherein the p-type GaN layer is formed to have a thickness of 1/4 of wavelength of light emitted in the 2 DM US 30632846-1. 069576.0655 Application No.: 11/634,106 active layer.
The method according to claim 1, wherein the wet-etching for removing the silicon substrate is performed by using a KOH solution as etching liquid.
The method according to claim 1 further including forming a transparent conductive layer on the p-type GaN layer having the roughness formed, prior to the forming of the p-electrode.
The method according to claim 1, wherein the n-electrode is formed of Ta/Ti/Al/Ni/Au or A l/Ti.
The method according to claim 1, wherein the
The method according to claim 1, wherein the
The method according to claim 1, wherein the electroplating or non-electroplating using any one and Cu.
The method according to claim 1, wherein the 100 0C
The method according to claim 1, wherein the and Au in that order. p-electrode is formed of Ni/Au. plating seed layer is formed of Cr/Au. structure supporting layer is formed by selected from a group consisting of Ni, A u, roughness is formed at temperature of 75 ° C to n-electrode is formed by stacking Ta, Ti, Al, Ni
5.
13.
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN-based LED
Materials described outside the worked examples.
silicon substrate
Si
AlN buffer layer
AlN
p-type GaN layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≥ 500 nm | — |
Related documents with shared materials, methods, properties, or citations.
GaN
n-electrode (Ta/Ti/Al/Ni/Au)
p-electrode (Ni/Au)
plating seed layer (Cr/Au)
structure supporting layer
KOH solution
KOH
transparent conductive layer (CIO/ITO)
active layer
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
GaN
n-electrode (Ta/Ti/Al/Ni/Au)
p-electrode (Ni/Au)
plating seed layer (Cr/Au)
structure supporting layer
KOH solution
KOH
transparent conductive layer (CIO/ITO)
active layer
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
GaN
n-electrode (Ta/Ti/Al/Ni/Au)
p-electrode (Ni/Au)
plating seed layer (Cr/Au)
structure supporting layer
KOH solution
KOH
transparent conductive layer (CIO/ITO)
active layer
LASER ANNEALING OF GAN LEDS WITH REDUCED PATTERN EFFECTS
GaN
n-electrode (Ta/Ti/Al/Ni/Au)
p-electrode (Ni/Au)
plating seed layer (Cr/Au)
structure supporting layer
KOH solution
KOH
transparent conductive layer (CIO/ITO)
active layer