Patent
US 9,653,588GaN Substrate, Semiconductor Device and Method for Fabricating GaN Substrate and Semiconductor Device
Zhenghai Zhang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,653,588Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for fabricating a GaN substrate according to an embodiment of the present invention; [0015]
FIG. 2 is a schematic flowchart of a method for fabricating a GaN substrate according to another embodiment of the present invention; [0016]
FIG. 3 is a schematic structural diagram of a GaN substrate according to still another embodiment of the present invention; [0017]
FIG. 4 is a schematic structural diagram of a GaN substrate according to yet another embodiment of the present invention; and 291980-v 1/4202-62400 3 Atty. …
FIG. 5E are schematic structural diagrams of a semiconductor device according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) substrate, comprising: a GaN base; an aluminum gallium nitride (AlGaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A l GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the AlGaN layer.
The GaN substrate according to claim 1, wherein the GaN base comprises: a base layer made of silicon carbide (SiC), sapphire, or silicon (Si); and a GaN layer disposed on the base layer.
A semiconductor device, comprising: a gallium nitride (GaN) substrate; and a semiconductor structure formed on the GaN substrate, wherein the GaN substrate comprises: a GaN base; an aluminum gallium nitride (A I GaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A I GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between a gate electrode and at least one of a source and a drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the A I GaN layer.
The semiconductor device of claim 5, wherein in a range of 10 7 ' to 10 8 cm3. 398179-v1/4202-62400 of 10 17 to 10 18 cm3. the p-type conducting layer has a hole density
A method for fabricating a gallium nitride (GaN) substrate, comprising: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a. gate electrode, a source, and a drain on an active area of the A l GaN layer; and forming a p-type conducting layer on the active area of the A 1 GaN layer, wherein the p- type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A I GaN layer and neutralize a dangling bond on the A I GaN layer. 398179-vI/4202-62400 3 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the GaN substrate according to claim 6, wherein before forming the A l GaN layer on the GaN base, the method further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the GaN substrate according to claim 6, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
1 1. A method for fabricating a semiconductor device, comprising: forming a gallium nitride (GaN) substrate by using a method for fabricating a GaN substrate; and forming a semiconductor structure on the GaN substrate, wherein the method for fabricating the GaN substrate comprises: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a gate electrode, a source, and a drain on an active area of the A I GaN layer; and forming a p-type conducting layer on the active area of the A l GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A L GaN layer and neutralize a dangling bond on the A l GaN layer. 398179-v 1/4202-62400 5 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the semiconductor device according to claim 11, wherein before forming the A I GaN layer on the GaN base, the method for fabricating the GaN substrate further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the semiconductor device according to claim 11, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Method for fabricating a GaN substrate by forming an AlGaN layer on a GaN base and then forming a p-type conducting layer on the active area of the AlGaN layer to exhaust surface state negative electrons and neutralize dangling bonds.
8 materials5 process steps
Detailed method for forming a GaN substrate on a SiC base layer with an AlN buffer layer, a GaN layer, an AlGaN layer, and a p-type GaN layer (doped with Be, Zn, or Mg) on the active area. Three methods for forming the p-type GaN layer are described: MBE with Be ion implantation, MOCVD growth of Zn-doped GaN, and MOCVD growth of Mg-doped GaN followed by N₂ annealing.
Layer stacks claimed or described, ordered top of device to substrate.
GaN substrate with p-type conducting layer
semiconductor device on GaN substrate
Materials described outside the worked examples.
sapphire
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ | GaN:Mg |
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,653,588Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for fabricating a GaN substrate according to an embodiment of the present invention; [0015]
FIG. 2 is a schematic flowchart of a method for fabricating a GaN substrate according to another embodiment of the present invention; [0016]
FIG. 3 is a schematic structural diagram of a GaN substrate according to still another embodiment of the present invention; [0017]
FIG. 4 is a schematic structural diagram of a GaN substrate according to yet another embodiment of the present invention; and 291980-v 1/4202-62400 3 Atty. …
FIG. 5E are schematic structural diagrams of a semiconductor device according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) substrate, comprising: a GaN base; an aluminum gallium nitride (AlGaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A l GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the AlGaN layer.
The GaN substrate according to claim 1, wherein the GaN base comprises: a base layer made of silicon carbide (SiC), sapphire, or silicon (Si); and a GaN layer disposed on the base layer.
A semiconductor device, comprising: a gallium nitride (GaN) substrate; and a semiconductor structure formed on the GaN substrate, wherein the GaN substrate comprises: a GaN base; an aluminum gallium nitride (A I GaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A I GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between a gate electrode and at least one of a source and a drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the A I GaN layer.
The semiconductor device of claim 5, wherein in a range of 10 7 ' to 10 8 cm3. 398179-v1/4202-62400 of 10 17 to 10 18 cm3. the p-type conducting layer has a hole density
A method for fabricating a gallium nitride (GaN) substrate, comprising: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a. gate electrode, a source, and a drain on an active area of the A l GaN layer; and forming a p-type conducting layer on the active area of the A 1 GaN layer, wherein the p- type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A I GaN layer and neutralize a dangling bond on the A I GaN layer. 398179-vI/4202-62400 3 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the GaN substrate according to claim 6, wherein before forming the A l GaN layer on the GaN base, the method further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the GaN substrate according to claim 6, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
1 1. A method for fabricating a semiconductor device, comprising: forming a gallium nitride (GaN) substrate by using a method for fabricating a GaN substrate; and forming a semiconductor structure on the GaN substrate, wherein the method for fabricating the GaN substrate comprises: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a gate electrode, a source, and a drain on an active area of the A I GaN layer; and forming a p-type conducting layer on the active area of the A l GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A L GaN layer and neutralize a dangling bond on the A l GaN layer. 398179-v 1/4202-62400 5 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the semiconductor device according to claim 11, wherein before forming the A I GaN layer on the GaN base, the method for fabricating the GaN substrate further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the semiconductor device according to claim 11, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Method for fabricating a GaN substrate by forming an AlGaN layer on a GaN base and then forming a p-type conducting layer on the active area of the AlGaN layer to exhaust surface state negative electrons and neutralize dangling bonds.
8 materials5 process steps
Detailed method for forming a GaN substrate on a SiC base layer with an AlN buffer layer, a GaN layer, an AlGaN layer, and a p-type GaN layer (doped with Be, Zn, or Mg) on the active area. Three methods for forming the p-type GaN layer are described: MBE with Be ion implantation, MOCVD growth of Zn-doped GaN, and MOCVD growth of Mg-doped GaN followed by N₂ annealing.
Layer stacks claimed or described, ordered top of device to substrate.
GaN substrate with p-type conducting layer
semiconductor device on GaN substrate
Materials described outside the worked examples.
sapphire
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ | GaN:Mg |
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,653,588Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for fabricating a GaN substrate according to an embodiment of the present invention; [0015]
FIG. 2 is a schematic flowchart of a method for fabricating a GaN substrate according to another embodiment of the present invention; [0016]
FIG. 3 is a schematic structural diagram of a GaN substrate according to still another embodiment of the present invention; [0017]
FIG. 4 is a schematic structural diagram of a GaN substrate according to yet another embodiment of the present invention; and 291980-v 1/4202-62400 3 Atty. …
FIG. 5E are schematic structural diagrams of a semiconductor device according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) substrate, comprising: a GaN base; an aluminum gallium nitride (AlGaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A l GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the AlGaN layer.
The GaN substrate according to claim 1, wherein the GaN base comprises: a base layer made of silicon carbide (SiC), sapphire, or silicon (Si); and a GaN layer disposed on the base layer.
A semiconductor device, comprising: a gallium nitride (GaN) substrate; and a semiconductor structure formed on the GaN substrate, wherein the GaN substrate comprises: a GaN base; an aluminum gallium nitride (A I GaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A I GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between a gate electrode and at least one of a source and a drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the A I GaN layer.
The semiconductor device of claim 5, wherein in a range of 10 7 ' to 10 8 cm3. 398179-v1/4202-62400 of 10 17 to 10 18 cm3. the p-type conducting layer has a hole density
A method for fabricating a gallium nitride (GaN) substrate, comprising: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a. gate electrode, a source, and a drain on an active area of the A l GaN layer; and forming a p-type conducting layer on the active area of the A 1 GaN layer, wherein the p- type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A I GaN layer and neutralize a dangling bond on the A I GaN layer. 398179-vI/4202-62400 3 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the GaN substrate according to claim 6, wherein before forming the A l GaN layer on the GaN base, the method further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the GaN substrate according to claim 6, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
1 1. A method for fabricating a semiconductor device, comprising: forming a gallium nitride (GaN) substrate by using a method for fabricating a GaN substrate; and forming a semiconductor structure on the GaN substrate, wherein the method for fabricating the GaN substrate comprises: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a gate electrode, a source, and a drain on an active area of the A I GaN layer; and forming a p-type conducting layer on the active area of the A l GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A L GaN layer and neutralize a dangling bond on the A l GaN layer. 398179-v 1/4202-62400 5 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the semiconductor device according to claim 11, wherein before forming the A I GaN layer on the GaN base, the method for fabricating the GaN substrate further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the semiconductor device according to claim 11, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Method for fabricating a GaN substrate by forming an AlGaN layer on a GaN base and then forming a p-type conducting layer on the active area of the AlGaN layer to exhaust surface state negative electrons and neutralize dangling bonds.
8 materials5 process steps
Detailed method for forming a GaN substrate on a SiC base layer with an AlN buffer layer, a GaN layer, an AlGaN layer, and a p-type GaN layer (doped with Be, Zn, or Mg) on the active area. Three methods for forming the p-type GaN layer are described: MBE with Be ion implantation, MOCVD growth of Zn-doped GaN, and MOCVD growth of Mg-doped GaN followed by N₂ annealing.
Layer stacks claimed or described, ordered top of device to substrate.
GaN substrate with p-type conducting layer
semiconductor device on GaN substrate
Materials described outside the worked examples.
sapphire
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ | GaN:Mg |
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,653,588Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic flowchart of a method for fabricating a GaN substrate according to an embodiment of the present invention; [0015]
FIG. 2 is a schematic flowchart of a method for fabricating a GaN substrate according to another embodiment of the present invention; [0016]
FIG. 3 is a schematic structural diagram of a GaN substrate according to still another embodiment of the present invention; [0017]
FIG. 4 is a schematic structural diagram of a GaN substrate according to yet another embodiment of the present invention; and 291980-v 1/4202-62400 3 Atty. …
FIG. 5E are schematic structural diagrams of a semiconductor device according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride (GaN) substrate, comprising: a GaN base; an aluminum gallium nitride (AlGaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A l GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the AlGaN layer.
The GaN substrate according to claim 1, wherein the GaN base comprises: a base layer made of silicon carbide (SiC), sapphire, or silicon (Si); and a GaN layer disposed on the base layer.
A semiconductor device, comprising: a gallium nitride (GaN) substrate; and a semiconductor structure formed on the GaN substrate, wherein the GaN substrate comprises: a GaN base; an aluminum gallium nitride (A I GaN) layer disposed on the GaN base; a p-type conducting layer disposed on an active area of the A I GaN layer; and a gate electrode, a source, and a drain disposed on the active area of the A I GaN layer, wherein the p-type conducting layer is laterally spaced between a gate electrode and at least one of a source and a drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A l GaN layer and neutralize a dangling bond on the A I GaN layer.
The semiconductor device of claim 5, wherein in a range of 10 7 ' to 10 8 cm3. 398179-v1/4202-62400 of 10 17 to 10 18 cm3. the p-type conducting layer has a hole density
A method for fabricating a gallium nitride (GaN) substrate, comprising: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a. gate electrode, a source, and a drain on an active area of the A l GaN layer; and forming a p-type conducting layer on the active area of the A 1 GaN layer, wherein the p- type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A I GaN layer and neutralize a dangling bond on the A I GaN layer. 398179-vI/4202-62400 3 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the GaN substrate according to claim 6, wherein before forming the A l GaN layer on the GaN base, the method further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the GaN substrate according to claim 6, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
1 1. A method for fabricating a semiconductor device, comprising: forming a gallium nitride (GaN) substrate by using a method for fabricating a GaN substrate; and forming a semiconductor structure on the GaN substrate, wherein the method for fabricating the GaN substrate comprises: forming an aluminum gallium nitride (A l GaN) layer on a GaN base; forming a gate electrode, a source, and a drain on an active area of the A I GaN layer; and forming a p-type conducting layer on the active area of the A l GaN layer, wherein the p-type conducting layer is laterally spaced between the gate electrode and at least one of the source and the drain, and wherein the p-type conducting layer is configured to exhaust surface state negative electrons on the A L GaN layer and neutralize a dangling bond on the A l GaN layer. 398179-v 1/4202-62400 5 Atty. Docket: 4202-62400 (83371582USO₄)
The method for fabricating the semiconductor device according to claim 11, wherein before forming the A I GaN layer on the GaN base, the method for fabricating the GaN substrate further comprises forming the GaN base, wherein forming the GaN base comprises: providing a base layer, wherein the base layer is made of silicon carbide (SiC), sapphire, or silicon (Si); and forming a GaN layer on the base layer.
The method for fabricating the semiconductor device according to claim 11, wherein forming the p-type conducting layer on the active area of the A I GaN layer comprises forming a p-type GaN layer on the active area of the A l GaN layer.
Embodiments described in the patent, grouped by the materials and process steps they use.
3 materials1 process step
Method for fabricating a GaN substrate by forming an AlGaN layer on a GaN base and then forming a p-type conducting layer on the active area of the AlGaN layer to exhaust surface state negative electrons and neutralize dangling bonds.
8 materials5 process steps
Detailed method for forming a GaN substrate on a SiC base layer with an AlN buffer layer, a GaN layer, an AlGaN layer, and a p-type GaN layer (doped with Be, Zn, or Mg) on the active area. Three methods for forming the p-type GaN layer are described: MBE with Be ion implantation, MOCVD growth of Zn-doped GaN, and MOCVD growth of Mg-doped GaN followed by N₂ annealing.
Layer stacks claimed or described, ordered top of device to substrate.
GaN substrate with p-type conducting layer
semiconductor device on GaN substrate
Materials described outside the worked examples.
sapphire
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ | GaN:Mg |
Hole Density | 100000000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Hole Density | 1000000000000000000 cm⁻³ | GaN:Be |
Thickness | 25–35 nm | — |
Thickness | 1–2 µm | — |
Thickness | 8–12 nm | — |
Pressure | 2–3 Pa | — |
Temperature | 700–800 °C | — |
Duration | 20–30 minutes | — |
Thickness | 10–200 nm | — |
Temperature | 900–1100 °C | — |
Thickness | 14–16 nm | — |
Thickness | 10–15 nm | — |
Duration | 2–3 minutes | — |
Hole Density | 1000000000000000000 cm⁻³ | GaN:Be |
Thickness | 25–35 nm | — |
Thickness | 1–2 µm | — |
Thickness | 8–12 nm | — |
Pressure | 2–3 Pa | — |
Temperature | 700–800 °C | — |
Duration | 20–30 minutes | — |
Thickness | 10–200 nm | — |
Temperature | 900–1100 °C | — |
Thickness | 14–16 nm | — |
Thickness | 10–15 nm | — |
Duration | 2–3 minutes | — |
Hole Density | 1000000000000000000 cm⁻³ | GaN:Be |
Thickness | 25–35 nm | — |
Thickness | 1–2 µm | — |
Thickness | 8–12 nm | — |
Pressure | 2–3 Pa | — |
Temperature | 700–800 °C | — |
Duration | 20–30 minutes | — |
Thickness | 10–200 nm | — |
Temperature | 900–1100 °C | — |
Thickness | 14–16 nm | — |
Thickness | 10–15 nm | — |
Duration | 2–3 minutes | — |
Hole Density | 1000000000000000000 cm⁻³ | GaN:Be |
Thickness | 25–35 nm | — |
Thickness | 1–2 µm | — |
Thickness | 8–12 nm | — |
Pressure | 2–3 Pa | — |
Temperature | 700–800 °C | — |
Duration | 20–30 minutes | — |
Thickness | 10–200 nm | — |
Temperature | 900–1100 °C | — |
Thickness | 14–16 nm | — |
Thickness | 10–15 nm | — |
Duration | 2–3 minutes | — |