Patent
US 10,475,889GALLIUM NITRIDE POWER AMPLIFIER INTEGRATION WITH METAL-OXIDE-SEMICONDUCTOR DEVICES
Xia LI
QUALCOMM·US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,475,889Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a vertical power amplifier (PA) device and complementary metal-oxide-semiconductor …
FIG. 2 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and CMOS control logic device integrated on a same wafer-level …
FIG. 3 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a metal-oxide-semiconductor (MOS) control logic device …
FIG. 4 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a MOS control logic device integrated on a same wafer-level …
FIG. 5I. Oxide 562 (e.g., Si O 2) is then deposited in the STI regions 524, 526, 528, 530, 532, and 534, and subsequently etched to expose the top of fins 106A, …
FIG. 6 is a flow diagram illustrating example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a semiconductor region disposed adjacent to the substrate; at least one first fin disposed adjacent to the semiconductor region; at least one first gate region disposed adjacent to the at least one first fin; at least one first drain contact disposed above the at least one first fin; at least one first source contact disposed below the substrate, wherein at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path; a second fin disposed above the semiconductor region; at least one second gate region disposed adjacent to the second fin; and a second source contact and a second drain contact disposed adjacent to the second fin and above the semiconductor region, wherein a second path is formed between the second source contact and the second drain contact for a second current flow through the second fin in a first horizontal direction along the second path. Original
The semiconductor device of claim 1, wherein a first side of the at least one first gate region and a second side of the at least one first gate region are on opposite sides of the at least one first fin. Original
(Original The semiconductor device of claim 1, further comprising: a third fin disposed above the semiconductor region; at least one third gate region disposed adjacent to the third fin; and a third source contact and a third drain contact disposed adjacent to the third fin and above the semiconductor region, wherein a third path is formed between the third source contact and the third drain contact for a third current flow through the third fin in a second horizontal direction along the third path.
The semiconductor device of claim 1, wherein the semiconductor region comprises at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). Original
The semiconductor device of claim 1, wherein the substrate comprises gallium nitride (GaN). Original
The semiconductor device of claim 1, wherein the at least one first drain contact is patterned. Original
The semiconductor device of claim 1, wherein: the substrate comprises a wafer-level substrate; and the at least one first fin and the second fin share the wafer-level substrate. Original
20-30. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials
A cross-sectional view of a semiconductor device 100 having a vertical PA 102 (vertical FinFET) and horizontal CMOS device 104 integrated on the same wafer-level substrate. The vertical PA includes fins 106A, 106B, 106C disposed above semiconductor region 108. Substrate 130 may include GaN with thickness approximately 100-300 micrometers. Semiconductor region 108 includes semiconductor layer 122 (n-doped GaN) and semiconductor layer 124, which includes semiconductor portion 126 (n-doped GaN) and semiconductor portion 128 (p-doped AlGaN, p-doped InGaN and/or Mg-doped P-GaN). Semiconductor portions 126 and 128 may each have a thickness approximately equal to 6 micrometers.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with vertical FinFET and horizontal MOS/CMOS integration
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate thickness | 100–300 micrometer | GaN |
semiconductor portion 126 and/or 128 thickness | 6 micrometer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,475,889Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a vertical power amplifier (PA) device and complementary metal-oxide-semiconductor …
FIG. 2 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and CMOS control logic device integrated on a same wafer-level …
FIG. 3 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a metal-oxide-semiconductor (MOS) control logic device …
FIG. 4 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a MOS control logic device integrated on a same wafer-level …
FIG. 5I. Oxide 562 (e.g., Si O 2) is then deposited in the STI regions 524, 526, 528, 530, 532, and 534, and subsequently etched to expose the top of fins 106A, …
FIG. 6 is a flow diagram illustrating example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a semiconductor region disposed adjacent to the substrate; at least one first fin disposed adjacent to the semiconductor region; at least one first gate region disposed adjacent to the at least one first fin; at least one first drain contact disposed above the at least one first fin; at least one first source contact disposed below the substrate, wherein at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path; a second fin disposed above the semiconductor region; at least one second gate region disposed adjacent to the second fin; and a second source contact and a second drain contact disposed adjacent to the second fin and above the semiconductor region, wherein a second path is formed between the second source contact and the second drain contact for a second current flow through the second fin in a first horizontal direction along the second path. Original
The semiconductor device of claim 1, wherein a first side of the at least one first gate region and a second side of the at least one first gate region are on opposite sides of the at least one first fin. Original
(Original The semiconductor device of claim 1, further comprising: a third fin disposed above the semiconductor region; at least one third gate region disposed adjacent to the third fin; and a third source contact and a third drain contact disposed adjacent to the third fin and above the semiconductor region, wherein a third path is formed between the third source contact and the third drain contact for a third current flow through the third fin in a second horizontal direction along the third path.
The semiconductor device of claim 1, wherein the semiconductor region comprises at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). Original
The semiconductor device of claim 1, wherein the substrate comprises gallium nitride (GaN). Original
The semiconductor device of claim 1, wherein the at least one first drain contact is patterned. Original
The semiconductor device of claim 1, wherein: the substrate comprises a wafer-level substrate; and the at least one first fin and the second fin share the wafer-level substrate. Original
20-30. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials
A cross-sectional view of a semiconductor device 100 having a vertical PA 102 (vertical FinFET) and horizontal CMOS device 104 integrated on the same wafer-level substrate. The vertical PA includes fins 106A, 106B, 106C disposed above semiconductor region 108. Substrate 130 may include GaN with thickness approximately 100-300 micrometers. Semiconductor region 108 includes semiconductor layer 122 (n-doped GaN) and semiconductor layer 124, which includes semiconductor portion 126 (n-doped GaN) and semiconductor portion 128 (p-doped AlGaN, p-doped InGaN and/or Mg-doped P-GaN). Semiconductor portions 126 and 128 may each have a thickness approximately equal to 6 micrometers.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with vertical FinFET and horizontal MOS/CMOS integration
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate thickness | 100–300 micrometer | GaN |
semiconductor portion 126 and/or 128 thickness | 6 micrometer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,475,889Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a vertical power amplifier (PA) device and complementary metal-oxide-semiconductor …
FIG. 2 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and CMOS control logic device integrated on a same wafer-level …
FIG. 3 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a metal-oxide-semiconductor (MOS) control logic device …
FIG. 4 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a MOS control logic device integrated on a same wafer-level …
FIG. 5I. Oxide 562 (e.g., Si O 2) is then deposited in the STI regions 524, 526, 528, 530, 532, and 534, and subsequently etched to expose the top of fins 106A, …
FIG. 6 is a flow diagram illustrating example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a semiconductor region disposed adjacent to the substrate; at least one first fin disposed adjacent to the semiconductor region; at least one first gate region disposed adjacent to the at least one first fin; at least one first drain contact disposed above the at least one first fin; at least one first source contact disposed below the substrate, wherein at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path; a second fin disposed above the semiconductor region; at least one second gate region disposed adjacent to the second fin; and a second source contact and a second drain contact disposed adjacent to the second fin and above the semiconductor region, wherein a second path is formed between the second source contact and the second drain contact for a second current flow through the second fin in a first horizontal direction along the second path. Original
The semiconductor device of claim 1, wherein a first side of the at least one first gate region and a second side of the at least one first gate region are on opposite sides of the at least one first fin. Original
(Original The semiconductor device of claim 1, further comprising: a third fin disposed above the semiconductor region; at least one third gate region disposed adjacent to the third fin; and a third source contact and a third drain contact disposed adjacent to the third fin and above the semiconductor region, wherein a third path is formed between the third source contact and the third drain contact for a third current flow through the third fin in a second horizontal direction along the third path.
The semiconductor device of claim 1, wherein the semiconductor region comprises at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). Original
The semiconductor device of claim 1, wherein the substrate comprises gallium nitride (GaN). Original
The semiconductor device of claim 1, wherein the at least one first drain contact is patterned. Original
The semiconductor device of claim 1, wherein: the substrate comprises a wafer-level substrate; and the at least one first fin and the second fin share the wafer-level substrate. Original
20-30. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials
A cross-sectional view of a semiconductor device 100 having a vertical PA 102 (vertical FinFET) and horizontal CMOS device 104 integrated on the same wafer-level substrate. The vertical PA includes fins 106A, 106B, 106C disposed above semiconductor region 108. Substrate 130 may include GaN with thickness approximately 100-300 micrometers. Semiconductor region 108 includes semiconductor layer 122 (n-doped GaN) and semiconductor layer 124, which includes semiconductor portion 126 (n-doped GaN) and semiconductor portion 128 (p-doped AlGaN, p-doped InGaN and/or Mg-doped P-GaN). Semiconductor portions 126 and 128 may each have a thickness approximately equal to 6 micrometers.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with vertical FinFET and horizontal MOS/CMOS integration
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate thickness | 100–300 micrometer | GaN |
semiconductor portion 126 and/or 128 thickness | 6 micrometer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,475,889Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a cross-sectional view of a semiconductor device having a vertical power amplifier (PA) device and complementary metal-oxide-semiconductor …
FIG. 2 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and CMOS control logic device integrated on a same wafer-level …
FIG. 3 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a metal-oxide-semiconductor (MOS) control logic device …
FIG. 4 illustrates a cross-sectional view of a semiconductor device having a vertical PA device and a MOS control logic device integrated on a same wafer-level …
FIG. 5I. Oxide 562 (e.g., Si O 2) is then deposited in the STI regions 524, 526, 528, 530, 532, and 534, and subsequently etched to expose the top of fins 106A, …
FIG. 6 is a flow diagram illustrating example operations for fabricating a semiconductor device, in accordance with certain aspects of the present disclosure.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a substrate; a semiconductor region disposed adjacent to the substrate; at least one first fin disposed adjacent to the semiconductor region; at least one first gate region disposed adjacent to the at least one first fin; at least one first drain contact disposed above the at least one first fin; at least one first source contact disposed below the substrate, wherein at least one first path is formed between the at least one first drain contact and the at least one first source contact for a first current flow through the at least one first fin in a vertical direction along the at least one first path; a second fin disposed above the semiconductor region; at least one second gate region disposed adjacent to the second fin; and a second source contact and a second drain contact disposed adjacent to the second fin and above the semiconductor region, wherein a second path is formed between the second source contact and the second drain contact for a second current flow through the second fin in a first horizontal direction along the second path. Original
The semiconductor device of claim 1, wherein a first side of the at least one first gate region and a second side of the at least one first gate region are on opposite sides of the at least one first fin. Original
(Original The semiconductor device of claim 1, further comprising: a third fin disposed above the semiconductor region; at least one third gate region disposed adjacent to the third fin; and a third source contact and a third drain contact disposed adjacent to the third fin and above the semiconductor region, wherein a third path is formed between the third source contact and the third drain contact for a third current flow through the third fin in a second horizontal direction along the third path.
The semiconductor device of claim 1, wherein the semiconductor region comprises at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), or indium gallium nitride (InGaN). Original
The semiconductor device of claim 1, wherein the substrate comprises gallium nitride (GaN). Original
The semiconductor device of claim 1, wherein the at least one first drain contact is patterned. Original
The semiconductor device of claim 1, wherein: the substrate comprises a wafer-level substrate; and the at least one first fin and the second fin share the wafer-level substrate. Original
20-30. Canceled
Canceled
Embodiments described in the patent, grouped by the materials and process steps they use.
5 materials
A cross-sectional view of a semiconductor device 100 having a vertical PA 102 (vertical FinFET) and horizontal CMOS device 104 integrated on the same wafer-level substrate. The vertical PA includes fins 106A, 106B, 106C disposed above semiconductor region 108. Substrate 130 may include GaN with thickness approximately 100-300 micrometers. Semiconductor region 108 includes semiconductor layer 122 (n-doped GaN) and semiconductor layer 124, which includes semiconductor portion 126 (n-doped GaN) and semiconductor portion 128 (p-doped AlGaN, p-doped InGaN and/or Mg-doped P-GaN). Semiconductor portions 126 and 128 may each have a thickness approximately equal to 6 micrometers.
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with vertical FinFET and horizontal MOS/CMOS integration
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 50, a backgrind process may be performed on the backside of the substrate 130 to reduce the thickness of the substrate 502 (e.g., from approximately 700 p …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
substrate thickness | 100–300 micrometer | GaN |
semiconductor portion 126 and/or 128 thickness | 6 micrometer | — |
Related documents with shared materials, methods, properties, or citations.
vertical fin field-effect transistor (FinFET)
horizontal metal-oxide-semiconductor (MOS) device
horizontal complementary metal-oxide-semiconductor (CMOS) device
Thickness | 100–300 µm | — |
vertical fin field-effect transistor (FinFET)
horizontal metal-oxide-semiconductor (MOS) device
horizontal complementary metal-oxide-semiconductor (CMOS) device
Thickness | 100–300 µm | — |
vertical fin field-effect transistor (FinFET)
horizontal metal-oxide-semiconductor (MOS) device
horizontal complementary metal-oxide-semiconductor (CMOS) device
Thickness | 100–300 µm | — |
vertical fin field-effect transistor (FinFET)
horizontal metal-oxide-semiconductor (MOS) device
horizontal complementary metal-oxide-semiconductor (CMOS) device
Thickness | 100–300 µm | — |