Patent
Atlas literature
Patent
US 12,444,600 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional schematic view of a baseline GaN device having a single surface passivation layer; 15
FIGS. 2A-2C depict flowcharts of steps, blocks or acts that may be combined with respect to an example method for fabricating a GaN device having a combination …
FIGS. 3A-3F illustrate cross-sectional schematic views of a semiconductor process wafer portion at various stages of an example process flow for fabricating a …
FIG. 4 depicts a flowchart of steps, blocks or acts of an example fabrication method according to an implementation of the disclosure;
FIGS. 5A and 5B depict example photomasks used for 30 patterning a GaN surface passivation layer in a baseline process and an embodiment of the disclosure, …
FIG. 6A-6D depict additional example patterns defining multiple openings distributed between gate and drain 35 regions of an HEMT device that allow different …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer comprising a first passivation layer portion formed at a first region of the semiconductor device and a second passivation layer portion formed at a second region of the semiconductor device, wherein the first passivation layer portion is formed as part of a first process and the second passivation layer portion is formed as part of a second process, wherein the first passivation layer portion is formed proximate to a drain access region of the semiconductor device, the first passivation layer portion comprising a first dielec-tric material deposited in the first process involving a lower O₂ environment than the second process.
The method as recited in claim 1, wherein the second passivation layer portion is formed proximate to a gate region of the semiconductor device, the second passivation layer portion comprising a second dielectric material depos-ited in the second process involving a higher O₂ environ-ment than the first process.
The method as recited in claim 1, wherein a gate dielectric layer is provided as one of the first or second passivation layers.
The method as recited in claim 1, further comprising: forming a gate dielectric layer over a gate region of the semiconductor device, the gate dielectric layer separate from the first and second passivation layer portions.
The method as recited in claim 1, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an O₂ level less than approximately 30 ppm.
The method as recited in claim 1, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 1, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 1, wherein the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) process, the first process using a first pump stabilization pressure, the first pump stabiliza-tion pressure less than a second pump stabilization pressure used in the second process.
The method as recited in claim 1, wherein the first process is configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device.
The method as recited in claim 1, wherein the second process is configured to deposit a second dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the semiconductor device.
A method of fabricating a gallium nitride (GaN) device, the method comprising: forming a first passivation layer, using a first process, over 5 a top surface of an epitaxial layer of a gallium nitride (GaN) substrate; producing a patterned first passivation layer by removing portions of the first passivation layer corresponding to a gate region opening and a drain access region open-ing; forming a second passivation layer, using a second pro-cess, over the patterned first passivation layer including the gate region opening and the drain access region opening; producing a patterned second passivation layer by remov-ing a portion of the second passivation layer corre-sponding to a gate contact opening in the gate region opening; forming a gate dielectric layer over the patterned second passivation layer; and forming a gate contact, a source contact and a drain contact for the GaN device, the gate contact formed over a portion of the gate dielectric layer disposed in the gate contact opening and the source and drain contacts formed in the epitaxial layer of the GaN substrate, wherein: a portion of the epitaxial layer located laterally between the gate contact and the drain contact includes a first section contacting the first passivation layer and a 30 second section contacting the second passivation layer; and the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) pro-cess, the first process using a first pump stabilization pressure greater than a second pump stabilization pressure used in the second process.
The method as recited in claim 11, wherein the first passivation layer comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm when the GaN device is loaded into an LPCVD chamber.
The method as recited in claim 11, wherein the second passivation layer comprises a silicon nitride layer formed by the second process comprising an LPCVD process using (i) an O₂ level less than approximately 30 ppm when the GaN device is loaded into an LPCVD chamber, and (ii) providing a pump stabilization pressure of about 6 milliTorr (mT) prior to commencing deposition of the second passivation layer.
The method as recited in claim 11, wherein the drain access region opening is laterally separated from the gate region opening by a distance in the epitaxial layer that is at least partially overlaid by a portion of the first passivation layer.
The method as recited in claim 11, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 11, wherein the gate dielectric layer is formed as a silicon nitride layer.
The method as recited in claim 11, wherein: the first section is proximate to the gate contact; and the second section is proximate to the drain contact.
The method as recited in claim 11, wherein the first and second processes each comprise a Low-Pressure Chemi-cal Vapor Deposition (LPCVD) process, the first process using an oxygen (O₂) level that is greater than an oxygen (O₂) level used in the second process.
The method as recited in claim 11, wherein the first process deposits a first dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the GaN device.
The method as recited in claim 11, wherein the second process deposits a second dielectric material for optimizing a dynamic RDSOn performance parameter of the GaN device.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer including a first passivation layer portion proximate to a drain region of the semiconductor device and a second passivation layer portion proximate to a gate region of the semiconductor device, wherein: the first passivation layer portion is formed as a result of a first process configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device; and the second passivation layer portion is formed as part of a second process configured to deposit a second dielec-tric material for optimizing a Time-Dependent Dielec-tric Breakdown (TDDB) parameter of the semiconduc-tor device, wherein the second process involves a higher O₂ environment than the first process.
The method as recited in claim 21, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level less than approximately 30 ppm.
The method as recited in claim 21, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 21, wherein the first process uses a first pump stabilization pressure less than a second pump stabilization pressure of the second process.
The method as recited in claim 21, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with composite surface passivation
Materials described outside the worked examples.
aluminum gallium nitride (AlGaN)
AlGaN
silicon nitride (first passivation layer, low O₂ LPCVD)
Si₃N₄
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,444,600 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional schematic view of a baseline GaN device having a single surface passivation layer; 15
FIGS. 2A-2C depict flowcharts of steps, blocks or acts that may be combined with respect to an example method for fabricating a GaN device having a combination …
FIGS. 3A-3F illustrate cross-sectional schematic views of a semiconductor process wafer portion at various stages of an example process flow for fabricating a …
FIG. 4 depicts a flowchart of steps, blocks or acts of an example fabrication method according to an implementation of the disclosure;
FIGS. 5A and 5B depict example photomasks used for 30 patterning a GaN surface passivation layer in a baseline process and an embodiment of the disclosure, …
FIG. 6A-6D depict additional example patterns defining multiple openings distributed between gate and drain 35 regions of an HEMT device that allow different …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer comprising a first passivation layer portion formed at a first region of the semiconductor device and a second passivation layer portion formed at a second region of the semiconductor device, wherein the first passivation layer portion is formed as part of a first process and the second passivation layer portion is formed as part of a second process, wherein the first passivation layer portion is formed proximate to a drain access region of the semiconductor device, the first passivation layer portion comprising a first dielec-tric material deposited in the first process involving a lower O₂ environment than the second process.
The method as recited in claim 1, wherein the second passivation layer portion is formed proximate to a gate region of the semiconductor device, the second passivation layer portion comprising a second dielectric material depos-ited in the second process involving a higher O₂ environ-ment than the first process.
The method as recited in claim 1, wherein a gate dielectric layer is provided as one of the first or second passivation layers.
The method as recited in claim 1, further comprising: forming a gate dielectric layer over a gate region of the semiconductor device, the gate dielectric layer separate from the first and second passivation layer portions.
The method as recited in claim 1, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an O₂ level less than approximately 30 ppm.
The method as recited in claim 1, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 1, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 1, wherein the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) process, the first process using a first pump stabilization pressure, the first pump stabiliza-tion pressure less than a second pump stabilization pressure used in the second process.
The method as recited in claim 1, wherein the first process is configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device.
The method as recited in claim 1, wherein the second process is configured to deposit a second dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the semiconductor device.
A method of fabricating a gallium nitride (GaN) device, the method comprising: forming a first passivation layer, using a first process, over 5 a top surface of an epitaxial layer of a gallium nitride (GaN) substrate; producing a patterned first passivation layer by removing portions of the first passivation layer corresponding to a gate region opening and a drain access region open-ing; forming a second passivation layer, using a second pro-cess, over the patterned first passivation layer including the gate region opening and the drain access region opening; producing a patterned second passivation layer by remov-ing a portion of the second passivation layer corre-sponding to a gate contact opening in the gate region opening; forming a gate dielectric layer over the patterned second passivation layer; and forming a gate contact, a source contact and a drain contact for the GaN device, the gate contact formed over a portion of the gate dielectric layer disposed in the gate contact opening and the source and drain contacts formed in the epitaxial layer of the GaN substrate, wherein: a portion of the epitaxial layer located laterally between the gate contact and the drain contact includes a first section contacting the first passivation layer and a 30 second section contacting the second passivation layer; and the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) pro-cess, the first process using a first pump stabilization pressure greater than a second pump stabilization pressure used in the second process.
The method as recited in claim 11, wherein the first passivation layer comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm when the GaN device is loaded into an LPCVD chamber.
The method as recited in claim 11, wherein the second passivation layer comprises a silicon nitride layer formed by the second process comprising an LPCVD process using (i) an O₂ level less than approximately 30 ppm when the GaN device is loaded into an LPCVD chamber, and (ii) providing a pump stabilization pressure of about 6 milliTorr (mT) prior to commencing deposition of the second passivation layer.
The method as recited in claim 11, wherein the drain access region opening is laterally separated from the gate region opening by a distance in the epitaxial layer that is at least partially overlaid by a portion of the first passivation layer.
The method as recited in claim 11, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 11, wherein the gate dielectric layer is formed as a silicon nitride layer.
The method as recited in claim 11, wherein: the first section is proximate to the gate contact; and the second section is proximate to the drain contact.
The method as recited in claim 11, wherein the first and second processes each comprise a Low-Pressure Chemi-cal Vapor Deposition (LPCVD) process, the first process using an oxygen (O₂) level that is greater than an oxygen (O₂) level used in the second process.
The method as recited in claim 11, wherein the first process deposits a first dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the GaN device.
The method as recited in claim 11, wherein the second process deposits a second dielectric material for optimizing a dynamic RDSOn performance parameter of the GaN device.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer including a first passivation layer portion proximate to a drain region of the semiconductor device and a second passivation layer portion proximate to a gate region of the semiconductor device, wherein: the first passivation layer portion is formed as a result of a first process configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device; and the second passivation layer portion is formed as part of a second process configured to deposit a second dielec-tric material for optimizing a Time-Dependent Dielec-tric Breakdown (TDDB) parameter of the semiconduc-tor device, wherein the second process involves a higher O₂ environment than the first process.
The method as recited in claim 21, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level less than approximately 30 ppm.
The method as recited in claim 21, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 21, wherein the first process uses a first pump stabilization pressure less than a second pump stabilization pressure of the second process.
The method as recited in claim 21, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with composite surface passivation
Materials described outside the worked examples.
aluminum gallium nitride (AlGaN)
AlGaN
silicon nitride (first passivation layer, low O₂ LPCVD)
Si₃N₄
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,444,600 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional schematic view of a baseline GaN device having a single surface passivation layer; 15
FIGS. 2A-2C depict flowcharts of steps, blocks or acts that may be combined with respect to an example method for fabricating a GaN device having a combination …
FIGS. 3A-3F illustrate cross-sectional schematic views of a semiconductor process wafer portion at various stages of an example process flow for fabricating a …
FIG. 4 depicts a flowchart of steps, blocks or acts of an example fabrication method according to an implementation of the disclosure;
FIGS. 5A and 5B depict example photomasks used for 30 patterning a GaN surface passivation layer in a baseline process and an embodiment of the disclosure, …
FIG. 6A-6D depict additional example patterns defining multiple openings distributed between gate and drain 35 regions of an HEMT device that allow different …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer comprising a first passivation layer portion formed at a first region of the semiconductor device and a second passivation layer portion formed at a second region of the semiconductor device, wherein the first passivation layer portion is formed as part of a first process and the second passivation layer portion is formed as part of a second process, wherein the first passivation layer portion is formed proximate to a drain access region of the semiconductor device, the first passivation layer portion comprising a first dielec-tric material deposited in the first process involving a lower O₂ environment than the second process.
The method as recited in claim 1, wherein the second passivation layer portion is formed proximate to a gate region of the semiconductor device, the second passivation layer portion comprising a second dielectric material depos-ited in the second process involving a higher O₂ environ-ment than the first process.
The method as recited in claim 1, wherein a gate dielectric layer is provided as one of the first or second passivation layers.
The method as recited in claim 1, further comprising: forming a gate dielectric layer over a gate region of the semiconductor device, the gate dielectric layer separate from the first and second passivation layer portions.
The method as recited in claim 1, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an O₂ level less than approximately 30 ppm.
The method as recited in claim 1, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 1, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 1, wherein the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) process, the first process using a first pump stabilization pressure, the first pump stabiliza-tion pressure less than a second pump stabilization pressure used in the second process.
The method as recited in claim 1, wherein the first process is configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device.
The method as recited in claim 1, wherein the second process is configured to deposit a second dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the semiconductor device.
A method of fabricating a gallium nitride (GaN) device, the method comprising: forming a first passivation layer, using a first process, over 5 a top surface of an epitaxial layer of a gallium nitride (GaN) substrate; producing a patterned first passivation layer by removing portions of the first passivation layer corresponding to a gate region opening and a drain access region open-ing; forming a second passivation layer, using a second pro-cess, over the patterned first passivation layer including the gate region opening and the drain access region opening; producing a patterned second passivation layer by remov-ing a portion of the second passivation layer corre-sponding to a gate contact opening in the gate region opening; forming a gate dielectric layer over the patterned second passivation layer; and forming a gate contact, a source contact and a drain contact for the GaN device, the gate contact formed over a portion of the gate dielectric layer disposed in the gate contact opening and the source and drain contacts formed in the epitaxial layer of the GaN substrate, wherein: a portion of the epitaxial layer located laterally between the gate contact and the drain contact includes a first section contacting the first passivation layer and a 30 second section contacting the second passivation layer; and the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) pro-cess, the first process using a first pump stabilization pressure greater than a second pump stabilization pressure used in the second process.
The method as recited in claim 11, wherein the first passivation layer comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm when the GaN device is loaded into an LPCVD chamber.
The method as recited in claim 11, wherein the second passivation layer comprises a silicon nitride layer formed by the second process comprising an LPCVD process using (i) an O₂ level less than approximately 30 ppm when the GaN device is loaded into an LPCVD chamber, and (ii) providing a pump stabilization pressure of about 6 milliTorr (mT) prior to commencing deposition of the second passivation layer.
The method as recited in claim 11, wherein the drain access region opening is laterally separated from the gate region opening by a distance in the epitaxial layer that is at least partially overlaid by a portion of the first passivation layer.
The method as recited in claim 11, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 11, wherein the gate dielectric layer is formed as a silicon nitride layer.
The method as recited in claim 11, wherein: the first section is proximate to the gate contact; and the second section is proximate to the drain contact.
The method as recited in claim 11, wherein the first and second processes each comprise a Low-Pressure Chemi-cal Vapor Deposition (LPCVD) process, the first process using an oxygen (O₂) level that is greater than an oxygen (O₂) level used in the second process.
The method as recited in claim 11, wherein the first process deposits a first dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the GaN device.
The method as recited in claim 11, wherein the second process deposits a second dielectric material for optimizing a dynamic RDSOn performance parameter of the GaN device.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer including a first passivation layer portion proximate to a drain region of the semiconductor device and a second passivation layer portion proximate to a gate region of the semiconductor device, wherein: the first passivation layer portion is formed as a result of a first process configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device; and the second passivation layer portion is formed as part of a second process configured to deposit a second dielec-tric material for optimizing a Time-Dependent Dielec-tric Breakdown (TDDB) parameter of the semiconduc-tor device, wherein the second process involves a higher O₂ environment than the first process.
The method as recited in claim 21, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level less than approximately 30 ppm.
The method as recited in claim 21, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 21, wherein the first process uses a first pump stabilization pressure less than a second pump stabilization pressure of the second process.
The method as recited in claim 21, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with composite surface passivation
Materials described outside the worked examples.
aluminum gallium nitride (AlGaN)
AlGaN
silicon nitride (first passivation layer, low O₂ LPCVD)
Si₃N₄
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,444,600 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional schematic view of a baseline GaN device having a single surface passivation layer; 15
FIGS. 2A-2C depict flowcharts of steps, blocks or acts that may be combined with respect to an example method for fabricating a GaN device having a combination …
FIGS. 3A-3F illustrate cross-sectional schematic views of a semiconductor process wafer portion at various stages of an example process flow for fabricating a …
FIG. 4 depicts a flowchart of steps, blocks or acts of an example fabrication method according to an implementation of the disclosure;
FIGS. 5A and 5B depict example photomasks used for 30 patterning a GaN surface passivation layer in a baseline process and an embodiment of the disclosure, …
FIG. 6A-6D depict additional example patterns defining multiple openings distributed between gate and drain 35 regions of an HEMT device that allow different …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer comprising a first passivation layer portion formed at a first region of the semiconductor device and a second passivation layer portion formed at a second region of the semiconductor device, wherein the first passivation layer portion is formed as part of a first process and the second passivation layer portion is formed as part of a second process, wherein the first passivation layer portion is formed proximate to a drain access region of the semiconductor device, the first passivation layer portion comprising a first dielec-tric material deposited in the first process involving a lower O₂ environment than the second process.
The method as recited in claim 1, wherein the second passivation layer portion is formed proximate to a gate region of the semiconductor device, the second passivation layer portion comprising a second dielectric material depos-ited in the second process involving a higher O₂ environ-ment than the first process.
The method as recited in claim 1, wherein a gate dielectric layer is provided as one of the first or second passivation layers.
The method as recited in claim 1, further comprising: forming a gate dielectric layer over a gate region of the semiconductor device, the gate dielectric layer separate from the first and second passivation layer portions.
The method as recited in claim 1, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an O₂ level less than approximately 30 ppm.
The method as recited in claim 1, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 1, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 1, wherein the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) process, the first process using a first pump stabilization pressure, the first pump stabiliza-tion pressure less than a second pump stabilization pressure used in the second process.
The method as recited in claim 1, wherein the first process is configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device.
The method as recited in claim 1, wherein the second process is configured to deposit a second dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the semiconductor device.
A method of fabricating a gallium nitride (GaN) device, the method comprising: forming a first passivation layer, using a first process, over 5 a top surface of an epitaxial layer of a gallium nitride (GaN) substrate; producing a patterned first passivation layer by removing portions of the first passivation layer corresponding to a gate region opening and a drain access region open-ing; forming a second passivation layer, using a second pro-cess, over the patterned first passivation layer including the gate region opening and the drain access region opening; producing a patterned second passivation layer by remov-ing a portion of the second passivation layer corre-sponding to a gate contact opening in the gate region opening; forming a gate dielectric layer over the patterned second passivation layer; and forming a gate contact, a source contact and a drain contact for the GaN device, the gate contact formed over a portion of the gate dielectric layer disposed in the gate contact opening and the source and drain contacts formed in the epitaxial layer of the GaN substrate, wherein: a portion of the epitaxial layer located laterally between the gate contact and the drain contact includes a first section contacting the first passivation layer and a 30 second section contacting the second passivation layer; and the first and second processes each comprise a Low-Pressure Chemical Vapor Deposition (LPCVD) pro-cess, the first process using a first pump stabilization pressure greater than a second pump stabilization pressure used in the second process.
The method as recited in claim 11, wherein the first passivation layer comprises a silicon nitride layer formed by the first process comprising a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm when the GaN device is loaded into an LPCVD chamber.
The method as recited in claim 11, wherein the second passivation layer comprises a silicon nitride layer formed by the second process comprising an LPCVD process using (i) an O₂ level less than approximately 30 ppm when the GaN device is loaded into an LPCVD chamber, and (ii) providing a pump stabilization pressure of about 6 milliTorr (mT) prior to commencing deposition of the second passivation layer.
The method as recited in claim 11, wherein the drain access region opening is laterally separated from the gate region opening by a distance in the epitaxial layer that is at least partially overlaid by a portion of the first passivation layer.
The method as recited in claim 11, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer.
The method as recited in claim 11, wherein the gate dielectric layer is formed as a silicon nitride layer.
The method as recited in claim 11, wherein: the first section is proximate to the gate contact; and the second section is proximate to the drain contact.
The method as recited in claim 11, wherein the first and second processes each comprise a Low-Pressure Chemi-cal Vapor Deposition (LPCVD) process, the first process using an oxygen (O₂) level that is greater than an oxygen (O₂) level used in the second process.
The method as recited in claim 11, wherein the first process deposits a first dielectric material for optimizing a Time-Dependent Dielectric Breakdown (TDDB) parameter of the GaN device.
The method as recited in claim 11, wherein the second process deposits a second dielectric material for optimizing a dynamic RDSOn performance parameter of the GaN device.
A method of fabricating a semiconductor device, the method comprising: providing a gallium nitride (GaN) substrate with an epitaxial layer formed thereover, the epitaxial layer forming a heterojunction with the GaN substrate; and forming a composite surface passivation layer over the epitaxial layer, the composite surface passivation layer including a first passivation layer portion proximate to a drain region of the semiconductor device and a second passivation layer portion proximate to a gate region of the semiconductor device, wherein: the first passivation layer portion is formed as a result of a first process configured to deposit a first dielectric material for optimizing a dynamic RDSOn performance parameter of the semiconductor device; and the second passivation layer portion is formed as part of a second process configured to deposit a second dielec-tric material for optimizing a Time-Dependent Dielec-tric Breakdown (TDDB) parameter of the semiconduc-tor device, wherein the second process involves a higher O₂ environment than the first process.
The method as recited in claim 21, wherein the first passivation layer portion comprises a silicon nitride layer formed by the first process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level less than approximately 30 ppm.
The method as recited in claim 21, wherein the second passivation layer portion comprises a silicon nitride layer formed by the second process including a Low-Pressure Chemical Vapor Deposition (LPCVD) process using an oxygen (O₂) level of approximately 600 parts per million (ppm) to 1000 ppm.
The method as recited in claim 21, wherein the first process uses a first pump stabilization pressure less than a second pump stabilization pressure of the second process.
The method as recited in claim 21, wherein the epitaxial layer is formed as an aluminum gallium nitride (AlGaN) layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with composite surface passivation
Materials described outside the worked examples.
aluminum gallium nitride (AlGaN)
AlGaN
silicon nitride (first passivation layer, low O₂ LPCVD)
Si₃N₄
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–30 nm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 2
Cited non-patent literature · 1
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