Patent
US 10,692,976GAN-ON-SI SWITCH DEVICES
Jenn Hwa Huang, Weixiao Huang
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,692,976Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a simplified partial cross-sectional view of a semiconductor structure having an epitaxial substrate layer; [007]
Figure 2 illustrates processing of the semiconductor structure subsequent to
Figure 3 illustrates processing of the semiconductor structure subsequent to 15
Figure 4 illustrates processing of the semiconductor structure subsequent to
Figure 5 illustrates processing of the semiconductor structure subsequent to 20
Figure 6 illustrates processing of the semiconductor structure subsequent to
Figure 7 illustrates processing of the semiconductor structure subsequent to
Figure 8 illustrates processing of the semiconductor structure subsequent to
Figure 9 illustrates processing of the semiconductor structure subsequent to
Figure 10 illustrates processing of the semiconductor structure subsequent to
Figure 11 illustrates processing of the semiconductor structure subsequent to
Figure 12 illustrates a side view of the semiconductor structure shown in
Figure 13 illustrates processing of the semiconductor structure subsequent to
Figure 14 is a simplified partial cross-sectional view of a semiconductor structure in which ohmic contact source/drain and gate contacts are formed on a mesa having implanted isolation regions without etching passivation layers; 10 [020]
Figure 15 illustrates a partial overlay plan view of the masks used to form the implant isolation regions on an elevated mesa device; and [021]
Figure 16 is a simplified schematic flow chart illustrating various methods for fabricating devices in accordance with selected embodiments of the invention. [022] It will be appreciated that for simplicity and clarity of illustration, elements 15 illustrated in the drawings have not necessarily been …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of an electrically insulating peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the electrically insulating peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 1, where the substrate comprises an epitaxial layer of gallium nitride (GaN), aluminum nitride (A l N), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (A l InGaN). Original
The semiconductor device of claim 1, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 1, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 1, further comprising: one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure. Previously presented
Canceled
A semiconductor device, comprising: a gallium nitride substrate layer comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; source/drain contacts on the elevated surface of the elevated mesa island structure; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of a peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, [[n]]and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 7, wherein the one or more insulating passivating layers formed on at least the elevated surface of the elevated mesa island structure prior to formation of the implanted isolation region. Currently amended
The semiconductor device of claim 7, where the gallium nitride substrate layer comprises an epitaxial layer of gallium nitride (GaN). Original
The semiconductor device of claim 7, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 7, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 7, further comprising [[:]] one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure; and wherein the one or more gate electrode layers are one or more patterned gate electrode layers on the elevated surface of the elevated mesa island structure. Currently amended
Canceled
A semiconductor structure comprising: a mesa island structure on a first surface of a gallium nitride substrate layer having tapered mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; one or more electrode conductor layers on the elevated surface of the mesa island structure electrically coupled to the gallium nitride substrate layer; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; and an isolation region [[for]] completely surrounding each mesa island structure implanted with ions in an upper portion of the tapered mesa sidewalls and in at least a horizontal face of the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and one or more gate elect rodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor structure of claim 14, where the gallium nitride substrate layer comprises an epitaxial galli u m nitride layer. Original
The semiconductor structure of claim 14, where the one or more electrode conductor layers comprise: one or more current electrode ohmic metal contact layers in electrode contact openings formed on the elevated surface of the mesa structure; and one or more current electrode ohmic metal contact layers formin g one or more ohmic alloy layers in contact with the substrate. Original
The semiconductor structure of claim 14, wherein the one or more insulatin g passivating layers comprise a first passivat i on silicon nitride layer on the elevated surface of the mesa island structure. Currently amended
The semiconductor structure of clai m 15, wherein the one or more insulating passivation layers comprises a first passivation silicon nitride layer on the first su r face of the epitaxial gallium nitride layer formed prior to or as part of forming a mesa etch mask layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with elevated mesa island structure (generic substrate)
metal insulator semiconductor (MIS) transistor
No layer stack recorded.
semiconductor device with GaN elevated mesa island structure
Materials described outside the worked examples.
gallium nitride
GaN
substrate (generic)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,692,976Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a simplified partial cross-sectional view of a semiconductor structure having an epitaxial substrate layer; [007]
Figure 2 illustrates processing of the semiconductor structure subsequent to
Figure 3 illustrates processing of the semiconductor structure subsequent to 15
Figure 4 illustrates processing of the semiconductor structure subsequent to
Figure 5 illustrates processing of the semiconductor structure subsequent to 20
Figure 6 illustrates processing of the semiconductor structure subsequent to
Figure 7 illustrates processing of the semiconductor structure subsequent to
Figure 8 illustrates processing of the semiconductor structure subsequent to
Figure 9 illustrates processing of the semiconductor structure subsequent to
Figure 10 illustrates processing of the semiconductor structure subsequent to
Figure 11 illustrates processing of the semiconductor structure subsequent to
Figure 12 illustrates a side view of the semiconductor structure shown in
Figure 13 illustrates processing of the semiconductor structure subsequent to
Figure 14 is a simplified partial cross-sectional view of a semiconductor structure in which ohmic contact source/drain and gate contacts are formed on a mesa having implanted isolation regions without etching passivation layers; 10 [020]
Figure 15 illustrates a partial overlay plan view of the masks used to form the implant isolation regions on an elevated mesa device; and [021]
Figure 16 is a simplified schematic flow chart illustrating various methods for fabricating devices in accordance with selected embodiments of the invention. [022] It will be appreciated that for simplicity and clarity of illustration, elements 15 illustrated in the drawings have not necessarily been …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of an electrically insulating peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the electrically insulating peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 1, where the substrate comprises an epitaxial layer of gallium nitride (GaN), aluminum nitride (A l N), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (A l InGaN). Original
The semiconductor device of claim 1, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 1, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 1, further comprising: one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure. Previously presented
Canceled
A semiconductor device, comprising: a gallium nitride substrate layer comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; source/drain contacts on the elevated surface of the elevated mesa island structure; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of a peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, [[n]]and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 7, wherein the one or more insulating passivating layers formed on at least the elevated surface of the elevated mesa island structure prior to formation of the implanted isolation region. Currently amended
The semiconductor device of claim 7, where the gallium nitride substrate layer comprises an epitaxial layer of gallium nitride (GaN). Original
The semiconductor device of claim 7, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 7, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 7, further comprising [[:]] one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure; and wherein the one or more gate electrode layers are one or more patterned gate electrode layers on the elevated surface of the elevated mesa island structure. Currently amended
Canceled
A semiconductor structure comprising: a mesa island structure on a first surface of a gallium nitride substrate layer having tapered mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; one or more electrode conductor layers on the elevated surface of the mesa island structure electrically coupled to the gallium nitride substrate layer; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; and an isolation region [[for]] completely surrounding each mesa island structure implanted with ions in an upper portion of the tapered mesa sidewalls and in at least a horizontal face of the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and one or more gate elect rodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor structure of claim 14, where the gallium nitride substrate layer comprises an epitaxial galli u m nitride layer. Original
The semiconductor structure of claim 14, where the one or more electrode conductor layers comprise: one or more current electrode ohmic metal contact layers in electrode contact openings formed on the elevated surface of the mesa structure; and one or more current electrode ohmic metal contact layers formin g one or more ohmic alloy layers in contact with the substrate. Original
The semiconductor structure of claim 14, wherein the one or more insulatin g passivating layers comprise a first passivat i on silicon nitride layer on the elevated surface of the mesa island structure. Currently amended
The semiconductor structure of clai m 15, wherein the one or more insulating passivation layers comprises a first passivation silicon nitride layer on the first su r face of the epitaxial gallium nitride layer formed prior to or as part of forming a mesa etch mask layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with elevated mesa island structure (generic substrate)
metal insulator semiconductor (MIS) transistor
No layer stack recorded.
semiconductor device with GaN elevated mesa island structure
Materials described outside the worked examples.
gallium nitride
GaN
substrate (generic)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,692,976Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a simplified partial cross-sectional view of a semiconductor structure having an epitaxial substrate layer; [007]
Figure 2 illustrates processing of the semiconductor structure subsequent to
Figure 3 illustrates processing of the semiconductor structure subsequent to 15
Figure 4 illustrates processing of the semiconductor structure subsequent to
Figure 5 illustrates processing of the semiconductor structure subsequent to 20
Figure 6 illustrates processing of the semiconductor structure subsequent to
Figure 7 illustrates processing of the semiconductor structure subsequent to
Figure 8 illustrates processing of the semiconductor structure subsequent to
Figure 9 illustrates processing of the semiconductor structure subsequent to
Figure 10 illustrates processing of the semiconductor structure subsequent to
Figure 11 illustrates processing of the semiconductor structure subsequent to
Figure 12 illustrates a side view of the semiconductor structure shown in
Figure 13 illustrates processing of the semiconductor structure subsequent to
Figure 14 is a simplified partial cross-sectional view of a semiconductor structure in which ohmic contact source/drain and gate contacts are formed on a mesa having implanted isolation regions without etching passivation layers; 10 [020]
Figure 15 illustrates a partial overlay plan view of the masks used to form the implant isolation regions on an elevated mesa device; and [021]
Figure 16 is a simplified schematic flow chart illustrating various methods for fabricating devices in accordance with selected embodiments of the invention. [022] It will be appreciated that for simplicity and clarity of illustration, elements 15 illustrated in the drawings have not necessarily been …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of an electrically insulating peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the electrically insulating peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 1, where the substrate comprises an epitaxial layer of gallium nitride (GaN), aluminum nitride (A l N), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (A l InGaN). Original
The semiconductor device of claim 1, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 1, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 1, further comprising: one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure. Previously presented
Canceled
A semiconductor device, comprising: a gallium nitride substrate layer comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; source/drain contacts on the elevated surface of the elevated mesa island structure; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of a peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, [[n]]and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 7, wherein the one or more insulating passivating layers formed on at least the elevated surface of the elevated mesa island structure prior to formation of the implanted isolation region. Currently amended
The semiconductor device of claim 7, where the gallium nitride substrate layer comprises an epitaxial layer of gallium nitride (GaN). Original
The semiconductor device of claim 7, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 7, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 7, further comprising [[:]] one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure; and wherein the one or more gate electrode layers are one or more patterned gate electrode layers on the elevated surface of the elevated mesa island structure. Currently amended
Canceled
A semiconductor structure comprising: a mesa island structure on a first surface of a gallium nitride substrate layer having tapered mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; one or more electrode conductor layers on the elevated surface of the mesa island structure electrically coupled to the gallium nitride substrate layer; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; and an isolation region [[for]] completely surrounding each mesa island structure implanted with ions in an upper portion of the tapered mesa sidewalls and in at least a horizontal face of the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and one or more gate elect rodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor structure of claim 14, where the gallium nitride substrate layer comprises an epitaxial galli u m nitride layer. Original
The semiconductor structure of claim 14, where the one or more electrode conductor layers comprise: one or more current electrode ohmic metal contact layers in electrode contact openings formed on the elevated surface of the mesa structure; and one or more current electrode ohmic metal contact layers formin g one or more ohmic alloy layers in contact with the substrate. Original
The semiconductor structure of claim 14, wherein the one or more insulatin g passivating layers comprise a first passivat i on silicon nitride layer on the elevated surface of the mesa island structure. Currently amended
The semiconductor structure of clai m 15, wherein the one or more insulating passivation layers comprises a first passivation silicon nitride layer on the first su r face of the epitaxial gallium nitride layer formed prior to or as part of forming a mesa etch mask layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with elevated mesa island structure (generic substrate)
metal insulator semiconductor (MIS) transistor
No layer stack recorded.
semiconductor device with GaN elevated mesa island structure
Materials described outside the worked examples.
gallium nitride
GaN
substrate (generic)
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,692,976Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a simplified partial cross-sectional view of a semiconductor structure having an epitaxial substrate layer; [007]
Figure 2 illustrates processing of the semiconductor structure subsequent to
Figure 3 illustrates processing of the semiconductor structure subsequent to 15
Figure 4 illustrates processing of the semiconductor structure subsequent to
Figure 5 illustrates processing of the semiconductor structure subsequent to 20
Figure 6 illustrates processing of the semiconductor structure subsequent to
Figure 7 illustrates processing of the semiconductor structure subsequent to
Figure 8 illustrates processing of the semiconductor structure subsequent to
Figure 9 illustrates processing of the semiconductor structure subsequent to
Figure 10 illustrates processing of the semiconductor structure subsequent to
Figure 11 illustrates processing of the semiconductor structure subsequent to
Figure 12 illustrates a side view of the semiconductor structure shown in
Figure 13 illustrates processing of the semiconductor structure subsequent to
Figure 14 is a simplified partial cross-sectional view of a semiconductor structure in which ohmic contact source/drain and gate contacts are formed on a mesa having implanted isolation regions without etching passivation layers; 10 [020]
Figure 15 illustrates a partial overlay plan view of the masks used to form the implant isolation regions on an elevated mesa device; and [021]
Figure 16 is a simplified schematic flow chart illustrating various methods for fabricating devices in accordance with selected embodiments of the invention. [022] It will be appreciated that for simplicity and clarity of illustration, elements 15 illustrated in the drawings have not necessarily been …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of an electrically insulating peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the electrically insulating peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 1, where the substrate comprises an epitaxial layer of gallium nitride (GaN), aluminum nitride (A l N), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (A l InGaN). Original
The semiconductor device of claim 1, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 1, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 1, further comprising: one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure. Previously presented
Canceled
A semiconductor device, comprising: a gallium nitride substrate layer comprising an elevated mesa island structure defining one or more active areas and surrounded by one or more recessed areas in the substrate defining one or more inactive areas, where the elevated mesa island structure has mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; source/drain contacts on the elevated surface of the elevated mesa island structure; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; an implanted isolation region formed around and completely surrounding the elevated mesa island structure in the mesa sidewalls and in at least a horizontal face of a peripheral edge region of the elevated surface adjacent the mesa sidewalls, where the implanted isolation region comprises an upper region of the substrate having defects, vacancies and/or an amorphous crystal structure to provide isolation for the mesa sidewalls and peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and active devices formed on the elevated mesa island structure that include one or more gate electrodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, [[n]]and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor device of claim 7, wherein the one or more insulating passivating layers formed on at least the elevated surface of the elevated mesa island structure prior to formation of the implanted isolation region. Currently amended
The semiconductor device of claim 7, where the gallium nitride substrate layer comprises an epitaxial layer of gallium nitride (GaN). Original
The semiconductor device of claim 7, where the implanted isolation region extends on the elevated surface of the elevated mesa island structure by a first distance. Original
The semiconductor device of claim 7, where the active devices comprise one or more metal insulator semiconductor (MIS) transistors. Original
The semiconductor device of claim 7, further comprising [[:]] one or more patterned current electrode layers formed on the elevated surface of the elevated mesa island structure; and wherein the one or more gate electrode layers are one or more patterned gate electrode layers on the elevated surface of the elevated mesa island structure. Currently amended
Canceled
A semiconductor structure comprising: a mesa island structure on a first surface of a gallium nitride substrate layer having tapered mesa sidewalls and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a lower upper facing surface of the gallium nitride substrate layer; one or more electrode conductor layers on the elevated surface of the mesa island structure electrically coupled to the gallium nitride substrate layer; an electrically insulating peripheral edge region around the elevated surface of the mesa island structure implanted with ions; and an isolation region [[for]] completely surrounding each mesa island structure implanted with ions in an upper portion of the tapered mesa sidewalls and in at least a horizontal face of the electrically insulating peripheral edge region; one or more insulating passivating layers formed on at least the mesa sidewalls and the elevated surface of the elevated mesa island structure; and one or more gate elect rodes on the elevated surface of the mesa island structure, where the one or more gate electrodes overlap the peripheral edge region, and where the implanted isolation region extends beyond an end of the one or more gate electrodes. Currently amended
The semiconductor structure of claim 14, where the gallium nitride substrate layer comprises an epitaxial galli u m nitride layer. Original
The semiconductor structure of claim 14, where the one or more electrode conductor layers comprise: one or more current electrode ohmic metal contact layers in electrode contact openings formed on the elevated surface of the mesa structure; and one or more current electrode ohmic metal contact layers formin g one or more ohmic alloy layers in contact with the substrate. Original
The semiconductor structure of claim 14, wherein the one or more insulatin g passivating layers comprise a first passivat i on silicon nitride layer on the elevated surface of the mesa island structure. Currently amended
The semiconductor structure of clai m 15, wherein the one or more insulating passivation layers comprises a first passivation silicon nitride layer on the first su r face of the epitaxial gallium nitride layer formed prior to or as part of forming a mesa etch mask layer. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor device with elevated mesa island structure (generic substrate)
metal insulator semiconductor (MIS) transistor
No layer stack recorded.
semiconductor device with GaN elevated mesa island structure
Materials described outside the worked examples.
gallium nitride
GaN
substrate (generic)
Related documents with shared materials, methods, properties, or citations.
semiconductor structure with GaN mesa island and tapered sidewalls
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
silicon nitride
Si₃N₄
semiconductor structure with GaN mesa island and tapered sidewalls
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
silicon nitride
Si₃N₄
semiconductor structure with GaN mesa island and tapered sidewalls
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
silicon nitride
Si₃N₄
semiconductor structure with GaN mesa island and tapered sidewalls
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
indium gallium nitride
InGaN
aluminum indium gallium nitride
AlInGaN
silicon nitride
Si₃N₄