HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES

Bruce M. Green

Patent

Atlas literature

Patent

US 9,276,101

HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES

Bruce M. Green, Karen E. Moore, Olin Hartin

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

23 independent · 13 dependent

1
Independent
1-16. canceled
2
Independent
canceled
3
Independent
canceled
4
Independent
canceled
5
Independent
canceled
6
Independent
canceled
7
Independent
canceled
8
Independent
canceled
9
Independent
canceled
10
Independent
canceled
11
Independent
canceled
12
Independent
canceled
13
Independent
canceled
14
Independent
canceled
15
Independent
canceled
16
Independent
canceled
17
IndependentGaNpassivation surface layerconformal passivation layersemiconductor device with GaN layer, T-gate, and MIM capacitor
A semiconductor device, comprising: a substrate comprising one or more active areas with a gallium nitride layer; a passivation surface layer covering the gallium nitride layer with a gate electrode opening deﬁned by passivation surface layer sidewalls separated by a ﬁrst width; a conductive gate electrode located at least in part in the gate electrode opening to be in contact with the gallium nitride layer, where the conductive gate electrode comprises a lower contact base having vertical sidewalls and upper gate electrode sidewall extensions formed to be vertically spaced apart from the passivation surface layer by a minimum vertical gap distance; a ﬁrst patterned metal layer deﬁning one or more bottom capacitor plate layers which are electrically isolated from the substrate; and one or more passivation layers located on at least a portion of the vertical sidewalls of the contact base and on a top surface of the one or more bottom capacitor plate lavers; and a second patterned metal layer deﬁning one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.
1. 18
  Dependent← claim 17semiconductor device with GaN layer, T-gate, and MIM capacitor
  The semiconductor device of claim 17, where the contact base has a width that is narrower than the ﬁrst width such that the one or more passivation layers cover the entirety of the vertical sidewalls of the contact base.
2. 19
  Dependent← claim 17semiconductor device with GaN layer, T-gate, and MIM capacitor
  The semiconductor device of claim 17, where contact base has a width that is equal to the ﬁrst width such that the one or more passivation layers cover vertical sidewalls of the contact base except where the contact base is in direct contact with the passivation surface layer sidewalls.
3. 20
  Dependent← claim 17semiconductor device with GaN layer, T-gate, and MIM capacitor
  The semiconductor device of claim 17, where the one or more passivation layers located on the vertical sidewalls of the contact base have a total thickness that is controlled to prevent an increase in total gate capacitance by more than 10 % as compared to a 3 conductive gate electrode that does not have one or more passivation layers located on the vertical sidewalls of the contact base.
21
IndependentGaNpassivation surface layerconformal passivation layergallium nitride transistor device with T-gate and integrated MIM capacitor
A gallium nitride transistor device, comprising: a substrate comprising an epitaxial gallium nitride surface layer; a passivation surface layer covering the epitaxial gallium nitride surface layer except for a gate contact opening and source/drain contact openings; a conductive gate electrode comprising: a contact base portion formed over the epitaxial gallium nitride surface layer in the gate contact opening, and gate electrode sidewall extensions that overlap with the passivation surface layer and are vertically spaced above the passivation surface layer by a vertical gap; a ﬁrst plurality of patterned conductor layers deﬁning (1) source/drain electrode layers in electrical contact with the epitaxial gallium nitride surface layer through the source/drain contact openings and (2) one or more bottom capacitor plate layers which are electrically isolated from the substrate; a passivation layer covering exposed sidewall surfaces of the conductive gate electrode and a top surface of the one or more bottom capacitor plate layers, wherein a portion of the passivation layer is formed on a vertical sidewall of the contact base portion located below the gate electrode sidewall extensions; and a second plurality of patterned conductor layers deﬁning (1) additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and (2) one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the passivation layer.
1. 22
  Dependent← claim 21GaNAlGaNGaNgallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the substrate comprises an upper gallium nitride cap layer, a middle aluminum gallium nitride ba rri er layer, and an underlying gallium nitride buﬀer layer.
2. 23
  Dependent← claim 21Si₃N₄gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the passivation surface layer comprises a layer of low-pressure chemical vapor deposition silicon nitride having a thickness of about 50-150 A. 4
3. 24
  Dependent← claim 21Nigallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the conductive gate electrode comprises a Schottky gate electrode comprising nickel.
4. 25
  Dependent← claim 21conformal passivation layergallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the passivation layer comprises a low hydrogen content and low ionic or electronic charge content passivation layer having a thickness of approximately 300 A.
5. 26
  Dependent← claim 21gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the gate electrode sidewall extensions are vertically spaced apart from the passivation surface layer by a vertical gap and where the contact base portion of the conductive gate electrode is laterally separated from the passivation surface layer by a lateral gap.
6. 27
  Dependent← claim 21gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the contact base portion of the conductive gate electrode comprises a bottom diﬀusion barrier metal layer and an upper Schottky metal layer.
7. 29
  Dependent← claim 21gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where the one or more bottom capacitor plate layers are located over an isolation region formed in the substrate.
8. 30
  Dependent← claim 21gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, further comprising one or more conformal dielectric layers formed on the passivation layer covering exposed sidewall surfaces of the conductive gate electrode to form a vertical metal-insulator-semiconductor (MIS) sandwich along the vertical edges of the contact base portion of the conductive gate electrode to reduce leakage and ensure high-voltage operation.
9. 31
  Dependent← claim 21gallium nitride transistor device with T-gate and integrated MIM capacitor
  The gallium nitride transistor device of claim 21, where each of the one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the passivation layer comprise a Metal-Insulator-Metal capacitor.
32
IndependentGaNpassivation surface layerconformal passivation layerintegrated circuit device with GaN mesa, T-gate, and MIM capacitor
A integrated circuit device, comprising: a semiconductor layer comprising an elevated mesa section comprising a gallium nitride surface layer; 5 a passivation surface layer covering the covering the elevated mesa section, where the passivation surface layer comprises a gate contact opening and source/drain contact openings deﬁned to expose the gallium nitride surface layer; a conductive gate electrode positioned within the gate contact opening, where the conductive gate electrode comprises a gate length contact base having a gate length and gate electrode sidewall extensions formed to be vertically spaced apart from the passivation surface layer by a minimum vertical gap distance YGATE; a ﬁrst plurality of patterned conductor layers deﬁning (1) source/drain electrode layers in electrical contact with the gallium nitride surface layer and (2) one or more bottom capacitor plate layers which are electrically isolated from the semiconductor layer; one or more passivation layers covering exposed sidewall surfaces of the conductive gate electrode and the one or more bottom capacitor plate layers; and a second plurality of patterned conductor layers deﬁning (1) additional source/drain electrode layers in ohmic contact with the source/drain electrode layers and (2) one or more top capacitor plate layers which are separated from the one or more bottom capacitor plate layers by the one or more passivation layers.
33
Independentintegrated circuit device with GaN mesa, T-gate, and MIM capacitor
The integrated circuit device of 32, where the gate length contact base is in direct contact with the passivation surface layer in the gate contact opening.
34
Independentintegrated circuit device with GaN mesa, T-gate, and MIM capacitor
The integrated circuit device of 33, where the one or more passivation layers on the conductive gate electrode cover exposed sidewall surfaces of the conductive gate electrode except where the gate length contact base is in direct contact with the passivation surface layer.
35
Independentintegrated circuit device with GaN mesa, T-gate, and MIM capacitor
The integrated circuit device of 32, where the gate length contact base is laterally spaced apart from the passivation surface layer in the gate contact opening.
36
Independentintegrated circuit device with GaN mesa, T-gate, and MIM capacitor
The integrated circuit device of 35, where the one or more passivation layers on the conductive gate electrode cover exposed sidewall surfaces of the conductive gate electrode including the exposed gate length contact base that is laterally spaced apart from the passivation surface layer. 6

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor device with GaN layer, T-gate, and MIM capacitor

top capacitor plate layertop capacitor plate layer

conformal passivation layerpassivation layer on gate sidewalls and capacitor plate top surface

bottom capacitor plate layer (patterned metal, electrically isolated)bottom capacitor plate layer (patterned metal, electrically isolated)

conductive gate electrode (T-gate with contact base and sidewall extensions)conductive gate electrode (T-gate with contact base and sidewall extensions)

passivation surface layerpassivation surface layer

Materials

Materials described outside the worked examples.

gallium nitride

GaN

Semiconductor Channel/Surface Layer

Buffer Layer In Substrate Stack

passivation surface layer

Why these are connected

Related documents with shared materials, methods, properties, or citations.

HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES | Matter42 Literature