Patent
US 10,347,544Co-Planar P-Channel and N-Channel Gallium Nitride-Based Transistors on Silicon and Techniques for Forming Same
SANSAPTAK DASGUPTA
US
Copyright © 2026 Matter42. All rights reserved.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a semiconductor substrate; an n-type transistor at least one of over and in the semiconductor substrate and comprising: a first buffer layer disposed over the semiconductor substrate; a first I II -N semiconductor layer disposed over the first buffer layer; and a first polarization layer disposed over the first I II -N semiconductor layer; and a p-type transistor at least one of over and in the semiconductor substrate, adjacent to the n-type transistor, and comprising: a second buffer layer disposed over the semiconductor substrate; a second I II -N semiconductor layer disposed over the second buffer layer; a second polarization layer disposed over the second I II -N semiconductor layer, wherein at least a portion of the second polarization layer is co-planar with at least a portion of the first polarization layer; and a third I II -N semiconductor layer disposed over the second polarization layer.
The integrated circuit of claim 1, wherein at least one of: the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>; and the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (G aN) and indium gallium nitride (InGaN).
The integrated circuit of claim 1 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer; S/D contacts disposed over the n-type S/D portions and comprising at least one of titanium (Ti), aluminum (Al), and tungsten (W); p-type S/D portions extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions and comprising at least one of nickel (Ni), gold (Au), and platinum (Pt).
The integrated circuit of any of claims 1-4 further comprising: a first gate stack disposed over the first I II -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
An integrated circuit comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 6, wherein the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The integrated circuit of claim 6 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 6, wherein the p-type S/D portions extend from either m-plane or a-plane sidewalls of the third I II -N semiconductor layer.
The integrated circuit of claim 6 further comprising: a first gate stack disposed over the first Ill -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II-N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The integrated circuit of claim 6, wherein the first and second buffer layers together constitute a single, unitary layer that is conformal to the first and second features and the portion of the semiconductor substrate that separates the first and second features.
The integrated circuit of any of claims 6-13, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The integrated circuit of any of claims 6-13, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor substrate; providing a dielectric layer disposed over the semiconductor substrate; providing first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; providing an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and providing a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The method of claim 16, wherein the first, second, and third I II -N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The method of claim 16 further comprising: providing n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; providing S/D contacts disposed over the n-type S/D portions; providing p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and providing S/D contacts disposed over the p-type S/D portions.
The method of claim 16 further comprising: providing a first gate stack disposed over the first I II -N semiconductor layer; and providing a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The method of any of claims 16-22, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The method of any of claims 16-22, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
An integrated circuit comprising: a silicon (Si) substrate; a dielectric layer disposed over the Si substrate; first and second recessed trenches disposed in the Si substrate, under corresponding first and second openings disposed in the dielectric layer, wherein the first and second recessed trenches are separated from one another by a prominence extending from the Si substrate; first and second buffer layers disposed on the semiconductor substrate, within the first and second recessed trenches, respectively; first and second gallium nitride (GaN) or indium gallium nitride (InGaN) layers disposed on the first and second buffer layers, respectively, within the first and second recessed trenches, respectively; first and second aluminum gallium nitride (AlGaN) or indium aluminum nitride (InA lN) layers disposed over the first and second GaN or InGaN layers, respectively, within the first and second recessed trenches, respectively, and extending through the first and second openings, respectively, of the dielectric layer such that at least a portion of each of the first and second AlGaN or MAI N layers is co-planar with an upper surface of the dielectric layer; and a third GaN or InGaN layer disposed over the at least a portion of the second AlGaN or InAl N layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 25 further comprising: n-type source/drain (S/D) portions disposed over the first GaN or InGaN layer and extending through the first AlGaN or InAl N layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third GaN or InGaN layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 25 further comprising: a first aluminum nitride (A l N) layer disposed between the first GaN or InGaN layer and the first AlGaN or InAl N layer; and a second A l N layer disposed between the second GaN or InGaN layer and the second A l GaN or InAl N layer.
The integrated circuit of claim 25, wherein the prominence extending from the Si substrate at least one of: is oxidized; and has a sidewall portion that is not perpendicular with respect to a bottom surface of at least one of the first and second recessed trenches.
Layer stacks claimed or described, ordered top of device to substrate.
n-type III-N transistor (claim 1 embodiment)
p-type III-N transistor (claim 1 embodiment)
n-channel III-N transistor in recessed feature with dielectric
p-channel III-N transistor in recessed feature with dielectric
co-planar GaN/InGaN n- and p-channel transistors on Si with AlGaN/InAlN polarization (claim 25)
Materials described outside the worked examples.
III-N semiconductor (first/second/third layers)
buffer layer
polarization layer
silicon substrate <111>
Si
gallium nitride
GaN
indium gallium nitride
InGaN
titanium
Ti
aluminum
Al
tungsten
W
nickel
Ni
gold
Au
platinum
Pt
silicon carbide
SiC
magnesium dopant
Mg
dielectric layer
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 2–3 um | — |
Thickness | 10–30 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 5–15 nm | — |
Thickness | 5–25 nm | — |
Thickness | 50–75 nm | — |
Thickness | 75–100 nm | — |
Thickness | 50–70 nm | — |
Thickness | 50–60 nm | — |
Thickness | 60–70 nm | — |
Thickness | 50–200 nm | — |
Thickness | 50–125 nm | — |
Thickness | 125–200 nm | — |
Thickness | 50–300 nm | — |
Thickness | 1–5 nm | — |
Thickness | 1–2.5 nm | — |
Thickness | 5–5 nm | — |
Thickness | 0–30 nm | — |
Thickness | 0–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
ENHANCEMENT MODE NORMALLY-OFF GALLIUM NITRIDE HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
Gallium Nitride Device with Field Plate Structure and Method of Manufacturing the Same
PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS
HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES
PHOTOCONDUCTIVE SEMICONDUCTOR SWITCH LATERALLY FABRICATED ALONGSIDE GaN ON Si FIELD-EFFECT TRANSISTORS
AlN BUFFER N-POLAR GaN HEMT PROFILE
GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING A GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE
Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a semiconductor substrate; an n-type transistor at least one of over and in the semiconductor substrate and comprising: a first buffer layer disposed over the semiconductor substrate; a first I II -N semiconductor layer disposed over the first buffer layer; and a first polarization layer disposed over the first I II -N semiconductor layer; and a p-type transistor at least one of over and in the semiconductor substrate, adjacent to the n-type transistor, and comprising: a second buffer layer disposed over the semiconductor substrate; a second I II -N semiconductor layer disposed over the second buffer layer; a second polarization layer disposed over the second I II -N semiconductor layer, wherein at least a portion of the second polarization layer is co-planar with at least a portion of the first polarization layer; and a third I II -N semiconductor layer disposed over the second polarization layer.
The integrated circuit of claim 1, wherein at least one of: the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>; and the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (G aN) and indium gallium nitride (InGaN).
The integrated circuit of claim 1 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer; S/D contacts disposed over the n-type S/D portions and comprising at least one of titanium (Ti), aluminum (Al), and tungsten (W); p-type S/D portions extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions and comprising at least one of nickel (Ni), gold (Au), and platinum (Pt).
The integrated circuit of any of claims 1-4 further comprising: a first gate stack disposed over the first I II -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
An integrated circuit comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 6, wherein the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The integrated circuit of claim 6 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 6, wherein the p-type S/D portions extend from either m-plane or a-plane sidewalls of the third I II -N semiconductor layer.
The integrated circuit of claim 6 further comprising: a first gate stack disposed over the first Ill -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II-N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The integrated circuit of claim 6, wherein the first and second buffer layers together constitute a single, unitary layer that is conformal to the first and second features and the portion of the semiconductor substrate that separates the first and second features.
The integrated circuit of any of claims 6-13, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The integrated circuit of any of claims 6-13, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor substrate; providing a dielectric layer disposed over the semiconductor substrate; providing first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; providing an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and providing a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The method of claim 16, wherein the first, second, and third I II -N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The method of claim 16 further comprising: providing n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; providing S/D contacts disposed over the n-type S/D portions; providing p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and providing S/D contacts disposed over the p-type S/D portions.
The method of claim 16 further comprising: providing a first gate stack disposed over the first I II -N semiconductor layer; and providing a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The method of any of claims 16-22, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The method of any of claims 16-22, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
An integrated circuit comprising: a silicon (Si) substrate; a dielectric layer disposed over the Si substrate; first and second recessed trenches disposed in the Si substrate, under corresponding first and second openings disposed in the dielectric layer, wherein the first and second recessed trenches are separated from one another by a prominence extending from the Si substrate; first and second buffer layers disposed on the semiconductor substrate, within the first and second recessed trenches, respectively; first and second gallium nitride (GaN) or indium gallium nitride (InGaN) layers disposed on the first and second buffer layers, respectively, within the first and second recessed trenches, respectively; first and second aluminum gallium nitride (AlGaN) or indium aluminum nitride (InA lN) layers disposed over the first and second GaN or InGaN layers, respectively, within the first and second recessed trenches, respectively, and extending through the first and second openings, respectively, of the dielectric layer such that at least a portion of each of the first and second AlGaN or MAI N layers is co-planar with an upper surface of the dielectric layer; and a third GaN or InGaN layer disposed over the at least a portion of the second AlGaN or InAl N layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 25 further comprising: n-type source/drain (S/D) portions disposed over the first GaN or InGaN layer and extending through the first AlGaN or InAl N layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third GaN or InGaN layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 25 further comprising: a first aluminum nitride (A l N) layer disposed between the first GaN or InGaN layer and the first AlGaN or InAl N layer; and a second A l N layer disposed between the second GaN or InGaN layer and the second A l GaN or InAl N layer.
The integrated circuit of claim 25, wherein the prominence extending from the Si substrate at least one of: is oxidized; and has a sidewall portion that is not perpendicular with respect to a bottom surface of at least one of the first and second recessed trenches.
Layer stacks claimed or described, ordered top of device to substrate.
n-type III-N transistor (claim 1 embodiment)
p-type III-N transistor (claim 1 embodiment)
n-channel III-N transistor in recessed feature with dielectric
p-channel III-N transistor in recessed feature with dielectric
co-planar GaN/InGaN n- and p-channel transistors on Si with AlGaN/InAlN polarization (claim 25)
Materials described outside the worked examples.
III-N semiconductor (first/second/third layers)
buffer layer
polarization layer
silicon substrate <111>
Si
gallium nitride
GaN
indium gallium nitride
InGaN
titanium
Ti
aluminum
Al
tungsten
W
nickel
Ni
gold
Au
platinum
Pt
silicon carbide
SiC
magnesium dopant
Mg
dielectric layer
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 2–3 um | — |
Thickness | 10–30 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 5–15 nm | — |
Thickness | 5–25 nm | — |
Thickness | 50–75 nm | — |
Thickness | 75–100 nm | — |
Thickness | 50–70 nm | — |
Thickness | 50–60 nm | — |
Thickness | 60–70 nm | — |
Thickness | 50–200 nm | — |
Thickness | 50–125 nm | — |
Thickness | 125–200 nm | — |
Thickness | 50–300 nm | — |
Thickness | 1–5 nm | — |
Thickness | 1–2.5 nm | — |
Thickness | 5–5 nm | — |
Thickness | 0–30 nm | — |
Thickness | 0–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
ENHANCEMENT MODE NORMALLY-OFF GALLIUM NITRIDE HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
Gallium Nitride Device with Field Plate Structure and Method of Manufacturing the Same
PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS
HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES
PHOTOCONDUCTIVE SEMICONDUCTOR SWITCH LATERALLY FABRICATED ALONGSIDE GaN ON Si FIELD-EFFECT TRANSISTORS
AlN BUFFER N-POLAR GaN HEMT PROFILE
GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING A GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE
Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a semiconductor substrate; an n-type transistor at least one of over and in the semiconductor substrate and comprising: a first buffer layer disposed over the semiconductor substrate; a first I II -N semiconductor layer disposed over the first buffer layer; and a first polarization layer disposed over the first I II -N semiconductor layer; and a p-type transistor at least one of over and in the semiconductor substrate, adjacent to the n-type transistor, and comprising: a second buffer layer disposed over the semiconductor substrate; a second I II -N semiconductor layer disposed over the second buffer layer; a second polarization layer disposed over the second I II -N semiconductor layer, wherein at least a portion of the second polarization layer is co-planar with at least a portion of the first polarization layer; and a third I II -N semiconductor layer disposed over the second polarization layer.
The integrated circuit of claim 1, wherein at least one of: the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>; and the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (G aN) and indium gallium nitride (InGaN).
The integrated circuit of claim 1 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer; S/D contacts disposed over the n-type S/D portions and comprising at least one of titanium (Ti), aluminum (Al), and tungsten (W); p-type S/D portions extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions and comprising at least one of nickel (Ni), gold (Au), and platinum (Pt).
The integrated circuit of any of claims 1-4 further comprising: a first gate stack disposed over the first I II -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
An integrated circuit comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 6, wherein the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The integrated circuit of claim 6 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 6, wherein the p-type S/D portions extend from either m-plane or a-plane sidewalls of the third I II -N semiconductor layer.
The integrated circuit of claim 6 further comprising: a first gate stack disposed over the first Ill -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II-N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The integrated circuit of claim 6, wherein the first and second buffer layers together constitute a single, unitary layer that is conformal to the first and second features and the portion of the semiconductor substrate that separates the first and second features.
The integrated circuit of any of claims 6-13, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The integrated circuit of any of claims 6-13, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor substrate; providing a dielectric layer disposed over the semiconductor substrate; providing first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; providing an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and providing a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The method of claim 16, wherein the first, second, and third I II -N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The method of claim 16 further comprising: providing n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; providing S/D contacts disposed over the n-type S/D portions; providing p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and providing S/D contacts disposed over the p-type S/D portions.
The method of claim 16 further comprising: providing a first gate stack disposed over the first I II -N semiconductor layer; and providing a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The method of any of claims 16-22, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The method of any of claims 16-22, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
An integrated circuit comprising: a silicon (Si) substrate; a dielectric layer disposed over the Si substrate; first and second recessed trenches disposed in the Si substrate, under corresponding first and second openings disposed in the dielectric layer, wherein the first and second recessed trenches are separated from one another by a prominence extending from the Si substrate; first and second buffer layers disposed on the semiconductor substrate, within the first and second recessed trenches, respectively; first and second gallium nitride (GaN) or indium gallium nitride (InGaN) layers disposed on the first and second buffer layers, respectively, within the first and second recessed trenches, respectively; first and second aluminum gallium nitride (AlGaN) or indium aluminum nitride (InA lN) layers disposed over the first and second GaN or InGaN layers, respectively, within the first and second recessed trenches, respectively, and extending through the first and second openings, respectively, of the dielectric layer such that at least a portion of each of the first and second AlGaN or MAI N layers is co-planar with an upper surface of the dielectric layer; and a third GaN or InGaN layer disposed over the at least a portion of the second AlGaN or InAl N layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 25 further comprising: n-type source/drain (S/D) portions disposed over the first GaN or InGaN layer and extending through the first AlGaN or InAl N layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third GaN or InGaN layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 25 further comprising: a first aluminum nitride (A l N) layer disposed between the first GaN or InGaN layer and the first AlGaN or InAl N layer; and a second A l N layer disposed between the second GaN or InGaN layer and the second A l GaN or InAl N layer.
The integrated circuit of claim 25, wherein the prominence extending from the Si substrate at least one of: is oxidized; and has a sidewall portion that is not perpendicular with respect to a bottom surface of at least one of the first and second recessed trenches.
Layer stacks claimed or described, ordered top of device to substrate.
n-type III-N transistor (claim 1 embodiment)
p-type III-N transistor (claim 1 embodiment)
n-channel III-N transistor in recessed feature with dielectric
p-channel III-N transistor in recessed feature with dielectric
co-planar GaN/InGaN n- and p-channel transistors on Si with AlGaN/InAlN polarization (claim 25)
Materials described outside the worked examples.
III-N semiconductor (first/second/third layers)
buffer layer
polarization layer
silicon substrate <111>
Si
gallium nitride
GaN
indium gallium nitride
InGaN
titanium
Ti
aluminum
Al
tungsten
W
nickel
Ni
gold
Au
platinum
Pt
silicon carbide
SiC
magnesium dopant
Mg
dielectric layer
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 2–3 um | — |
Thickness | 10–30 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 5–15 nm | — |
Thickness | 5–25 nm | — |
Thickness | 50–75 nm | — |
Thickness | 75–100 nm | — |
Thickness | 50–70 nm | — |
Thickness | 50–60 nm | — |
Thickness | 60–70 nm | — |
Thickness | 50–200 nm | — |
Thickness | 50–125 nm | — |
Thickness | 125–200 nm | — |
Thickness | 50–300 nm | — |
Thickness | 1–5 nm | — |
Thickness | 1–2.5 nm | — |
Thickness | 5–5 nm | — |
Thickness | 0–30 nm | — |
Thickness | 0–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
ENHANCEMENT MODE NORMALLY-OFF GALLIUM NITRIDE HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
Gallium Nitride Device with Field Plate Structure and Method of Manufacturing the Same
PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS
HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES
PHOTOCONDUCTIVE SEMICONDUCTOR SWITCH LATERALLY FABRICATED ALONGSIDE GaN ON Si FIELD-EFFECT TRANSISTORS
AlN BUFFER N-POLAR GaN HEMT PROFILE
GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING A GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE
Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising: a semiconductor substrate; an n-type transistor at least one of over and in the semiconductor substrate and comprising: a first buffer layer disposed over the semiconductor substrate; a first I II -N semiconductor layer disposed over the first buffer layer; and a first polarization layer disposed over the first I II -N semiconductor layer; and a p-type transistor at least one of over and in the semiconductor substrate, adjacent to the n-type transistor, and comprising: a second buffer layer disposed over the semiconductor substrate; a second I II -N semiconductor layer disposed over the second buffer layer; a second polarization layer disposed over the second I II -N semiconductor layer, wherein at least a portion of the second polarization layer is co-planar with at least a portion of the first polarization layer; and a third I II -N semiconductor layer disposed over the second polarization layer.
The integrated circuit of claim 1, wherein at least one of: the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>; and the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (G aN) and indium gallium nitride (InGaN).
The integrated circuit of claim 1 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer; S/D contacts disposed over the n-type S/D portions and comprising at least one of titanium (Ti), aluminum (Al), and tungsten (W); p-type S/D portions extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions and comprising at least one of nickel (Ni), gold (Au), and platinum (Pt).
The integrated circuit of any of claims 1-4 further comprising: a first gate stack disposed over the first I II -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
An integrated circuit comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 6, wherein the first, second, and third I II-N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The integrated circuit of claim 6 further comprising: n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 6, wherein the p-type S/D portions extend from either m-plane or a-plane sidewalls of the third I II -N semiconductor layer.
The integrated circuit of claim 6 further comprising: a first gate stack disposed over the first Ill -N semiconductor layer; and a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II-N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third III -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The integrated circuit of claim 6, wherein the first and second buffer layers together constitute a single, unitary layer that is conformal to the first and second features and the portion of the semiconductor substrate that separates the first and second features.
The integrated circuit of any of claims 6-13, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The integrated circuit of any of claims 6-13, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor substrate; providing a dielectric layer disposed over the semiconductor substrate; providing first and second features disposed in the semiconductor substrate, under corresponding first and second openings disposed in the dielectric layer, wherein: the first and second openings are narrower in width than the first and second features, respectively; and the first and second features are separated by a portion of the semiconductor substrate; providing an n-channel transistor device comprising: a first buffer layer disposed over the semiconductor substrate, within the first feature; a first I II -N semiconductor layer disposed over the first buffer layer, within the first feature; and a first polarization layer disposed over the first I II -N semiconductor layer, within the first feature and extending through the first opening such that at least a portion of the first polarization layer is co-planar with an upper surface of the dielectric layer; and providing a p-channel transistor device comprising: a second buffer layer disposed over the semiconductor substrate, within the second feature; a second I II -N semiconductor layer disposed over the second buffer layer, within the second feature; a second polarization layer disposed over the second I II -N semiconductor layer, within the second feature and extending through the second opening such that at least a portion of the second polarization layer is co-planar with the upper surface of the dielectric layer; and a third I II -N semiconductor layer disposed over the at least a portion of the second polarization layer that is co-planar with the upper surface of the dielectric layer.
The method of claim 16, wherein the first, second, and third I II -N semiconductor layers each comprise at least one of gallium nitride (GaN) and indium gallium nitride (InGaN).
The method of claim 16 further comprising: providing n-type source/drain (S/D) portions disposed over the first I II -N semiconductor layer and extending through the first polarization layer and the dielectric layer; providing S/D contacts disposed over the n-type S/D portions; providing p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third I II -N semiconductor layer; and providing S/D contacts disposed over the p-type S/D portions.
The method of claim 16 further comprising: providing a first gate stack disposed over the first I II -N semiconductor layer; and providing a second gate stack disposed over the second I II -N semiconductor layer; wherein either: the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer; the first gate stack is disposed over the first polarization layer, and the second gate stack is disposed within the third I II -N semiconductor layer; or the first gate stack is disposed within the first polarization layer, and the second gate stack is disposed over the third I II -N semiconductor layer.
The method of any of claims 16-22, wherein the semiconductor substrate comprises silicon (Si) having a crystal orientation of <111>.
The method of any of claims 16-22, wherein the portion of the semiconductor substrate that separates the first and second features at least one of: is oxidized; and has a sidewall portion that is slanted with respect to a bottom surface of at least one of the first and second features.
An integrated circuit comprising: a silicon (Si) substrate; a dielectric layer disposed over the Si substrate; first and second recessed trenches disposed in the Si substrate, under corresponding first and second openings disposed in the dielectric layer, wherein the first and second recessed trenches are separated from one another by a prominence extending from the Si substrate; first and second buffer layers disposed on the semiconductor substrate, within the first and second recessed trenches, respectively; first and second gallium nitride (GaN) or indium gallium nitride (InGaN) layers disposed on the first and second buffer layers, respectively, within the first and second recessed trenches, respectively; first and second aluminum gallium nitride (AlGaN) or indium aluminum nitride (InA lN) layers disposed over the first and second GaN or InGaN layers, respectively, within the first and second recessed trenches, respectively, and extending through the first and second openings, respectively, of the dielectric layer such that at least a portion of each of the first and second AlGaN or MAI N layers is co-planar with an upper surface of the dielectric layer; and a third GaN or InGaN layer disposed over the at least a portion of the second AlGaN or InAl N layer that is co-planar with the upper surface of the dielectric layer.
The integrated circuit of claim 25 further comprising: n-type source/drain (S/D) portions disposed over the first GaN or InGaN layer and extending through the first AlGaN or InAl N layer and the dielectric layer; S/D contacts disposed over the n-type S/D portions; p-type S/D portions disposed over the dielectric layer, extending from sidewalls of the third GaN or InGaN layer; and S/D contacts disposed over the p-type S/D portions.
The integrated circuit of claim 25 further comprising: a first aluminum nitride (A l N) layer disposed between the first GaN or InGaN layer and the first AlGaN or InAl N layer; and a second A l N layer disposed between the second GaN or InGaN layer and the second A l GaN or InAl N layer.
The integrated circuit of claim 25, wherein the prominence extending from the Si substrate at least one of: is oxidized; and has a sidewall portion that is not perpendicular with respect to a bottom surface of at least one of the first and second recessed trenches.
Layer stacks claimed or described, ordered top of device to substrate.
n-type III-N transistor (claim 1 embodiment)
p-type III-N transistor (claim 1 embodiment)
n-channel III-N transistor in recessed feature with dielectric
p-channel III-N transistor in recessed feature with dielectric
co-planar GaN/InGaN n- and p-channel transistors on Si with AlGaN/InAlN polarization (claim 25)
Materials described outside the worked examples.
III-N semiconductor (first/second/third layers)
buffer layer
polarization layer
silicon substrate <111>
Si
gallium nitride
GaN
indium gallium nitride
InGaN
titanium
Ti
aluminum
Al
tungsten
W
nickel
Ni
gold
Au
platinum
Pt
silicon carbide
SiC
magnesium dopant
Mg
dielectric layer
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–150 nm | — |
Thickness | 10–100 nm | — |
Thickness | 10–50 nm | — |
Thickness | 50–100 nm | — |
Thickness | 2–3 um | — |
Thickness | 10–30 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 5–15 nm | — |
Thickness | 5–25 nm | — |
Thickness | 50–75 nm | — |
Thickness | 75–100 nm | — |
Thickness | 50–70 nm | — |
Thickness | 50–60 nm | — |
Thickness | 60–70 nm | — |
Thickness | 50–200 nm | — |
Thickness | 50–125 nm | — |
Thickness | 125–200 nm | — |
Thickness | 50–300 nm | — |
Thickness | 1–5 nm | — |
Thickness | 1–2.5 nm | — |
Thickness | 5–5 nm | — |
Thickness | 0–30 nm | — |
Thickness | 0–100 nm | — |
Related documents with shared materials, methods, properties, or citations.
ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
ENHANCEMENT MODE NORMALLY-OFF GALLIUM NITRIDE HETEROSTRUCTURE FIELD EFFECT TRANSISTOR
Gallium Nitride Device with Field Plate Structure and Method of Manufacturing the Same
PROCESS OF FABRICATING HIGH EFFICIENCY, HIGH LINEARITY N-POLAR GALLIUM-NITRIDE (GaN) TRANSISTORS
HIGH SPEED GALLIUM NITRIDE TRANSISTOR DEVICES
PHOTOCONDUCTIVE SEMICONDUCTOR SWITCH LATERALLY FABRICATED ALONGSIDE GaN ON Si FIELD-EFFECT TRANSISTORS
AlN BUFFER N-POLAR GaN HEMT PROFILE
GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MAKING A GALLIUM NITRIDE/ ALUMINUM GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE
Preparation Method of GaN Field Effect Transistor Based on Diamond Substrate