Patent
Atlas literature
Patent
US 12,112,944 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
FIG. 40 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3 and a barrier layer 5. In other possible embodiments, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method of a gallium nitride (GaN) field effect transistor, comprising following steps: step 1, preparing a GaN heterojunction layer on a front-side of a silicon carbide (SiC) substrate; step 2, thinning a backside of the SiC substrate to obtain a thinned SiC substrate; step 3, growing a sacrificial layer on a backside of the thinned SiC substrate; step 4, coating a photoresist on the sacrificial layer; step 5, exposing and developing the photoresist to form a metal mask area graphics on the sacrificial layer; step 6, evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer on the metal mask area graphics; step 7, removing a part of the sacrificial layer that is outside an area covered by the metal mask layer to form a groove area on the sacrificial layer and to obtain a remaining sacrificial layer; step 8, removing the metal mask layer using a wet process; step 9, using the remaining sacrificial layer as a mask, and etching the thinned SiC substrate such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate; step 10, growing a diamond layer on the remaining sacrificial layer and the backside of the GaN heterojunction layer; step 11, removing a part of the diamond layer that covers the remaining sacrificial layer using the wet process to obtain a remaining diamond layer, and removing the remaining sacrificial layer using the wet process; step 12, preparing a source electrode, a drain electrode and a gate electrode on a front-side of the GaN het-erojunction layer; step 13, preparing a through hole mask layer on the remaining diamond layer and the remaining SiC substrate; step 14, using the through hole mask layer as a mask, and etching the remaining SiC substrate and the GaN heterojunction layer to form a source through hole that is in communication with the source electrode; and step 15, removing the through hole mask layer, and preparing a back grounding metal on the remaining diamond layer and the remaining SiC substrate, to complete preparation of the GaN field effect transistor, the back grounding metal being in communication with the source through hole.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer and a barrier layer.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer, wherein the insertion layer is an AlN layer with a thickness of 1 nm∼2 nm, and the cap layer is a GaN layer with a thickness of 2 nm∼4 nm.
The method according to claim 1, wherein in the step 2, a thickness of the SiC substrate is greater than 300 µm, and a thickness of the thinned SiC substrate is 1 µm∼100 µm.
The method according to claim 1, wherein in the step 3, the sacrificial layer is a SiO₂ layer.
The method according to claim 1, wherein in the step 10, a thickness of the diamond layer is smaller than a sum of a thicknesses of the remaining sacrificial layer and a thicknesses of the thinned SiC substrate by at least 1 µm.
The method according to claim 1, wherein in the step 13, the through hole mask layer is a SiO₂ mask layer or a metal Ni mask layer.
The method according to claim 1, wherein in the step 15, a metalized through hole and the back grounding metal are formed using magnetron sputtering or electroplating. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT on diamond substrate
Materials described outside the worked examples.
GaN heterojunction layer
silicon carbide substrate
SiC
diamond layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–1000 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,944 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
FIG. 40 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3 and a barrier layer 5. In other possible embodiments, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method of a gallium nitride (GaN) field effect transistor, comprising following steps: step 1, preparing a GaN heterojunction layer on a front-side of a silicon carbide (SiC) substrate; step 2, thinning a backside of the SiC substrate to obtain a thinned SiC substrate; step 3, growing a sacrificial layer on a backside of the thinned SiC substrate; step 4, coating a photoresist on the sacrificial layer; step 5, exposing and developing the photoresist to form a metal mask area graphics on the sacrificial layer; step 6, evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer on the metal mask area graphics; step 7, removing a part of the sacrificial layer that is outside an area covered by the metal mask layer to form a groove area on the sacrificial layer and to obtain a remaining sacrificial layer; step 8, removing the metal mask layer using a wet process; step 9, using the remaining sacrificial layer as a mask, and etching the thinned SiC substrate such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate; step 10, growing a diamond layer on the remaining sacrificial layer and the backside of the GaN heterojunction layer; step 11, removing a part of the diamond layer that covers the remaining sacrificial layer using the wet process to obtain a remaining diamond layer, and removing the remaining sacrificial layer using the wet process; step 12, preparing a source electrode, a drain electrode and a gate electrode on a front-side of the GaN het-erojunction layer; step 13, preparing a through hole mask layer on the remaining diamond layer and the remaining SiC substrate; step 14, using the through hole mask layer as a mask, and etching the remaining SiC substrate and the GaN heterojunction layer to form a source through hole that is in communication with the source electrode; and step 15, removing the through hole mask layer, and preparing a back grounding metal on the remaining diamond layer and the remaining SiC substrate, to complete preparation of the GaN field effect transistor, the back grounding metal being in communication with the source through hole.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer and a barrier layer.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer, wherein the insertion layer is an AlN layer with a thickness of 1 nm∼2 nm, and the cap layer is a GaN layer with a thickness of 2 nm∼4 nm.
The method according to claim 1, wherein in the step 2, a thickness of the SiC substrate is greater than 300 µm, and a thickness of the thinned SiC substrate is 1 µm∼100 µm.
The method according to claim 1, wherein in the step 3, the sacrificial layer is a SiO₂ layer.
The method according to claim 1, wherein in the step 10, a thickness of the diamond layer is smaller than a sum of a thicknesses of the remaining sacrificial layer and a thicknesses of the thinned SiC substrate by at least 1 µm.
The method according to claim 1, wherein in the step 13, the through hole mask layer is a SiO₂ mask layer or a metal Ni mask layer.
The method according to claim 1, wherein in the step 15, a metalized through hole and the back grounding metal are formed using magnetron sputtering or electroplating. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT on diamond substrate
Materials described outside the worked examples.
GaN heterojunction layer
silicon carbide substrate
SiC
diamond layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–1000 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,944 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
FIG. 40 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3 and a barrier layer 5. In other possible embodiments, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method of a gallium nitride (GaN) field effect transistor, comprising following steps: step 1, preparing a GaN heterojunction layer on a front-side of a silicon carbide (SiC) substrate; step 2, thinning a backside of the SiC substrate to obtain a thinned SiC substrate; step 3, growing a sacrificial layer on a backside of the thinned SiC substrate; step 4, coating a photoresist on the sacrificial layer; step 5, exposing and developing the photoresist to form a metal mask area graphics on the sacrificial layer; step 6, evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer on the metal mask area graphics; step 7, removing a part of the sacrificial layer that is outside an area covered by the metal mask layer to form a groove area on the sacrificial layer and to obtain a remaining sacrificial layer; step 8, removing the metal mask layer using a wet process; step 9, using the remaining sacrificial layer as a mask, and etching the thinned SiC substrate such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate; step 10, growing a diamond layer on the remaining sacrificial layer and the backside of the GaN heterojunction layer; step 11, removing a part of the diamond layer that covers the remaining sacrificial layer using the wet process to obtain a remaining diamond layer, and removing the remaining sacrificial layer using the wet process; step 12, preparing a source electrode, a drain electrode and a gate electrode on a front-side of the GaN het-erojunction layer; step 13, preparing a through hole mask layer on the remaining diamond layer and the remaining SiC substrate; step 14, using the through hole mask layer as a mask, and etching the remaining SiC substrate and the GaN heterojunction layer to form a source through hole that is in communication with the source electrode; and step 15, removing the through hole mask layer, and preparing a back grounding metal on the remaining diamond layer and the remaining SiC substrate, to complete preparation of the GaN field effect transistor, the back grounding metal being in communication with the source through hole.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer and a barrier layer.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer, wherein the insertion layer is an AlN layer with a thickness of 1 nm∼2 nm, and the cap layer is a GaN layer with a thickness of 2 nm∼4 nm.
The method according to claim 1, wherein in the step 2, a thickness of the SiC substrate is greater than 300 µm, and a thickness of the thinned SiC substrate is 1 µm∼100 µm.
The method according to claim 1, wherein in the step 3, the sacrificial layer is a SiO₂ layer.
The method according to claim 1, wherein in the step 10, a thickness of the diamond layer is smaller than a sum of a thicknesses of the remaining sacrificial layer and a thicknesses of the thinned SiC substrate by at least 1 µm.
The method according to claim 1, wherein in the step 13, the through hole mask layer is a SiO₂ mask layer or a metal Ni mask layer.
The method according to claim 1, wherein in the step 15, a metalized through hole and the back grounding metal are formed using magnetron sputtering or electroplating. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT on diamond substrate
Materials described outside the worked examples.
GaN heterojunction layer
silicon carbide substrate
SiC
diamond layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–1000 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,112,944 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
FIG. 40 1(a), in the step 1, the GaN heterojunction layer includes a buffer layer 2, a channel layer 3 and a barrier layer 5. In other possible embodiments, …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method of a gallium nitride (GaN) field effect transistor, comprising following steps: step 1, preparing a GaN heterojunction layer on a front-side of a silicon carbide (SiC) substrate; step 2, thinning a backside of the SiC substrate to obtain a thinned SiC substrate; step 3, growing a sacrificial layer on a backside of the thinned SiC substrate; step 4, coating a photoresist on the sacrificial layer; step 5, exposing and developing the photoresist to form a metal mask area graphics on the sacrificial layer; step 6, evaporating and stripping a metal on the metal mask area graphics to form a metal mask layer on the metal mask area graphics; step 7, removing a part of the sacrificial layer that is outside an area covered by the metal mask layer to form a groove area on the sacrificial layer and to obtain a remaining sacrificial layer; step 8, removing the metal mask layer using a wet process; step 9, using the remaining sacrificial layer as a mask, and etching the thinned SiC substrate such that the groove area extends to a backside of the GaN heterojunction layer and to obtain a remaining SiC substrate; step 10, growing a diamond layer on the remaining sacrificial layer and the backside of the GaN heterojunction layer; step 11, removing a part of the diamond layer that covers the remaining sacrificial layer using the wet process to obtain a remaining diamond layer, and removing the remaining sacrificial layer using the wet process; step 12, preparing a source electrode, a drain electrode and a gate electrode on a front-side of the GaN het-erojunction layer; step 13, preparing a through hole mask layer on the remaining diamond layer and the remaining SiC substrate; step 14, using the through hole mask layer as a mask, and etching the remaining SiC substrate and the GaN heterojunction layer to form a source through hole that is in communication with the source electrode; and step 15, removing the through hole mask layer, and preparing a back grounding metal on the remaining diamond layer and the remaining SiC substrate, to complete preparation of the GaN field effect transistor, the back grounding metal being in communication with the source through hole.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer and a barrier layer.
The method according to claim 1, wherein in the step 1, the GaN heterojunction layer comprises a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer, wherein the insertion layer is an AlN layer with a thickness of 1 nm∼2 nm, and the cap layer is a GaN layer with a thickness of 2 nm∼4 nm.
The method according to claim 1, wherein in the step 2, a thickness of the SiC substrate is greater than 300 µm, and a thickness of the thinned SiC substrate is 1 µm∼100 µm.
The method according to claim 1, wherein in the step 3, the sacrificial layer is a SiO₂ layer.
The method according to claim 1, wherein in the step 10, a thickness of the diamond layer is smaller than a sum of a thicknesses of the remaining sacrificial layer and a thicknesses of the thinned SiC substrate by at least 1 µm.
The method according to claim 1, wherein in the step 13, the through hole mask layer is a SiO₂ mask layer or a metal Ni mask layer.
The method according to claim 1, wherein in the step 15, a metalized through hole and the back grounding metal are formed using magnetron sputtering or electroplating. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT on diamond substrate
Materials described outside the worked examples.
GaN heterojunction layer
silicon carbide substrate
SiC
diamond layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a schematic structural diagram of a preparation 45 method of GaN field effect transistor based on diamond substrate according to an embodiment of the …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–1000 um | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Related documents with shared materials, methods, properties, or citations.
back grounding metal
AlxGaN barrier layer
AlxGaN
InxAlN barrier layer
InxAlN
InxAlyGaN barrier layer
InxAlyGaN
AlN buffer layer
AlN
GaN channel layer
GaN
SiO₂
Ni metal mask layer
Ni
| ≥ 300 µm |
| — |
Thickness | ≥ 1 µm | — |
back grounding metal
AlxGaN barrier layer
AlxGaN
InxAlN barrier layer
InxAlN
InxAlyGaN barrier layer
InxAlyGaN
AlN buffer layer
AlN
GaN channel layer
GaN
SiO₂
Ni metal mask layer
Ni
| ≥ 300 µm |
| — |
Thickness | ≥ 1 µm | — |
back grounding metal
AlxGaN barrier layer
AlxGaN
InxAlN barrier layer
InxAlN
InxAlyGaN barrier layer
InxAlyGaN
AlN buffer layer
AlN
GaN channel layer
GaN
SiO₂
Ni metal mask layer
Ni
| ≥ 300 µm |
| — |
Thickness | ≥ 1 µm | — |
back grounding metal
AlxGaN barrier layer
AlxGaN
InxAlN barrier layer
InxAlN
InxAlyGaN barrier layer
InxAlyGaN
AlN buffer layer
AlN
GaN channel layer
GaN
SiO₂
Ni metal mask layer
Ni
| ≥ 300 µm |
| — |
Thickness | ≥ 1 µm | — |
