Patent
US 8,772,832GaN HEMTs with a Back Gate Connected to the Source
Karim S Boutros
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,772,832Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1: Structure of prior art FETs.
Figure 2: Side view of the device illustrating an embodiment of the principles of the invention.
Figure 3A: Side view of the device illustrating an embodiment of the principles of the invention. 15
Figure 3 B: Top section A-A view of the device in figure 3A.
Figure 4: Method of fabrication of a GaN HEMT with a Back Gate.
Figure 5: Alternative method of fabrication of GaN HEMT with a Back Gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEM T device comprising: a substrate, a buffer layer, a channel layer, and a barrier layer; a source, a gate s and a drain disposed on the barrier layer; a void in the buffer layer and substrate below an active region between the gate and the drain; a back gate metal layer disposed on an underside of the substrate; the source is electrically connected to the back gate metal layer; a conductive plating on the surfaces of the substrate and buffer la y er exposed b y the void below the active region between the g ate and drain.
The device of claim 1 f u rther comprising a nucleation layer between the substrate and the buffer layer; the nucleation layer comprising a void in the active region between the gate and the drain.
The device of claim 1 wherein the channel layer comprises a combination of a Group III and a Group V material
The device of claim 1 f u rther comprising an insulating cap layer.
canceled
The device of claim [[3]] 1 wherein the conductive plating comprises metal.
The device of claim [[3]] 1 wherein the conductive plating is electrically connected to the back gate metal layer.
A method of forming a HEM T device comprising: receiving a substrate with a buffer layer, a channel layer, a barrier layer formed on a top side of the substrate thereon; forming a source, a drain and a gate on the barrier layer; etching the underside of the substrate through the buffer layer to form a void in a region between the gate and the drain; forming a back g ate metal la v er on the underside of the substrate, on an underside of the channel la y er and on edges of the nucleation la y er and buffer la y er exposed by the formation of the void in the region between the g ate and drain.
The method of claim 9 wherein the device further comprises a nucleation layer between the substrate and the buffer layer and wherein the void extends through the nucleation layer.
The method of claim 9 wherein the channel layer comprises GaN.
canceled
The method of claim [[11]] 9 further comprising forming a source field plate on the HEM T device connected to the source and connected to the back gate metal layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with back gate connected to source
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1: Structure of prior art FETs.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–50 nm | — |
Duration | 1–100 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,772,832Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1: Structure of prior art FETs.
Figure 2: Side view of the device illustrating an embodiment of the principles of the invention.
Figure 3A: Side view of the device illustrating an embodiment of the principles of the invention. 15
Figure 3 B: Top section A-A view of the device in figure 3A.
Figure 4: Method of fabrication of a GaN HEMT with a Back Gate.
Figure 5: Alternative method of fabrication of GaN HEMT with a Back Gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEM T device comprising: a substrate, a buffer layer, a channel layer, and a barrier layer; a source, a gate s and a drain disposed on the barrier layer; a void in the buffer layer and substrate below an active region between the gate and the drain; a back gate metal layer disposed on an underside of the substrate; the source is electrically connected to the back gate metal layer; a conductive plating on the surfaces of the substrate and buffer la y er exposed b y the void below the active region between the g ate and drain.
The device of claim 1 f u rther comprising a nucleation layer between the substrate and the buffer layer; the nucleation layer comprising a void in the active region between the gate and the drain.
The device of claim 1 wherein the channel layer comprises a combination of a Group III and a Group V material
The device of claim 1 f u rther comprising an insulating cap layer.
canceled
The device of claim [[3]] 1 wherein the conductive plating comprises metal.
The device of claim [[3]] 1 wherein the conductive plating is electrically connected to the back gate metal layer.
A method of forming a HEM T device comprising: receiving a substrate with a buffer layer, a channel layer, a barrier layer formed on a top side of the substrate thereon; forming a source, a drain and a gate on the barrier layer; etching the underside of the substrate through the buffer layer to form a void in a region between the gate and the drain; forming a back g ate metal la v er on the underside of the substrate, on an underside of the channel la y er and on edges of the nucleation la y er and buffer la y er exposed by the formation of the void in the region between the g ate and drain.
The method of claim 9 wherein the device further comprises a nucleation layer between the substrate and the buffer layer and wherein the void extends through the nucleation layer.
The method of claim 9 wherein the channel layer comprises GaN.
canceled
The method of claim [[11]] 9 further comprising forming a source field plate on the HEM T device connected to the source and connected to the back gate metal layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with back gate connected to source
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1: Structure of prior art FETs.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–50 nm | — |
Duration | 1–100 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,772,832Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1: Structure of prior art FETs.
Figure 2: Side view of the device illustrating an embodiment of the principles of the invention.
Figure 3A: Side view of the device illustrating an embodiment of the principles of the invention. 15
Figure 3 B: Top section A-A view of the device in figure 3A.
Figure 4: Method of fabrication of a GaN HEMT with a Back Gate.
Figure 5: Alternative method of fabrication of GaN HEMT with a Back Gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEM T device comprising: a substrate, a buffer layer, a channel layer, and a barrier layer; a source, a gate s and a drain disposed on the barrier layer; a void in the buffer layer and substrate below an active region between the gate and the drain; a back gate metal layer disposed on an underside of the substrate; the source is electrically connected to the back gate metal layer; a conductive plating on the surfaces of the substrate and buffer la y er exposed b y the void below the active region between the g ate and drain.
The device of claim 1 f u rther comprising a nucleation layer between the substrate and the buffer layer; the nucleation layer comprising a void in the active region between the gate and the drain.
The device of claim 1 wherein the channel layer comprises a combination of a Group III and a Group V material
The device of claim 1 f u rther comprising an insulating cap layer.
canceled
The device of claim [[3]] 1 wherein the conductive plating comprises metal.
The device of claim [[3]] 1 wherein the conductive plating is electrically connected to the back gate metal layer.
A method of forming a HEM T device comprising: receiving a substrate with a buffer layer, a channel layer, a barrier layer formed on a top side of the substrate thereon; forming a source, a drain and a gate on the barrier layer; etching the underside of the substrate through the buffer layer to form a void in a region between the gate and the drain; forming a back g ate metal la v er on the underside of the substrate, on an underside of the channel la y er and on edges of the nucleation la y er and buffer la y er exposed by the formation of the void in the region between the g ate and drain.
The method of claim 9 wherein the device further comprises a nucleation layer between the substrate and the buffer layer and wherein the void extends through the nucleation layer.
The method of claim 9 wherein the channel layer comprises GaN.
canceled
The method of claim [[11]] 9 further comprising forming a source field plate on the HEM T device connected to the source and connected to the back gate metal layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with back gate connected to source
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1: Structure of prior art FETs.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–50 nm | — |
Duration | 1–100 minutes |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,772,832Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1: Structure of prior art FETs.
Figure 2: Side view of the device illustrating an embodiment of the principles of the invention.
Figure 3A: Side view of the device illustrating an embodiment of the principles of the invention. 15
Figure 3 B: Top section A-A view of the device in figure 3A.
Figure 4: Method of fabrication of a GaN HEMT with a Back Gate.
Figure 5: Alternative method of fabrication of GaN HEMT with a Back Gate.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A HEM T device comprising: a substrate, a buffer layer, a channel layer, and a barrier layer; a source, a gate s and a drain disposed on the barrier layer; a void in the buffer layer and substrate below an active region between the gate and the drain; a back gate metal layer disposed on an underside of the substrate; the source is electrically connected to the back gate metal layer; a conductive plating on the surfaces of the substrate and buffer la y er exposed b y the void below the active region between the g ate and drain.
The device of claim 1 f u rther comprising a nucleation layer between the substrate and the buffer layer; the nucleation layer comprising a void in the active region between the gate and the drain.
The device of claim 1 wherein the channel layer comprises a combination of a Group III and a Group V material
The device of claim 1 f u rther comprising an insulating cap layer.
canceled
The device of claim [[3]] 1 wherein the conductive plating comprises metal.
The device of claim [[3]] 1 wherein the conductive plating is electrically connected to the back gate metal layer.
A method of forming a HEM T device comprising: receiving a substrate with a buffer layer, a channel layer, a barrier layer formed on a top side of the substrate thereon; forming a source, a drain and a gate on the barrier layer; etching the underside of the substrate through the buffer layer to form a void in a region between the gate and the drain; forming a back g ate metal la v er on the underside of the substrate, on an underside of the channel la y er and on edges of the nucleation la y er and buffer la y er exposed by the formation of the void in the region between the g ate and drain.
The method of claim 9 wherein the device further comprises a nucleation layer between the substrate and the buffer layer and wherein the void extends through the nucleation layer.
The method of claim 9 wherein the channel layer comprises GaN.
canceled
The method of claim [[11]] 9 further comprising forming a source field plate on the HEM T device connected to the source and connected to the back gate metal layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with back gate connected to source
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1: Structure of prior art FETs.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 10–50 nm | — |
Duration | 1–100 minutes |
Related documents with shared materials, methods, properties, or citations.
buffer layer
barrier layer
nucleation layer
conductive metal plating
Group III-Group V material
insulating cap layer
AlN or AlGaN nucleation layer
AlxGa₁-xN buffer/nucleation layer
AlxGa(1-x)N
| — |
buffer layer
barrier layer
nucleation layer
conductive metal plating
Group III-Group V material
insulating cap layer
AlN or AlGaN nucleation layer
AlxGa₁-xN buffer/nucleation layer
AlxGa(1-x)N
| — |
buffer layer
barrier layer
nucleation layer
conductive metal plating
Group III-Group V material
insulating cap layer
AlN or AlGaN nucleation layer
AlxGa₁-xN buffer/nucleation layer
AlxGa(1-x)N
| — |
buffer layer
barrier layer
nucleation layer
conductive metal plating
Group III-Group V material
insulating cap layer
AlN or AlGaN nucleation layer
AlxGa₁-xN buffer/nucleation layer
AlxGa(1-x)N
| — |