Patent
US 10,062,775GaN-based power electronic device and method for manufacturing the same
Sen HUANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,062,775Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 b are schematic diagrams of two GaN-based power electronic device structures according to embodiments of the present disclosure. [0027]
FIG. 2b are schematic diagrams for dry etching a P-type A I(I n,Ga)N layer in a region excluding the gate as shown in
FIG. 3 shows comparison of band diagrams for si t uations before and aft er the AI (In, Ga) N/InGaN superlattice layer is inserted betw e n the P-type A …
FIG. 4b are schematic diagrams of illumination and propagation in the below- gate A I(In, Ga)N/I nGaN superlattice inserting layer when the gate is forward …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based power electronic device comprising a substrate and an epitaxial layer disposed on the substrate, wherein: the epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, a gate, a source, a drain and a passivation la y er are disposed on the epitaxial layer; the superlattice structure layer is inserted between the GaN-based heterostructure layer [[,]] and the P-type cap layer so as to enhance the barrier height of the gate of the GaN-based power electronic device and to suppress the current collapse induced by traps inside and on the surface of the heterostructure, wherein Al(I n, Ga) N thickness and InGaN thickness in a single period of the Al(I n, Ga)N/I nGaN superlattice structure are respectively in a range of 1-4 nm, and the P-type cap la y er between the gate and the source and between the gate and the drain is removed by using the superlattice structure layer as a stopping la y er. Currently amended
The GaN-based power electronic device according to claim 1, wherein the superlattice structure layer is a I N/GaN superlattice structure, a Al(I n,Ga)N/I nGaN superlattice structure, a I N/GaN/A I N quantum well structure or a Al(I n,Ga)N/I nGaN/Al(I n, Ga)N quantum well structure. Original
The GaN-based power electronic device according to claim 1, wherein the heterostructure layer comprises a buffer layer and a barrier layer disposed on the buffer layer, and the buffer layer is a GaN buffer layer, the barrier layer is a Al(I n,Ga)N barrier layer. Currently amended
The GaN-based power electronic device according to claim 1, wherein the P-type cap layer is a binary alloy layer of P-GaN, P-InN or P-A I N, or a ternary alloy layer of P-A l GaN, P-A lI nN or P-I nGaN, or a quaternary alloy layer of P-A lI nGaN. Original
Canceled
A method for manufacturing a GaN-based power electronic device comprising steps o f: (1) preparing a substrate; (2) forming, on the substrate, a epitaxial layer comprising a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, the superlattice structure layer is disposed on the heterostructure layer, and the P-type cap layer is disposed on the superlattice structure layer [[;]] and (3) forming a gate, a source, a drain and a passivation layer on the epitaxial layer, wherein the P-type cap la y er between the g ate and the source and between the gate and the drain is removed by using a dry etching approach with the superlattice structure layer as a stopping layer. Currently amended
The method according to claim 7, wherein the superlattice structure layer is provided between the gate and the source and between the gate and the drain, or the superlattice structure layer is not provided between the gate and the source and between the gate and the drain. Original
The method according to claim 7, wherein the gate of the device is a Schottky contact or an Ohmic contact. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based power electronic device (enhancement-mode HEMT)
Materials described outside the worked examples.
GaN
P-type cap layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,062,775Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 b are schematic diagrams of two GaN-based power electronic device structures according to embodiments of the present disclosure. [0027]
FIG. 2b are schematic diagrams for dry etching a P-type A I(I n,Ga)N layer in a region excluding the gate as shown in
FIG. 3 shows comparison of band diagrams for si t uations before and aft er the AI (In, Ga) N/InGaN superlattice layer is inserted betw e n the P-type A …
FIG. 4b are schematic diagrams of illumination and propagation in the below- gate A I(In, Ga)N/I nGaN superlattice inserting layer when the gate is forward …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based power electronic device comprising a substrate and an epitaxial layer disposed on the substrate, wherein: the epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, a gate, a source, a drain and a passivation la y er are disposed on the epitaxial layer; the superlattice structure layer is inserted between the GaN-based heterostructure layer [[,]] and the P-type cap layer so as to enhance the barrier height of the gate of the GaN-based power electronic device and to suppress the current collapse induced by traps inside and on the surface of the heterostructure, wherein Al(I n, Ga) N thickness and InGaN thickness in a single period of the Al(I n, Ga)N/I nGaN superlattice structure are respectively in a range of 1-4 nm, and the P-type cap la y er between the gate and the source and between the gate and the drain is removed by using the superlattice structure layer as a stopping la y er. Currently amended
The GaN-based power electronic device according to claim 1, wherein the superlattice structure layer is a I N/GaN superlattice structure, a Al(I n,Ga)N/I nGaN superlattice structure, a I N/GaN/A I N quantum well structure or a Al(I n,Ga)N/I nGaN/Al(I n, Ga)N quantum well structure. Original
The GaN-based power electronic device according to claim 1, wherein the heterostructure layer comprises a buffer layer and a barrier layer disposed on the buffer layer, and the buffer layer is a GaN buffer layer, the barrier layer is a Al(I n,Ga)N barrier layer. Currently amended
The GaN-based power electronic device according to claim 1, wherein the P-type cap layer is a binary alloy layer of P-GaN, P-InN or P-A I N, or a ternary alloy layer of P-A l GaN, P-A lI nN or P-I nGaN, or a quaternary alloy layer of P-A lI nGaN. Original
Canceled
A method for manufacturing a GaN-based power electronic device comprising steps o f: (1) preparing a substrate; (2) forming, on the substrate, a epitaxial layer comprising a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, the superlattice structure layer is disposed on the heterostructure layer, and the P-type cap layer is disposed on the superlattice structure layer [[;]] and (3) forming a gate, a source, a drain and a passivation layer on the epitaxial layer, wherein the P-type cap la y er between the g ate and the source and between the gate and the drain is removed by using a dry etching approach with the superlattice structure layer as a stopping layer. Currently amended
The method according to claim 7, wherein the superlattice structure layer is provided between the gate and the source and between the gate and the drain, or the superlattice structure layer is not provided between the gate and the source and between the gate and the drain. Original
The method according to claim 7, wherein the gate of the device is a Schottky contact or an Ohmic contact. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based power electronic device (enhancement-mode HEMT)
Materials described outside the worked examples.
GaN
P-type cap layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,062,775Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 b are schematic diagrams of two GaN-based power electronic device structures according to embodiments of the present disclosure. [0027]
FIG. 2b are schematic diagrams for dry etching a P-type A I(I n,Ga)N layer in a region excluding the gate as shown in
FIG. 3 shows comparison of band diagrams for si t uations before and aft er the AI (In, Ga) N/InGaN superlattice layer is inserted betw e n the P-type A …
FIG. 4b are schematic diagrams of illumination and propagation in the below- gate A I(In, Ga)N/I nGaN superlattice inserting layer when the gate is forward …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based power electronic device comprising a substrate and an epitaxial layer disposed on the substrate, wherein: the epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, a gate, a source, a drain and a passivation la y er are disposed on the epitaxial layer; the superlattice structure layer is inserted between the GaN-based heterostructure layer [[,]] and the P-type cap layer so as to enhance the barrier height of the gate of the GaN-based power electronic device and to suppress the current collapse induced by traps inside and on the surface of the heterostructure, wherein Al(I n, Ga) N thickness and InGaN thickness in a single period of the Al(I n, Ga)N/I nGaN superlattice structure are respectively in a range of 1-4 nm, and the P-type cap la y er between the gate and the source and between the gate and the drain is removed by using the superlattice structure layer as a stopping la y er. Currently amended
The GaN-based power electronic device according to claim 1, wherein the superlattice structure layer is a I N/GaN superlattice structure, a Al(I n,Ga)N/I nGaN superlattice structure, a I N/GaN/A I N quantum well structure or a Al(I n,Ga)N/I nGaN/Al(I n, Ga)N quantum well structure. Original
The GaN-based power electronic device according to claim 1, wherein the heterostructure layer comprises a buffer layer and a barrier layer disposed on the buffer layer, and the buffer layer is a GaN buffer layer, the barrier layer is a Al(I n,Ga)N barrier layer. Currently amended
The GaN-based power electronic device according to claim 1, wherein the P-type cap layer is a binary alloy layer of P-GaN, P-InN or P-A I N, or a ternary alloy layer of P-A l GaN, P-A lI nN or P-I nGaN, or a quaternary alloy layer of P-A lI nGaN. Original
Canceled
A method for manufacturing a GaN-based power electronic device comprising steps o f: (1) preparing a substrate; (2) forming, on the substrate, a epitaxial layer comprising a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, the superlattice structure layer is disposed on the heterostructure layer, and the P-type cap layer is disposed on the superlattice structure layer [[;]] and (3) forming a gate, a source, a drain and a passivation layer on the epitaxial layer, wherein the P-type cap la y er between the g ate and the source and between the gate and the drain is removed by using a dry etching approach with the superlattice structure layer as a stopping layer. Currently amended
The method according to claim 7, wherein the superlattice structure layer is provided between the gate and the source and between the gate and the drain, or the superlattice structure layer is not provided between the gate and the source and between the gate and the drain. Original
The method according to claim 7, wherein the gate of the device is a Schottky contact or an Ohmic contact. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based power electronic device (enhancement-mode HEMT)
Materials described outside the worked examples.
GaN
P-type cap layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,062,775Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 b are schematic diagrams of two GaN-based power electronic device structures according to embodiments of the present disclosure. [0027]
FIG. 2b are schematic diagrams for dry etching a P-type A I(I n,Ga)N layer in a region excluding the gate as shown in
FIG. 3 shows comparison of band diagrams for si t uations before and aft er the AI (In, Ga) N/InGaN superlattice layer is inserted betw e n the P-type A …
FIG. 4b are schematic diagrams of illumination and propagation in the below- gate A I(In, Ga)N/I nGaN superlattice inserting layer when the gate is forward …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A GaN-based power electronic device comprising a substrate and an epitaxial layer disposed on the substrate, wherein: the epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, a gate, a source, a drain and a passivation la y er are disposed on the epitaxial layer; the superlattice structure layer is inserted between the GaN-based heterostructure layer [[,]] and the P-type cap layer so as to enhance the barrier height of the gate of the GaN-based power electronic device and to suppress the current collapse induced by traps inside and on the surface of the heterostructure, wherein Al(I n, Ga) N thickness and InGaN thickness in a single period of the Al(I n, Ga)N/I nGaN superlattice structure are respectively in a range of 1-4 nm, and the P-type cap la y er between the gate and the source and between the gate and the drain is removed by using the superlattice structure layer as a stopping la y er. Currently amended
The GaN-based power electronic device according to claim 1, wherein the superlattice structure layer is a I N/GaN superlattice structure, a Al(I n,Ga)N/I nGaN superlattice structure, a I N/GaN/A I N quantum well structure or a Al(I n,Ga)N/I nGaN/Al(I n, Ga)N quantum well structure. Original
The GaN-based power electronic device according to claim 1, wherein the heterostructure layer comprises a buffer layer and a barrier layer disposed on the buffer layer, and the buffer layer is a GaN buffer layer, the barrier layer is a Al(I n,Ga)N barrier layer. Currently amended
The GaN-based power electronic device according to claim 1, wherein the P-type cap layer is a binary alloy layer of P-GaN, P-InN or P-A I N, or a ternary alloy layer of P-A l GaN, P-A lI nN or P-I nGaN, or a quaternary alloy layer of P-A lI nGaN. Original
Canceled
A method for manufacturing a GaN-based power electronic device comprising steps o f: (1) preparing a substrate; (2) forming, on the substrate, a epitaxial layer comprising a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer, the superlattice structure layer is disposed on the heterostructure layer, and the P-type cap layer is disposed on the superlattice structure layer [[;]] and (3) forming a gate, a source, a drain and a passivation layer on the epitaxial layer, wherein the P-type cap la y er between the g ate and the source and between the gate and the drain is removed by using a dry etching approach with the superlattice structure layer as a stopping layer. Currently amended
The method according to claim 7, wherein the superlattice structure layer is provided between the gate and the source and between the gate and the drain, or the superlattice structure layer is not provided between the gate and the source and between the gate and the drain. Original
The method according to claim 7, wherein the gate of the device is a Schottky contact or an Ohmic contact. Original
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based power electronic device (enhancement-mode HEMT)
Materials described outside the worked examples.
GaN
P-type cap layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 3–30 nm | — |
Thickness | 1–4 nm |
Related documents with shared materials, methods, properties, or citations.
superlattice structure layer
Al(In,Ga)N/InGaN superlattice
AlN/GaN superlattice
AlN/GaN/AlN quantum well
Al(In,Ga)N/InGaN/Al(In,Ga)N quantum well
Al(In,Ga)N barrier layer
GaN-based heterostructure layer
P-GaN
P-InN
P-AlN
P-AlGaN
P-AlInN
P-InGaN
P-AlInGaN
| — |
superlattice structure layer
Al(In,Ga)N/InGaN superlattice
AlN/GaN superlattice
AlN/GaN/AlN quantum well
Al(In,Ga)N/InGaN/Al(In,Ga)N quantum well
Al(In,Ga)N barrier layer
GaN-based heterostructure layer
P-GaN
P-InN
P-AlN
P-AlGaN
P-AlInN
P-InGaN
P-AlInGaN
| — |
superlattice structure layer
Al(In,Ga)N/InGaN superlattice
AlN/GaN superlattice
AlN/GaN/AlN quantum well
Al(In,Ga)N/InGaN/Al(In,Ga)N quantum well
Al(In,Ga)N barrier layer
GaN-based heterostructure layer
P-GaN
P-InN
P-AlN
P-AlGaN
P-AlInN
P-InGaN
P-AlInGaN
| — |
superlattice structure layer
Al(In,Ga)N/InGaN superlattice
AlN/GaN superlattice
AlN/GaN/AlN quantum well
Al(In,Ga)N/InGaN/Al(In,Ga)N quantum well
Al(In,Ga)N barrier layer
GaN-based heterostructure layer
P-GaN
P-InN
P-AlN
P-AlGaN
P-AlInN
P-InGaN
P-AlInGaN
| — |