Patent
US 11,145,507METHOD OF FORMING GALLIUM NITRIDE FILM OVER SOI SUBSTRATE
Ping-Hai CHIAO
US
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Patent
Atlas literature
Patent
US 11,145,507Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a GaN film, comprising: providing a silicon-on-insulator (SO I) substrate comprising a substrate, an insulator layer on the substrate and a silicon layer on the insulator layer; patterning the silicon layer into a patterned silicon layer comprising a plurality of recessed features, each recessed feature having a sidewall, wherein a process of patterning comprises: forming a patterned mask la y er on the silicon la yer; and etching a portion of the silicon layer not covered by the patterned mask lay er using a wet etching process, wherein the wet etching process comprises applying a wet etchant comprising Na O H aqueous solution on the silicon layer, wherein a concentration of the Na O H aqueous solution ranges from about 15 wt% to about 50 wt %; epitaxially growing a plurality of GaN structures from the sidewalls, wherein the GaN structures are separated from each other; and continuously epitaxially growing the GaN structures vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer. Currently amended
The method of claim 1, wherein the Na OH aqueous solution is at a temperature from about ° C to about 80 °C. Currently amended
The method of claim 1, wherein a roughness average (Ra) of the sidewalls ranges from about 0.60 m to about 0.9 pm. Currently amended
The method of claim 1, wherein the patterned mask layer is substantially made of silicon oxide. Currently amended
The method of claim 1, wherein the GaN structures are semi-polar GaN structures. Original
The method of claim 1, wherein a crystal orientation of the silicon layer is <100>. Original
The method of claim 1, further comprising: forming semiconductor devices over the GaN layer, wherein the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.1.svg 0.38 3.82 Black and white Currently amended
The method of claim 1, wherein the sidewalls comprise silicon (111) facets. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a width of each slot ranges from about 300 nm to about 500 nm. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a pitch of the slots ranges from about 200 nm to about 300 nm. Original
The method of claim 1, wherein a thickness of the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.2.svg 0.38 4.52 Black and white Currently amended
The method of claim 1, wherein the recessed features include a shape selected from the group consisting of a square shape, a triangle shape SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.3.svg 0.38 2.32 Black and white Currently amended
2-5. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN film on SOI substrate
Materials described outside the worked examples.
GaN
NaOH aqueous solution
NaOH
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
roughness average (Ra) of sidewalls | 0.6–0.9 um | Si |
width of each slot (recessed feature) | 300–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,145,507Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a GaN film, comprising: providing a silicon-on-insulator (SO I) substrate comprising a substrate, an insulator layer on the substrate and a silicon layer on the insulator layer; patterning the silicon layer into a patterned silicon layer comprising a plurality of recessed features, each recessed feature having a sidewall, wherein a process of patterning comprises: forming a patterned mask la y er on the silicon la yer; and etching a portion of the silicon layer not covered by the patterned mask lay er using a wet etching process, wherein the wet etching process comprises applying a wet etchant comprising Na O H aqueous solution on the silicon layer, wherein a concentration of the Na O H aqueous solution ranges from about 15 wt% to about 50 wt %; epitaxially growing a plurality of GaN structures from the sidewalls, wherein the GaN structures are separated from each other; and continuously epitaxially growing the GaN structures vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer. Currently amended
The method of claim 1, wherein the Na OH aqueous solution is at a temperature from about ° C to about 80 °C. Currently amended
The method of claim 1, wherein a roughness average (Ra) of the sidewalls ranges from about 0.60 m to about 0.9 pm. Currently amended
The method of claim 1, wherein the patterned mask layer is substantially made of silicon oxide. Currently amended
The method of claim 1, wherein the GaN structures are semi-polar GaN structures. Original
The method of claim 1, wherein a crystal orientation of the silicon layer is <100>. Original
The method of claim 1, further comprising: forming semiconductor devices over the GaN layer, wherein the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.1.svg 0.38 3.82 Black and white Currently amended
The method of claim 1, wherein the sidewalls comprise silicon (111) facets. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a width of each slot ranges from about 300 nm to about 500 nm. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a pitch of the slots ranges from about 200 nm to about 300 nm. Original
The method of claim 1, wherein a thickness of the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.2.svg 0.38 4.52 Black and white Currently amended
The method of claim 1, wherein the recessed features include a shape selected from the group consisting of a square shape, a triangle shape SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.3.svg 0.38 2.32 Black and white Currently amended
2-5. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN film on SOI substrate
Materials described outside the worked examples.
GaN
NaOH aqueous solution
NaOH
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
roughness average (Ra) of sidewalls | 0.6–0.9 um | Si |
width of each slot (recessed feature) | 300–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,145,507Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a GaN film, comprising: providing a silicon-on-insulator (SO I) substrate comprising a substrate, an insulator layer on the substrate and a silicon layer on the insulator layer; patterning the silicon layer into a patterned silicon layer comprising a plurality of recessed features, each recessed feature having a sidewall, wherein a process of patterning comprises: forming a patterned mask la y er on the silicon la yer; and etching a portion of the silicon layer not covered by the patterned mask lay er using a wet etching process, wherein the wet etching process comprises applying a wet etchant comprising Na O H aqueous solution on the silicon layer, wherein a concentration of the Na O H aqueous solution ranges from about 15 wt% to about 50 wt %; epitaxially growing a plurality of GaN structures from the sidewalls, wherein the GaN structures are separated from each other; and continuously epitaxially growing the GaN structures vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer. Currently amended
The method of claim 1, wherein the Na OH aqueous solution is at a temperature from about ° C to about 80 °C. Currently amended
The method of claim 1, wherein a roughness average (Ra) of the sidewalls ranges from about 0.60 m to about 0.9 pm. Currently amended
The method of claim 1, wherein the patterned mask layer is substantially made of silicon oxide. Currently amended
The method of claim 1, wherein the GaN structures are semi-polar GaN structures. Original
The method of claim 1, wherein a crystal orientation of the silicon layer is <100>. Original
The method of claim 1, further comprising: forming semiconductor devices over the GaN layer, wherein the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.1.svg 0.38 3.82 Black and white Currently amended
The method of claim 1, wherein the sidewalls comprise silicon (111) facets. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a width of each slot ranges from about 300 nm to about 500 nm. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a pitch of the slots ranges from about 200 nm to about 300 nm. Original
The method of claim 1, wherein a thickness of the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.2.svg 0.38 4.52 Black and white Currently amended
The method of claim 1, wherein the recessed features include a shape selected from the group consisting of a square shape, a triangle shape SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.3.svg 0.38 2.32 Black and white Currently amended
2-5. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN film on SOI substrate
Materials described outside the worked examples.
GaN
NaOH aqueous solution
NaOH
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
roughness average (Ra) of sidewalls | 0.6–0.9 um | Si |
width of each slot (recessed feature) | 300–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,145,507Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a GaN film, comprising: providing a silicon-on-insulator (SO I) substrate comprising a substrate, an insulator layer on the substrate and a silicon layer on the insulator layer; patterning the silicon layer into a patterned silicon layer comprising a plurality of recessed features, each recessed feature having a sidewall, wherein a process of patterning comprises: forming a patterned mask la y er on the silicon la yer; and etching a portion of the silicon layer not covered by the patterned mask lay er using a wet etching process, wherein the wet etching process comprises applying a wet etchant comprising Na O H aqueous solution on the silicon layer, wherein a concentration of the Na O H aqueous solution ranges from about 15 wt% to about 50 wt %; epitaxially growing a plurality of GaN structures from the sidewalls, wherein the GaN structures are separated from each other; and continuously epitaxially growing the GaN structures vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer. Currently amended
The method of claim 1, wherein the Na OH aqueous solution is at a temperature from about ° C to about 80 °C. Currently amended
The method of claim 1, wherein a roughness average (Ra) of the sidewalls ranges from about 0.60 m to about 0.9 pm. Currently amended
The method of claim 1, wherein the patterned mask layer is substantially made of silicon oxide. Currently amended
The method of claim 1, wherein the GaN structures are semi-polar GaN structures. Original
The method of claim 1, wherein a crystal orientation of the silicon layer is <100>. Original
The method of claim 1, further comprising: forming semiconductor devices over the GaN layer, wherein the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.1.svg 0.38 3.82 Black and white Currently amended
The method of claim 1, wherein the sidewalls comprise silicon (111) facets. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a width of each slot ranges from about 300 nm to about 500 nm. Original
The method of claim 1, wherein the recessed features are in shape of slots, and a pitch of the slots ranges from about 200 nm to about 300 nm. Original
The method of claim 1, wherein a thickness of the SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.2.svg 0.38 4.52 Black and white Currently amended
The method of claim 1, wherein the recessed features include a shape selected from the group consisting of a square shape, a triangle shape SVG 16714810.08-12-2021.KSASYCFQLDFLYM1.CLM.3.svg 0.38 2.32 Black and white Currently amended
2-5. Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN film on SOI substrate
Materials described outside the worked examples.
GaN
NaOH aqueous solution
NaOH
silicon
Si
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
roughness average (Ra) of sidewalls | 0.6–0.9 um | Si |
width of each slot (recessed feature) | 300–500 nm |
Related documents with shared materials, methods, properties, or citations.
insulator layer
silicon oxide
SiO₂
pitch of slots (recessed features) | 200–300 nm | Si |
thickness of silicon layer | 0.3–1 um | Si |
Temperature | 40–80 °C | — |
insulator layer
silicon oxide
SiO₂
pitch of slots (recessed features) | 200–300 nm | Si |
thickness of silicon layer | 0.3–1 um | Si |
Temperature | 40–80 °C | — |
insulator layer
silicon oxide
SiO₂
pitch of slots (recessed features) | 200–300 nm | Si |
thickness of silicon layer | 0.3–1 um | Si |
Temperature | 40–80 °C | — |
insulator layer
silicon oxide
SiO₂
pitch of slots (recessed features) | 200–300 nm | Si |
thickness of silicon layer | 0.3–1 um | Si |
Temperature | 40–80 °C | — |