Patent
US 9,190,534Enhancement Mode Normally-Off Gallium Nitride Heterostructure Field Effect Transistor
Tahir HUSSAIN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,190,534Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a partially fabricated GaN HFET in accordance with the present disclosure; [0011]
FIG. 2 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0012]
FIG. 3 shows yet another partially fabricated GaN HFET in accordance with the present disclosure; [0013]
FIG. 4 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a GaN HFET in accordance with the present disclosure; and [0015]
FIG. 6 is a flow chart illustrating a method of fabricating a GaN HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the first length dimension is.2 5 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the ions comprise fluorine ions.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the gate comprises titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein: the first length dimension of the gate comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth length dimension; and wherein the implant area is under the fourth l ength dimension of the gate.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a gate area in a channel region between the source and the drain, the gate area having a first length dimension along a direction of current flow between the source and the drain; and ions i mplanted in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; wherein the implant area has a relative position within the gate area offset towards the drain. currently amended
The normally "off ' GaN heterostructure field effect transistor having a source and a drain of claim 18 wherein: the channel region comprises: a GaN channel layer; and an A l GaN Schottky layer over the GaN channel layer; and the implant region ions-are-implanted-into is in the A l GaN Schottky layer. U. S. Appln. No. 14/248,695 Page 3
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the first length dimension is.25 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the i mplanted ions comprise are implanted using-a fluorine ion s ion treatment.
The normally "off ' GaN heterostructure field effect transistor of claim 18 further comprising: gate contact metal deposited over the gate area; wherein the gate contact metal is titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein: the first length dimension of the gate area in the channel region comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth l ength dimension; and U. S. App l n. No. 14/248,695 Page 4 wherein the implant area is in the fourth length dimension of the gate area in the channel region.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a substrate; a buffer laye r on the substrate; a channel layer on the buffer layer; a charge providing layer on the channel layer; a gate between the source and the drain, the gate having a first length dimension along a direction of current flow between the source and the drain; ions in an implant area in the charge providing layer, wherein the implant area is under the gate; wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; and wherein the implant area has a relative position under the gate that is offset towards the drain.
The normally "off ' GaN heterostructure field effect transistor of claim 25 wherein: the channel comprises GaN; and the charge providing layer comprises an A l GaN Schottky layer. U. S. App l n. No. 14/248,695 Pa ge
Layer stacks claimed or described, ordered top of device to substrate.
normally-off GaN HFET (gate-area/channel-region embodiment)
Materials described outside the worked examples.
GaN
AlGaN
fluorine ions
F
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 Å | — |
Thickness | 2–25 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,190,534Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a partially fabricated GaN HFET in accordance with the present disclosure; [0011]
FIG. 2 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0012]
FIG. 3 shows yet another partially fabricated GaN HFET in accordance with the present disclosure; [0013]
FIG. 4 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a GaN HFET in accordance with the present disclosure; and [0015]
FIG. 6 is a flow chart illustrating a method of fabricating a GaN HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
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The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the first length dimension is.2 5 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the ions comprise fluorine ions.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the gate comprises titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein: the first length dimension of the gate comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth length dimension; and wherein the implant area is under the fourth l ength dimension of the gate.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a gate area in a channel region between the source and the drain, the gate area having a first length dimension along a direction of current flow between the source and the drain; and ions i mplanted in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; wherein the implant area has a relative position within the gate area offset towards the drain. currently amended
The normally "off ' GaN heterostructure field effect transistor having a source and a drain of claim 18 wherein: the channel region comprises: a GaN channel layer; and an A l GaN Schottky layer over the GaN channel layer; and the implant region ions-are-implanted-into is in the A l GaN Schottky layer. U. S. Appln. No. 14/248,695 Page 3
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the first length dimension is.25 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the i mplanted ions comprise are implanted using-a fluorine ion s ion treatment.
The normally "off ' GaN heterostructure field effect transistor of claim 18 further comprising: gate contact metal deposited over the gate area; wherein the gate contact metal is titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein: the first length dimension of the gate area in the channel region comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth l ength dimension; and U. S. App l n. No. 14/248,695 Page 4 wherein the implant area is in the fourth length dimension of the gate area in the channel region.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a substrate; a buffer laye r on the substrate; a channel layer on the buffer layer; a charge providing layer on the channel layer; a gate between the source and the drain, the gate having a first length dimension along a direction of current flow between the source and the drain; ions in an implant area in the charge providing layer, wherein the implant area is under the gate; wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; and wherein the implant area has a relative position under the gate that is offset towards the drain.
The normally "off ' GaN heterostructure field effect transistor of claim 25 wherein: the channel comprises GaN; and the charge providing layer comprises an A l GaN Schottky layer. U. S. App l n. No. 14/248,695 Pa ge
Layer stacks claimed or described, ordered top of device to substrate.
normally-off GaN HFET (gate-area/channel-region embodiment)
Materials described outside the worked examples.
GaN
AlGaN
fluorine ions
F
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 Å | — |
Thickness | 2–25 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,190,534Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a partially fabricated GaN HFET in accordance with the present disclosure; [0011]
FIG. 2 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0012]
FIG. 3 shows yet another partially fabricated GaN HFET in accordance with the present disclosure; [0013]
FIG. 4 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a GaN HFET in accordance with the present disclosure; and [0015]
FIG. 6 is a flow chart illustrating a method of fabricating a GaN HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
canceled
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the first length dimension is.2 5 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the ions comprise fluorine ions.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the gate comprises titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein: the first length dimension of the gate comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth length dimension; and wherein the implant area is under the fourth l ength dimension of the gate.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a gate area in a channel region between the source and the drain, the gate area having a first length dimension along a direction of current flow between the source and the drain; and ions i mplanted in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; wherein the implant area has a relative position within the gate area offset towards the drain. currently amended
The normally "off ' GaN heterostructure field effect transistor having a source and a drain of claim 18 wherein: the channel region comprises: a GaN channel layer; and an A l GaN Schottky layer over the GaN channel layer; and the implant region ions-are-implanted-into is in the A l GaN Schottky layer. U. S. Appln. No. 14/248,695 Page 3
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the first length dimension is.25 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the i mplanted ions comprise are implanted using-a fluorine ion s ion treatment.
The normally "off ' GaN heterostructure field effect transistor of claim 18 further comprising: gate contact metal deposited over the gate area; wherein the gate contact metal is titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein: the first length dimension of the gate area in the channel region comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth l ength dimension; and U. S. App l n. No. 14/248,695 Page 4 wherein the implant area is in the fourth length dimension of the gate area in the channel region.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a substrate; a buffer laye r on the substrate; a channel layer on the buffer layer; a charge providing layer on the channel layer; a gate between the source and the drain, the gate having a first length dimension along a direction of current flow between the source and the drain; ions in an implant area in the charge providing layer, wherein the implant area is under the gate; wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; and wherein the implant area has a relative position under the gate that is offset towards the drain.
The normally "off ' GaN heterostructure field effect transistor of claim 25 wherein: the channel comprises GaN; and the charge providing layer comprises an A l GaN Schottky layer. U. S. App l n. No. 14/248,695 Pa ge
Layer stacks claimed or described, ordered top of device to substrate.
normally-off GaN HFET (gate-area/channel-region embodiment)
Materials described outside the worked examples.
GaN
AlGaN
fluorine ions
F
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 Å | — |
Thickness | 2–25 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,190,534Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a partially fabricated GaN HFET in accordance with the present disclosure; [0011]
FIG. 2 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0012]
FIG. 3 shows yet another partially fabricated GaN HFET in accordance with the present disclosure; [0013]
FIG. 4 shows another partially fabricated GaN HFET in accordance with the present disclosure; [0014]
FIG. 5 shows a GaN HFET in accordance with the present disclosure; and [0015]
FIG. 6 is a flow chart illustrating a method of fabricating a GaN HFET in accordance with the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
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The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the first length dimension is.2 5 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the ions comprise fluorine ions.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein the gate comprises titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 2 5 wherein: the first length dimension of the gate comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth length dimension; and wherein the implant area is under the fourth l ength dimension of the gate.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a gate area in a channel region between the source and the drain, the gate area having a first length dimension along a direction of current flow between the source and the drain; and ions i mplanted in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; wherein the implant area has a relative position within the gate area offset towards the drain. currently amended
The normally "off ' GaN heterostructure field effect transistor having a source and a drain of claim 18 wherein: the channel region comprises: a GaN channel layer; and an A l GaN Schottky layer over the GaN channel layer; and the implant region ions-are-implanted-into is in the A l GaN Schottky layer. U. S. Appln. No. 14/248,695 Page 3
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the first length dimension is.25 to 2 microns in length.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein the i mplanted ions comprise are implanted using-a fluorine ion s ion treatment.
The normally "off ' GaN heterostructure field effect transistor of claim 18 further comprising: gate contact metal deposited over the gate area; wherein the gate contact metal is titanium, aluminum, nickel, platinum, or iridium, or any combination thereof.
The normally "off ' GaN heterostructure field effect transistor of claim 18 wherein: the first length dimension of the gate area in the channel region comprises a sum of a third length dimension, a fourth length dimension, and a fifth length dimension along the direction of current flow between the source and the drain; wherein the third length dimension is near the source; wherein the fifth length dimension is near the drain; wherein the fourth length dimension is between the third length dimension and the fifth length dimension; wherein the third length dimension is greater than the fifth l ength dimension; and U. S. App l n. No. 14/248,695 Page 4 wherein the implant area is in the fourth length dimension of the gate area in the channel region.
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A normally "off ' GaN heterostructure field effect transistor having a source and a drain comprising: a substrate; a buffer laye r on the substrate; a channel layer on the buffer layer; a charge providing layer on the channel layer; a gate between the source and the drain, the gate having a first length dimension along a direction of current flow between the source and the drain; ions in an implant area in the charge providing layer, wherein the implant area is under the gate; wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension; and wherein the implant area has a relative position under the gate that is offset towards the drain.
The normally "off ' GaN heterostructure field effect transistor of claim 25 wherein: the channel comprises GaN; and the charge providing layer comprises an A l GaN Schottky layer. U. S. App l n. No. 14/248,695 Pa ge
Layer stacks claimed or described, ordered top of device to substrate.
normally-off GaN HFET (gate-area/channel-region embodiment)
Materials described outside the worked examples.
GaN
AlGaN
fluorine ions
F
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 200–500 Å | — |
Thickness | 2–25 µm |
Related documents with shared materials, methods, properties, or citations.
normally-off GaN HFET (full layer-stack embodiment, claim 25)
titanium
Ti
aluminum
Al
nickel
Ni
platinum
Pt
iridium
Ir
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
silicon carbide
SiC
gold
Au
| — |
Thickness | 2–5 µm | — |
normally-off GaN HFET (full layer-stack embodiment, claim 25)
titanium
Ti
aluminum
Al
nickel
Ni
platinum
Pt
iridium
Ir
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
silicon carbide
SiC
gold
Au
| — |
Thickness | 2–5 µm | — |
normally-off GaN HFET (full layer-stack embodiment, claim 25)
titanium
Ti
aluminum
Al
nickel
Ni
platinum
Pt
iridium
Ir
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
silicon carbide
SiC
gold
Au
| — |
Thickness | 2–5 µm | — |
normally-off GaN HFET (full layer-stack embodiment, claim 25)
titanium
Ti
aluminum
Al
nickel
Ni
platinum
Pt
iridium
Ir
silicon nitride
SiN
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
silicon carbide
SiC
gold
Au
| — |
Thickness | 2–5 µm | — |