Patent
US 8,318,545METHOD OF MAKING A MOUNTED GALLIUM NITRIDE DEVICE
David F. Abdo
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,318,545Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section view of a semiconductor device 10 during a processing stage. By way of example, semiconductor device 10 may include a wafer …
FIG. 2, by processing GaN layer 16, an active layer 18 having various active devices and interconnects may be formed over GaN layer 16. This layer may be …
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
FIG. 4, a heat sink 24 having a gold layer 22, which may be plated on it, may be brought in contact with SiC substrate layer 12 having gold layer 20. The two …
FIG. 5, the pressing, heating, and scrubbing of the die with heat sink 24 will result in heat sink 24 getting attached to the singulated die resulting in a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making a mounted gallium nitride (GaN), comprising: obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer; after the step of processing the GaN layer, forming a gold layer on the silicon layer; after formin g the g old layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and attaching the device structure to a heat sink structure using the gold layer.
The method of claim 1, wherein the step of attaching is further characterized as forming a eutectic bond.
The method of claim 1, wherein the step of attaching is further characterized by the heat sink structure further characterized as having at least a layer of gold.
The method of claim 1, wherein the step of obtaining the device structure is further characterized by the SiC layer functioning as a substrate.
The method of claim 1, wherein the step of attaching is further characterized as forming a gold/silicon eutectic bond by scrubbing and applying heat and pressure between the gold layer and a layer of gold on the heat sink structure.
A mounted gallium nitride (GaN) device, comprising: a silicon layer; a silicon carbide (SiC) layer over the silicon layer; a GaN layer over the SiC layer; an active layer of active devices and interconnect over the GaN layer; a heat sink; and a eutectic bond comprising gold and silicon between the heat sink and the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the silicon layer comprises polysilicon. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 100 times thicker than the GaN layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 25 times thicker than the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is polycrystalline. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is monocrystalline. withdrawn
A method of making a mounted gallium nitride (GaN) device, comprising: -4- MT₁₁₃₄₁ZK-US obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer, after formin g the active layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and after sawin g the wafer, attaching the silicon layer of the device structure to a heat sink structure with a eutectic bond comprising gold and silicon.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 100 times thicker than the GaN layer.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 25 times thicker than the silicon layer.
The method of claim 17, wherein the step of obtaining is further characterized by the silicon layer being polysilicon.
Layer stacks claimed or described, ordered top of device to substrate.
mounted GaN device (wafer/die structure)
mounted GaN device (packaged with heat sink)
Materials described outside the worked examples.
silicon layer
Si
silicon carbide layer
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,318,545Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section view of a semiconductor device 10 during a processing stage. By way of example, semiconductor device 10 may include a wafer …
FIG. 2, by processing GaN layer 16, an active layer 18 having various active devices and interconnects may be formed over GaN layer 16. This layer may be …
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
FIG. 4, a heat sink 24 having a gold layer 22, which may be plated on it, may be brought in contact with SiC substrate layer 12 having gold layer 20. The two …
FIG. 5, the pressing, heating, and scrubbing of the die with heat sink 24 will result in heat sink 24 getting attached to the singulated die resulting in a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making a mounted gallium nitride (GaN), comprising: obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer; after the step of processing the GaN layer, forming a gold layer on the silicon layer; after formin g the g old layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and attaching the device structure to a heat sink structure using the gold layer.
The method of claim 1, wherein the step of attaching is further characterized as forming a eutectic bond.
The method of claim 1, wherein the step of attaching is further characterized by the heat sink structure further characterized as having at least a layer of gold.
The method of claim 1, wherein the step of obtaining the device structure is further characterized by the SiC layer functioning as a substrate.
The method of claim 1, wherein the step of attaching is further characterized as forming a gold/silicon eutectic bond by scrubbing and applying heat and pressure between the gold layer and a layer of gold on the heat sink structure.
A mounted gallium nitride (GaN) device, comprising: a silicon layer; a silicon carbide (SiC) layer over the silicon layer; a GaN layer over the SiC layer; an active layer of active devices and interconnect over the GaN layer; a heat sink; and a eutectic bond comprising gold and silicon between the heat sink and the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the silicon layer comprises polysilicon. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 100 times thicker than the GaN layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 25 times thicker than the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is polycrystalline. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is monocrystalline. withdrawn
A method of making a mounted gallium nitride (GaN) device, comprising: -4- MT₁₁₃₄₁ZK-US obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer, after formin g the active layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and after sawin g the wafer, attaching the silicon layer of the device structure to a heat sink structure with a eutectic bond comprising gold and silicon.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 100 times thicker than the GaN layer.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 25 times thicker than the silicon layer.
The method of claim 17, wherein the step of obtaining is further characterized by the silicon layer being polysilicon.
Layer stacks claimed or described, ordered top of device to substrate.
mounted GaN device (wafer/die structure)
mounted GaN device (packaged with heat sink)
Materials described outside the worked examples.
silicon layer
Si
silicon carbide layer
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,318,545Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section view of a semiconductor device 10 during a processing stage. By way of example, semiconductor device 10 may include a wafer …
FIG. 2, by processing GaN layer 16, an active layer 18 having various active devices and interconnects may be formed over GaN layer 16. This layer may be …
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
FIG. 4, a heat sink 24 having a gold layer 22, which may be plated on it, may be brought in contact with SiC substrate layer 12 having gold layer 20. The two …
FIG. 5, the pressing, heating, and scrubbing of the die with heat sink 24 will result in heat sink 24 getting attached to the singulated die resulting in a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making a mounted gallium nitride (GaN), comprising: obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer; after the step of processing the GaN layer, forming a gold layer on the silicon layer; after formin g the g old layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and attaching the device structure to a heat sink structure using the gold layer.
The method of claim 1, wherein the step of attaching is further characterized as forming a eutectic bond.
The method of claim 1, wherein the step of attaching is further characterized by the heat sink structure further characterized as having at least a layer of gold.
The method of claim 1, wherein the step of obtaining the device structure is further characterized by the SiC layer functioning as a substrate.
The method of claim 1, wherein the step of attaching is further characterized as forming a gold/silicon eutectic bond by scrubbing and applying heat and pressure between the gold layer and a layer of gold on the heat sink structure.
A mounted gallium nitride (GaN) device, comprising: a silicon layer; a silicon carbide (SiC) layer over the silicon layer; a GaN layer over the SiC layer; an active layer of active devices and interconnect over the GaN layer; a heat sink; and a eutectic bond comprising gold and silicon between the heat sink and the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the silicon layer comprises polysilicon. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 100 times thicker than the GaN layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 25 times thicker than the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is polycrystalline. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is monocrystalline. withdrawn
A method of making a mounted gallium nitride (GaN) device, comprising: -4- MT₁₁₃₄₁ZK-US obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer, after formin g the active layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and after sawin g the wafer, attaching the silicon layer of the device structure to a heat sink structure with a eutectic bond comprising gold and silicon.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 100 times thicker than the GaN layer.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 25 times thicker than the silicon layer.
The method of claim 17, wherein the step of obtaining is further characterized by the silicon layer being polysilicon.
Layer stacks claimed or described, ordered top of device to substrate.
mounted GaN device (wafer/die structure)
mounted GaN device (packaged with heat sink)
Materials described outside the worked examples.
silicon layer
Si
silicon carbide layer
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,318,545Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-section view of a semiconductor device 10 during a processing stage. By way of example, semiconductor device 10 may include a wafer …
FIG. 2, by processing GaN layer 16, an active layer 18 having various active devices and interconnects may be formed over GaN layer 16. This layer may be …
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
FIG. 4, a heat sink 24 having a gold layer 22, which may be plated on it, may be brought in contact with SiC substrate layer 12 having gold layer 20. The two …
FIG. 5, the pressing, heating, and scrubbing of the die with heat sink 24 will result in heat sink 24 getting attached to the singulated die resulting in a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of making a mounted gallium nitride (GaN), comprising: obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer; after the step of processing the GaN layer, forming a gold layer on the silicon layer; after formin g the g old layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and attaching the device structure to a heat sink structure using the gold layer.
The method of claim 1, wherein the step of attaching is further characterized as forming a eutectic bond.
The method of claim 1, wherein the step of attaching is further characterized by the heat sink structure further characterized as having at least a layer of gold.
The method of claim 1, wherein the step of obtaining the device structure is further characterized by the SiC layer functioning as a substrate.
The method of claim 1, wherein the step of attaching is further characterized as forming a gold/silicon eutectic bond by scrubbing and applying heat and pressure between the gold layer and a layer of gold on the heat sink structure.
A mounted gallium nitride (GaN) device, comprising: a silicon layer; a silicon carbide (SiC) layer over the silicon layer; a GaN layer over the SiC layer; an active layer of active devices and interconnect over the GaN layer; a heat sink; and a eutectic bond comprising gold and silicon between the heat sink and the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the silicon layer comprises polysilicon. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 100 times thicker than the GaN layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer is at least 25 times thicker than the silicon layer. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is polycrystalline. withdrawn
The mounted GaN device of claim 11, wherein the SiC layer has at least a portion that is monocrystalline. withdrawn
A method of making a mounted gallium nitride (GaN) device, comprising: -4- MT₁₁₃₄₁ZK-US obtaining a device structure in a wafer, the device structure comprising a silicon layer, a silicon carbide (SiC) layer over the silicon layer, and a GaN layer over the SiC layer; processing the GaN layer to form an active layer of active devices and interconnect over the GaN layer, after formin g the active layer, sawin g the wafer so that the device structure is a singulated die from the wafer; and after sawin g the wafer, attaching the silicon layer of the device structure to a heat sink structure with a eutectic bond comprising gold and silicon.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 100 times thicker than the GaN layer.
The method of claim 17, wherein the step of obtaining is further characterized by the SiC layer being at least 25 times thicker than the silicon layer.
The method of claim 17, wherein the step of obtaining is further characterized by the silicon layer being polysilicon.
Layer stacks claimed or described, ordered top of device to substrate.
mounted GaN device (wafer/die structure)
mounted GaN device (packaged with heat sink)
Materials described outside the worked examples.
silicon layer
Si
silicon carbide layer
SiC
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3, a gold (Au) layer 20 may be formed on a non-active side (the side that does not have active layer 16) of semiconductor device 10. As part of this step …
Related documents with shared materials, methods, properties, or citations.
gallium nitride layer
GaN
gold layer
Au
gold/silicon eutectic bond
Au-Si
gallium nitride layer
GaN
gold layer
Au
gold/silicon eutectic bond
Au-Si
gallium nitride layer
GaN
gold layer
Au
gold/silicon eutectic bond
Au-Si
gallium nitride layer
GaN
gold layer
Au
gold/silicon eutectic bond
Au-Si