Patent
US 9,064,947Title: ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS
ROBERTS, John, MIZAN, Ahmad, PATTERSON, Girvan, KLOWAK, Greg
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,064,947Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a plan view example of a prior art building block structure. [0022]
FIG. 2 illustrates a plan view of an embodiment of the present invention. [0023]
FIG. 3 illustrates a cross section taken along the line I- I' of Fig. 2 [0024]
FIG. 4 illustrates a plan view of the embodiment shown in Fig. 2. [0025]
FIG. 5 illustrates a plan of a second embodiment of the present invention. [0026]
FIG. 6 illustrates a plan view of a third embodiment of the present invention. 6 WO 2011/014951 PCT/CA₂ 010/001202 [0027]
FIG. 7 illustrates packaging of the embodiment shown in Fig. 4
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a) a substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump or ball connection formed thereon; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and g) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 1, wherein the drain and source island electrodes are each a four-sided figure.
The device of claim 1, wherein the drain and source island electrodes are triangular shaped.
The device of claim 1, wherein the drain and source island electrodes are a combination of various variants of polygon shapes that allow drain/source island juxtapositioning.
The device of claim 1, wherein the low resistance gate interconnect comprises a low resistance metal strap connecting each of the plurality of gate electrodes to the plurality of gate pads.
The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said nitride semiconductor layer.
The device of claim 1, wherein each of the said first and second ball connections is formed of gold.
The device of claim 1 wherein the nitride semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.
The device of claim 1, wherein each of the gate electrodes is formed from palladium, and source and drain island electrodes are made from titanium and aluminum.
The device of claim 1, wherein the substrate is an insulative high resistance substrate, and the gate connections further comprise bump or ball connections on the gate pads.
The device of claim 1 wherein the source island electrodes and drain island electrodes are substantially square shaped and said ball or bump connections are centred on each island.
A nitride semiconductor device comprising: a) a conductive substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two- dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; and d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a via connection to the conductive substrate; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and h) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 2 further comprising a copper thermal heat sink bonded to the backside of the conductive substrate in electrical contact therewith, and wherein the copper thermal heat sink provides a backside source connection. 16 The device of claim 15 further comprising a package and wherein the gate connections comprise bump or ball connections on the gate pads and wherein the drain bump or ball connections and the gate bump or ball connections are directly bonded to respective copper tracks of the package.
The device of claim 2 wherein the source island electrodes and drain island electrodes are substantially square shaped, and said ball or bump connections or via connections are centred on each island.
Layer stacks claimed or described, ordered top of device to substrate.
island-matrixed GaN field-effect transistor (insulative/non-conductive substrate variant)
island-matrixed GaN field-effect transistor (conductive substrate variant with via source connections)
Materials described outside the worked examples.
nitride semiconductor hetero-layer
undoped gallium nitride
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 150–450 µm | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,947Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a plan view example of a prior art building block structure. [0022]
FIG. 2 illustrates a plan view of an embodiment of the present invention. [0023]
FIG. 3 illustrates a cross section taken along the line I- I' of Fig. 2 [0024]
FIG. 4 illustrates a plan view of the embodiment shown in Fig. 2. [0025]
FIG. 5 illustrates a plan of a second embodiment of the present invention. [0026]
FIG. 6 illustrates a plan view of a third embodiment of the present invention. 6 WO 2011/014951 PCT/CA₂ 010/001202 [0027]
FIG. 7 illustrates packaging of the embodiment shown in Fig. 4
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a) a substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump or ball connection formed thereon; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and g) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 1, wherein the drain and source island electrodes are each a four-sided figure.
The device of claim 1, wherein the drain and source island electrodes are triangular shaped.
The device of claim 1, wherein the drain and source island electrodes are a combination of various variants of polygon shapes that allow drain/source island juxtapositioning.
The device of claim 1, wherein the low resistance gate interconnect comprises a low resistance metal strap connecting each of the plurality of gate electrodes to the plurality of gate pads.
The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said nitride semiconductor layer.
The device of claim 1, wherein each of the said first and second ball connections is formed of gold.
The device of claim 1 wherein the nitride semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.
The device of claim 1, wherein each of the gate electrodes is formed from palladium, and source and drain island electrodes are made from titanium and aluminum.
The device of claim 1, wherein the substrate is an insulative high resistance substrate, and the gate connections further comprise bump or ball connections on the gate pads.
The device of claim 1 wherein the source island electrodes and drain island electrodes are substantially square shaped and said ball or bump connections are centred on each island.
A nitride semiconductor device comprising: a) a conductive substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two- dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; and d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a via connection to the conductive substrate; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and h) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 2 further comprising a copper thermal heat sink bonded to the backside of the conductive substrate in electrical contact therewith, and wherein the copper thermal heat sink provides a backside source connection. 16 The device of claim 15 further comprising a package and wherein the gate connections comprise bump or ball connections on the gate pads and wherein the drain bump or ball connections and the gate bump or ball connections are directly bonded to respective copper tracks of the package.
The device of claim 2 wherein the source island electrodes and drain island electrodes are substantially square shaped, and said ball or bump connections or via connections are centred on each island.
Layer stacks claimed or described, ordered top of device to substrate.
island-matrixed GaN field-effect transistor (insulative/non-conductive substrate variant)
island-matrixed GaN field-effect transistor (conductive substrate variant with via source connections)
Materials described outside the worked examples.
nitride semiconductor hetero-layer
undoped gallium nitride
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 150–450 µm | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,947Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a plan view example of a prior art building block structure. [0022]
FIG. 2 illustrates a plan view of an embodiment of the present invention. [0023]
FIG. 3 illustrates a cross section taken along the line I- I' of Fig. 2 [0024]
FIG. 4 illustrates a plan view of the embodiment shown in Fig. 2. [0025]
FIG. 5 illustrates a plan of a second embodiment of the present invention. [0026]
FIG. 6 illustrates a plan view of a third embodiment of the present invention. 6 WO 2011/014951 PCT/CA₂ 010/001202 [0027]
FIG. 7 illustrates packaging of the embodiment shown in Fig. 4
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a) a substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump or ball connection formed thereon; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and g) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 1, wherein the drain and source island electrodes are each a four-sided figure.
The device of claim 1, wherein the drain and source island electrodes are triangular shaped.
The device of claim 1, wherein the drain and source island electrodes are a combination of various variants of polygon shapes that allow drain/source island juxtapositioning.
The device of claim 1, wherein the low resistance gate interconnect comprises a low resistance metal strap connecting each of the plurality of gate electrodes to the plurality of gate pads.
The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said nitride semiconductor layer.
The device of claim 1, wherein each of the said first and second ball connections is formed of gold.
The device of claim 1 wherein the nitride semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.
The device of claim 1, wherein each of the gate electrodes is formed from palladium, and source and drain island electrodes are made from titanium and aluminum.
The device of claim 1, wherein the substrate is an insulative high resistance substrate, and the gate connections further comprise bump or ball connections on the gate pads.
The device of claim 1 wherein the source island electrodes and drain island electrodes are substantially square shaped and said ball or bump connections are centred on each island.
A nitride semiconductor device comprising: a) a conductive substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two- dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; and d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a via connection to the conductive substrate; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and h) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 2 further comprising a copper thermal heat sink bonded to the backside of the conductive substrate in electrical contact therewith, and wherein the copper thermal heat sink provides a backside source connection. 16 The device of claim 15 further comprising a package and wherein the gate connections comprise bump or ball connections on the gate pads and wherein the drain bump or ball connections and the gate bump or ball connections are directly bonded to respective copper tracks of the package.
The device of claim 2 wherein the source island electrodes and drain island electrodes are substantially square shaped, and said ball or bump connections or via connections are centred on each island.
Layer stacks claimed or described, ordered top of device to substrate.
island-matrixed GaN field-effect transistor (insulative/non-conductive substrate variant)
island-matrixed GaN field-effect transistor (conductive substrate variant with via source connections)
Materials described outside the worked examples.
nitride semiconductor hetero-layer
undoped gallium nitride
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 150–450 µm | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,064,947Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a plan view example of a prior art building block structure. [0022]
FIG. 2 illustrates a plan view of an embodiment of the present invention. [0023]
FIG. 3 illustrates a cross section taken along the line I- I' of Fig. 2 [0024]
FIG. 4 illustrates a plan view of the embodiment shown in Fig. 2. [0025]
FIG. 5 illustrates a plan of a second embodiment of the present invention. [0026]
FIG. 6 illustrates a plan view of a third embodiment of the present invention. 6 WO 2011/014951 PCT/CA₂ 010/001202 [0027]
FIG. 7 illustrates packaging of the embodiment shown in Fig. 4
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride semiconductor device comprising: a) a substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump or ball connection formed thereon; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and g) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 1, wherein the drain and source island electrodes are each a four-sided figure.
The device of claim 1, wherein the drain and source island electrodes are triangular shaped.
The device of claim 1, wherein the drain and source island electrodes are a combination of various variants of polygon shapes that allow drain/source island juxtapositioning.
The device of claim 1, wherein the low resistance gate interconnect comprises a low resistance metal strap connecting each of the plurality of gate electrodes to the plurality of gate pads.
The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said nitride semiconductor layer.
The device of claim 1, wherein each of the said first and second ball connections is formed of gold.
The device of claim 1 wherein the nitride semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.
The device of claim 1, wherein each of the gate electrodes is formed from palladium, and source and drain island electrodes are made from titanium and aluminum.
The device of claim 1, wherein the substrate is an insulative high resistance substrate, and the gate connections further comprise bump or ball connections on the gate pads.
The device of claim 1 wherein the source island electrodes and drain island electrodes are substantially square shaped and said ball or bump connections are centred on each island.
A nitride semiconductor device comprising: a) a conductive substrate; b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate; c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi- island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and a rr anged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two- dimensional active regions in a device area of the nitride semiconductor layer, with: i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode; ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; and d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a via connection to the conductive substrate; f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon; and h) the low resistance gate interconnect being connected to a plurality of gate pads.
The device of claim 2 further comprising a copper thermal heat sink bonded to the backside of the conductive substrate in electrical contact therewith, and wherein the copper thermal heat sink provides a backside source connection. 16 The device of claim 15 further comprising a package and wherein the gate connections comprise bump or ball connections on the gate pads and wherein the drain bump or ball connections and the gate bump or ball connections are directly bonded to respective copper tracks of the package.
The device of claim 2 wherein the source island electrodes and drain island electrodes are substantially square shaped, and said ball or bump connections or via connections are centred on each island.
Layer stacks claimed or described, ordered top of device to substrate.
island-matrixed GaN field-effect transistor (insulative/non-conductive substrate variant)
island-matrixed GaN field-effect transistor (conductive substrate variant with via source connections)
Materials described outside the worked examples.
nitride semiconductor hetero-layer
undoped gallium nitride
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 150–450 µm | — |
Thickness | 3–20 µm |
Related documents with shared materials, methods, properties, or citations.
undoped aluminum gallium nitride
AlGaN
gold
Au
palladium
Pd
titanium
Ti
aluminum
Al
copper
Cu
| — |
Thickness | ≤ 3 mm | — |
undoped aluminum gallium nitride
AlGaN
gold
Au
palladium
Pd
titanium
Ti
aluminum
Al
copper
Cu
| — |
Thickness | ≤ 3 mm | — |
undoped aluminum gallium nitride
AlGaN
gold
Au
palladium
Pd
titanium
Ti
aluminum
Al
copper
Cu
| — |
Thickness | ≤ 3 mm | — |
undoped aluminum gallium nitride
AlGaN
gold
Au
palladium
Pd
titanium
Ti
aluminum
Al
copper
Cu
| — |
Thickness | ≤ 3 mm | — |