Patent
US 10,714,605HIGHLY SCALED LINEAR GaN HEMT STRUCTURES
Jeong-Sun MOON
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,714,605Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 3A shows a graded and composite channel GaN HEMT structure, and FIG s. 3B and 3C show graphs of the carrier density vs. depth and characteristics of the …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 1 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded Al G aN layer on the second G aN layer.
The transistor of claim 1 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 1 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 1: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 7 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded AlGaN layer on the second G aN layer.
The transistor of claim 7 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 7 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 7: wherein the first graded AlGaN layer comprises Al GAiXN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The transistor of claim 7: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; and providing a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded AlG aN layer on the first G aN layer.
The method of claim 14 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 14 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 14 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 14: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; providing a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and providing a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The method of claim 20 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 20 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 20 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 20: wherein the first graded AlG aN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlG aN layer, or varies from 0 to 0.3 over the thickness of the first graded AlG aN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The method of claim 20: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
Layer stacks claimed or described, ordered top of device to substrate.
single-gate GaN HEMT with graded channel
single-gate GaN HEMT with composite channel
Materials described outside the worked examples.
GaN
graded AlGaN
AlxGa₁-xN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 40–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
Patent
Atlas literature
Patent
US 10,714,605Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 3A shows a graded and composite channel GaN HEMT structure, and FIG s. 3B and 3C show graphs of the carrier density vs. depth and characteristics of the …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 1 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded Al G aN layer on the second G aN layer.
The transistor of claim 1 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 1 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 1: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 7 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded AlGaN layer on the second G aN layer.
The transistor of claim 7 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 7 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 7: wherein the first graded AlGaN layer comprises Al GAiXN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The transistor of claim 7: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; and providing a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded AlG aN layer on the first G aN layer.
The method of claim 14 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 14 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 14 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 14: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; providing a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and providing a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The method of claim 20 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 20 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 20 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 20: wherein the first graded AlG aN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlG aN layer, or varies from 0 to 0.3 over the thickness of the first graded AlG aN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The method of claim 20: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
Layer stacks claimed or described, ordered top of device to substrate.
single-gate GaN HEMT with graded channel
single-gate GaN HEMT with composite channel
Materials described outside the worked examples.
GaN
graded AlGaN
AlxGa₁-xN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 40–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
Patent
Atlas literature
Patent
US 10,714,605Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 3A shows a graded and composite channel GaN HEMT structure, and FIG s. 3B and 3C show graphs of the carrier density vs. depth and characteristics of the …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 1 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded Al G aN layer on the second G aN layer.
The transistor of claim 1 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 1 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 1: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 7 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded AlGaN layer on the second G aN layer.
The transistor of claim 7 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 7 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 7: wherein the first graded AlGaN layer comprises Al GAiXN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The transistor of claim 7: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; and providing a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded AlG aN layer on the first G aN layer.
The method of claim 14 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 14 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 14 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 14: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; providing a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and providing a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The method of claim 20 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 20 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 20 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 20: wherein the first graded AlG aN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlG aN layer, or varies from 0 to 0.3 over the thickness of the first graded AlG aN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The method of claim 20: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
Layer stacks claimed or described, ordered top of device to substrate.
single-gate GaN HEMT with graded channel
single-gate GaN HEMT with composite channel
Materials described outside the worked examples.
GaN
graded AlGaN
AlxGa₁-xN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 40–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
Patent
Atlas literature
Patent
US 10,714,605Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 3A shows a graded and composite channel GaN HEMT structure, and FIG s. 3B and 3C show graphs of the carrier density vs. depth and characteristics of the …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; and a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 1 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded Al G aN layer on the second G aN layer.
The transistor of claim 1 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 1 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 1: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A transistor comprising: a substrate; a channel layer coupled to the substrate; a source electrode coupled to the channel layer; a drain electrode coupled to the channel layer; a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The transistor of claim 7 wherein the channel layer further comprises a composite channel comprising: the at least a first G aN layer; the first graded Al G aN layer on the first G aN layer; a Si delta doping layer on the first graded Al G aN layer; a second G aN layer on the Si delta doping layer; and a second graded AlGaN layer on the second G aN layer.
The transistor of claim 7 further comprising: an Al G aN barrier layer on the channel layer.
The transistor of claim 7 further comprising: a back barrier layer between the substrate and the channel layer.
The transistor of claim 7: wherein the first graded AlGaN layer comprises Al GAiXN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The transistor of claim 7: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; and providing a gate electrode coupled to the channel layer between the source electrode and the drain electrode; wherein the gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded AlG aN layer on the first G aN layer.
The method of claim 14 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 14 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 14 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 14: wherein the first graded AlGaN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlGaN layer, or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
A method of providing a transistor comprising: providing a substrate; providing a channel layer coupled to the substrate; providing a source electrode coupled to the channel layer; providing a drain electrode coupled to the channel layer; providing a first gate electrode coupled to the channel layer between the source electrode and the drain electrode; and providing a second gate electrode coupled to the channel layer between the first gate electrode and the drain electrode; wherein the first gate electrode has a gate length dimension of less than 50 nanometers near the channel layer; and wherein the channel layer comprises: at least a first G aN layer; and a first graded Al G aN layer on the first G aN layer.
The method of claim 20 further comprising: providing a composite channel, the composite channel comprising: the at least a first G aN layer; the first graded AlG aN layer on the first GaN layer; a Si delta doping layer on the first graded AlGaN layer; a second G aN layer on the Si delta doping layer; and a second graded AlG aN layer on the second GaN layer.
The method of claim 20 further comprising: providing an AlG aN barrier layer on the channel layer.
The method of claim 20 further comprising: providing a back barrier layer between the substrate and the channel layer.
The method of claim 20: wherein the first graded AlG aN layer comprises Al xGAixN; wherein x varies from 0 to 0.1 over a thickness of the first graded AlG aN layer, or varies from 0 to 0.3 over the thickness of the first graded AlG aN layer; and wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.
The method of claim 20: wherein the first gate is a radio frequency (R F) gate; and wherein the second gate is a direct current (DC) gate for reducing Rds and Cgd nonlinearities.
Layer stacks claimed or described, ordered top of device to substrate.
single-gate GaN HEMT with graded channel
single-gate GaN HEMT with composite channel
Materials described outside the worked examples.
GaN
graded AlGaN
AlxGa₁-xN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 B shows a scaled linear GaN HEMT structure with a single gate in accordance with the present disclosure; [0016] FIG s. 2A, 2B, 2C, 2D, 2E, 2F, and 2G …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 40–50 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE
GALLIUM NITRIDE (GAN) POWER AMPLIFIERS (PA) WITH ANGLED ELECTRODES AND 100 CMOS AND METHOD FOR PRODUCING THE SAME
dual-gate GaN HEMT with graded channel
dual-gate GaN HEMT with composite channel
dual-gate linear GaN HEMT (described embodiment)
Si delta doping layer
AlN
AlGaN
Al0.30Ga0.70N barrier
Al0.30Ga0.70N
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
| — |
Thickness | ≤ 60 Å | — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 6 nm | — |
dual-gate GaN HEMT with graded channel
dual-gate GaN HEMT with composite channel
dual-gate linear GaN HEMT (described embodiment)
Si delta doping layer
AlN
AlGaN
Al0.30Ga0.70N barrier
Al0.30Ga0.70N
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
| — |
Thickness | ≤ 60 Å | — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 6 nm | — |
dual-gate GaN HEMT with graded channel
dual-gate GaN HEMT with composite channel
dual-gate linear GaN HEMT (described embodiment)
Si delta doping layer
AlN
AlGaN
Al0.30Ga0.70N barrier
Al0.30Ga0.70N
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
| — |
Thickness | ≤ 60 Å | — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 6 nm | — |
dual-gate GaN HEMT with graded channel
dual-gate GaN HEMT with composite channel
dual-gate linear GaN HEMT (described embodiment)
Si delta doping layer
AlN
AlGaN
Al0.30Ga0.70N barrier
Al0.30Ga0.70N
FIG. 2C. [0039] A Si delta-doping layer 53 having a layer of which may be A lo. 3 Ga o. 7 N with a thickness of about 50 Angstroms on a layer of AlN having a …
FIG. 4A shows a SEM image of a fabricated dual-gate GaN HEMT device having the structure depicted in
| — |
Thickness | ≤ 60 Å | — |
Thickness | ≤ 50 nm | — |
Thickness | ≤ 6 nm | — |