Patent
US 10,930,576GALLIUM-NITRIDE BASED DEVICES IMPLEMENTING AN ENGINEERED SUBSTRATE STRUCTURE
Vladimir Odnoblyudov, Cem Basceri, Shari Farrens, Ozgur Aktas
QROMIS, I NC.·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,930,576Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 2A is a secondary ion mass spectroscopy (SIMS) profile illustrating species concentration as a function of depth for an engineered structure according to …
FIG. 3 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 8 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to another embodiment of the present invention. The …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 14A is a simplified schematic diagram illustrating an acoustic resonator fabricated using an engineered substrate 1402 according to an embodiment of the …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
FIG. 16A is a simplified schematic diagram illustrating a MEMS device fabricated using an engineered substrate 1602 according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A micro-electromechanical system (MEMS) device comprising: a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion l ayer; wherein the support structure defines a cavity; and a I II -V membrane coupled to a portion of the support structure, wherein a portion of the III -V membrane is suspended over the cavity defined by the support structure and defines a M EMS structure. Original
The MEMS device of claim 1 wherein the polycrystalline ceramic core comprises aluminum nitride. Original
The MEMS device of claim 1 wherein: the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer comprises a polysilicon layer encapsulating the first TEOS oxide layer; the second adhesion layer comprises a second TEOS layer encapsulating the polysilicon layer; and the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer. Original
The MEMS device of claim 1 wherein the support structure further comprises: a bonding layer coupled to the barrier layer; a substantially single crystalline silicon layer coupled to the bonding layer; and a buffer layer coupled to the substantially single crystalline silicon layer; wherein the I II -V membrane is epitaxially grown on the buffer layer. Original
The MEMS device of claim 1 wherein the M EMS structure comprises a cantilever, or a resonator, or an interdigitated capacitor, or a piezo-electric actuator. Original
Layer stacks claimed or described, ordered top of device to substrate.
MEMS device
Materials described outside the worked examples.
polycrystalline ceramic core
aluminum nitride (polycrystalline ceramic core)
AlN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.1 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,576Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 2A is a secondary ion mass spectroscopy (SIMS) profile illustrating species concentration as a function of depth for an engineered structure according to …
FIG. 3 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 8 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to another embodiment of the present invention. The …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 14A is a simplified schematic diagram illustrating an acoustic resonator fabricated using an engineered substrate 1402 according to an embodiment of the …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
FIG. 16A is a simplified schematic diagram illustrating a MEMS device fabricated using an engineered substrate 1602 according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A micro-electromechanical system (MEMS) device comprising: a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion l ayer; wherein the support structure defines a cavity; and a I II -V membrane coupled to a portion of the support structure, wherein a portion of the III -V membrane is suspended over the cavity defined by the support structure and defines a M EMS structure. Original
The MEMS device of claim 1 wherein the polycrystalline ceramic core comprises aluminum nitride. Original
The MEMS device of claim 1 wherein: the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer comprises a polysilicon layer encapsulating the first TEOS oxide layer; the second adhesion layer comprises a second TEOS layer encapsulating the polysilicon layer; and the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer. Original
The MEMS device of claim 1 wherein the support structure further comprises: a bonding layer coupled to the barrier layer; a substantially single crystalline silicon layer coupled to the bonding layer; and a buffer layer coupled to the substantially single crystalline silicon layer; wherein the I II -V membrane is epitaxially grown on the buffer layer. Original
The MEMS device of claim 1 wherein the M EMS structure comprises a cantilever, or a resonator, or an interdigitated capacitor, or a piezo-electric actuator. Original
Layer stacks claimed or described, ordered top of device to substrate.
MEMS device
Materials described outside the worked examples.
polycrystalline ceramic core
aluminum nitride (polycrystalline ceramic core)
AlN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.1 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,576Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 2A is a secondary ion mass spectroscopy (SIMS) profile illustrating species concentration as a function of depth for an engineered structure according to …
FIG. 3 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 8 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to another embodiment of the present invention. The …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 14A is a simplified schematic diagram illustrating an acoustic resonator fabricated using an engineered substrate 1402 according to an embodiment of the …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
FIG. 16A is a simplified schematic diagram illustrating a MEMS device fabricated using an engineered substrate 1602 according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A micro-electromechanical system (MEMS) device comprising: a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion l ayer; wherein the support structure defines a cavity; and a I II -V membrane coupled to a portion of the support structure, wherein a portion of the III -V membrane is suspended over the cavity defined by the support structure and defines a M EMS structure. Original
The MEMS device of claim 1 wherein the polycrystalline ceramic core comprises aluminum nitride. Original
The MEMS device of claim 1 wherein: the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer comprises a polysilicon layer encapsulating the first TEOS oxide layer; the second adhesion layer comprises a second TEOS layer encapsulating the polysilicon layer; and the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer. Original
The MEMS device of claim 1 wherein the support structure further comprises: a bonding layer coupled to the barrier layer; a substantially single crystalline silicon layer coupled to the bonding layer; and a buffer layer coupled to the substantially single crystalline silicon layer; wherein the I II -V membrane is epitaxially grown on the buffer layer. Original
The MEMS device of claim 1 wherein the M EMS structure comprises a cantilever, or a resonator, or an interdigitated capacitor, or a piezo-electric actuator. Original
Layer stacks claimed or described, ordered top of device to substrate.
MEMS device
Materials described outside the worked examples.
polycrystalline ceramic core
aluminum nitride (polycrystalline ceramic core)
AlN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.1 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,930,576Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 2A is a secondary ion mass spectroscopy (SIMS) profile illustrating species concentration as a function of depth for an engineered structure according to …
FIG. 3 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 110 that can have a coefficient of thermal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 8 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to another embodiment of the present invention. The …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 14A is a simplified schematic diagram illustrating an acoustic resonator fabricated using an engineered substrate 1402 according to an embodiment of the …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
FIG. 16A is a simplified schematic diagram illustrating a MEMS device fabricated using an engineered substrate 1602 according to an embodiment of the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A micro-electromechanical system (MEMS) device comprising: a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion l ayer; wherein the support structure defines a cavity; and a I II -V membrane coupled to a portion of the support structure, wherein a portion of the III -V membrane is suspended over the cavity defined by the support structure and defines a M EMS structure. Original
The MEMS device of claim 1 wherein the polycrystalline ceramic core comprises aluminum nitride. Original
The MEMS device of claim 1 wherein: the first adhesion layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer comprises a polysilicon layer encapsulating the first TEOS oxide layer; the second adhesion layer comprises a second TEOS layer encapsulating the polysilicon layer; and the barrier layer comprises a silicon nitride layer encapsulating the second TEOS layer. Original
The MEMS device of claim 1 wherein the support structure further comprises: a bonding layer coupled to the barrier layer; a substantially single crystalline silicon layer coupled to the bonding layer; and a buffer layer coupled to the substantially single crystalline silicon layer; wherein the I II -V membrane is epitaxially grown on the buffer layer. Original
The MEMS device of claim 1 wherein the M EMS structure comprises a cantilever, or a resonator, or an interdigitated capacitor, or a piezo-electric actuator. Original
Layer stacks claimed or described, ordered top of device to substrate.
MEMS device
Materials described outside the worked examples.
polycrystalline ceramic core
aluminum nitride (polycrystalline ceramic core)
AlN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.1 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
acoustic resonator
first TEOS layer (first adhesion layer)
polysilicon layer (conductive layer)
second TEOS layer (second adhesion layer)
silicon nitride layer (barrier layer)
Si₃N₄
bonding layer
substantially single crystalline silicon layer
Si
buffer layer
epitaxial aluminum gallium nitride (III-V membrane)
AlGaN
epitaxial gallium nitride (III-V membrane)
GaN
III-V membrane
silicon oxide layer
SiO₂
epitaxial III-V layer
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
| — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 1 V | — |
acoustic resonator
first TEOS layer (first adhesion layer)
polysilicon layer (conductive layer)
second TEOS layer (second adhesion layer)
silicon nitride layer (barrier layer)
Si₃N₄
bonding layer
substantially single crystalline silicon layer
Si
buffer layer
epitaxial aluminum gallium nitride (III-V membrane)
AlGaN
epitaxial gallium nitride (III-V membrane)
GaN
III-V membrane
silicon oxide layer
SiO₂
epitaxial III-V layer
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
| — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 1 V | — |
acoustic resonator
first TEOS layer (first adhesion layer)
polysilicon layer (conductive layer)
second TEOS layer (second adhesion layer)
silicon nitride layer (barrier layer)
Si₃N₄
bonding layer
substantially single crystalline silicon layer
Si
buffer layer
epitaxial aluminum gallium nitride (III-V membrane)
AlGaN
epitaxial gallium nitride (III-V membrane)
GaN
III-V membrane
silicon oxide layer
SiO₂
epitaxial III-V layer
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
| — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 1 V | — |
acoustic resonator
first TEOS layer (first adhesion layer)
polysilicon layer (conductive layer)
second TEOS layer (second adhesion layer)
silicon nitride layer (barrier layer)
Si₃N₄
bonding layer
substantially single crystalline silicon layer
Si
buffer layer
epitaxial aluminum gallium nitride (III-V membrane)
AlGaN
epitaxial gallium nitride (III-V membrane)
GaN
III-V membrane
silicon oxide layer
SiO₂
epitaxial III-V layer
FIG. 1. The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. Moreover, the crystal …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 4, it will be appreciated that deposition of adhesion layer material on other portions of the core will not adversely impact the performance of the …
FIG. 5 is a simplified flowchart illustrating a method of fabricating an engineered substrate according to an embodiment of the present invention. The method can …
FIG. 7 is a simplified schematic diagram illustrating a I II -V epitaxial layer on an engineered substrate structure according to an embodiment of the present …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 9 is a simplified schematic diagram of a fin-FET with a quasi-vertical architecture fabricated using an engineered substrate 902 according to an embodiment …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 10 is a simplified schematic diagram illustrating a fin-FET fabricated using an engineered substrate after removal from the engineered substrate according …
FIG. 11 is a simplified schematic diagram of a sidewall metal-oxide-semiconductor field-effect transistor (MOSFET) with a quasi-vertical architecture fabricated …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 12 is a simplified schematic diagram of a sidewall MOS transistor with a quasi- vertical architecture fabricated using an engineered substrate after …
FIG. 13 is a simplified schematic diagram of an MOS transistor fabricated using an engineered substrate 1302 according to an embodiment of the present …
FIG. 15 is a simplified schematic diagram illustrating a micro-LED display fabricated using an engineered substrate after removal from the engineered substrate …
| — |
Thickness | ≤ 0.5 nm | — |
Thickness | ≤ 0.2 nm | — |
Voltage | ≥ 1 V | — |