Patent
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Patent
US 12,142,639 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 3.
FIGS. 4-21 are partial sectional side elevation views of the electronic device of
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 7 shows one example, in which an epitaxial deposition process 700 is performed that deposits the second aluminum nitride 60 sublayer 108 over the first …
FIG. 8 shows one example in which an epitaxial 65 deposition process 800 is performed that deposits the second aluminum gallium nitride sublayer 109 over the …
FIG. 9. The method 300 continues at 306 with performing an epitaxial deposition process 1000 that forms an aluminum gallium nitride interlayer 110 over the …
FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the aluminum gallium nitride layer 110 over the top …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIGS. 13 and 14 show epitaxial deposition processes 1300 and 1400 that respectively form the next pair of aluminum nitride and gallium nitride sublayers 113 …
FIG. 14 deposits the second gallium nitride sublayer 114, for example, using process parameters as described above in connection with
FIG. 15. The method 300 continues at 310 with performing an 10 epitaxial deposition process that deposits at least one layer of the buffer structure using an …
FIG. 16 shows one example, in which an epitaxial deposi- tion process 1600 is performed that deposits the carbon doped gallium nitride layer 116 (GAN:C) over …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 21. The method 300 further also includes forming the gate, drain and source structures (e.g., 131, 132, 134, 135, 136 and 138 in
FIG. 22 is a perspective view of a packaged electronic device fabricated according to the method of
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 25 is a flow diagram of a method for making an 5 electronic device according to a further aspect.
FIGS. 26-35 are partial sectional side elevation views of the electronic device of
FIG. 27 shows one example, in which an epitaxial deposition process 2700 is performed that deposits the first aluminum gallium nitride sublayer 2311 over the …
FIG. 28 shows one example, in which a second epitaxial deposition process 2800 is performed that deposits the second aluminum gal- lium nitride sublayer 2312 …
FIG. 29 shows one example, in which a third epitaxial deposition process 2900 is performed that deposits the third aluminum gallium nitride sublayer 2313 with …
FIG. 30 shows one example, in which an epitaxial deposition process 3000 is performed that deposits the carbon doped gallium nitride layer 2316 (GAN:C) over …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
FIG. 35. The method 2500 further also includes forming the gate, 65 drain and source structures (e.g., 23323, 2332, 2334, 2335, 2336 and 2338 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a first superlattice over the substrate, the first superlattice including alternating pairs of respective aluminum nitride and aluminum gallium nitride layers; a second superlattice over the first superlattice, the second superlattice including alternating pairs of respective aluminum nitride and gallium nitride layers; a hetero-epitaxy structure over the second superlattice; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 1, further compris-ing: an aluminum nitride layer over the substrate, wherein the first superlattice is disposed over the aluminum nitride layer.
The semiconductor device of claim 1, further compris-ing: an aluminum gallium nitride layer over the first superla-ttice, wherein the second superlattice is disposed over the aluminum gallium nitride layer.
The semiconductor device of claim 1, further compris-ing: a carbon doped gallium nitride layer disposed over the second superlattice; and a gallium nitride layer disposed over the carbon doped gallium nitride layer.
The semiconductor device of claim 1, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the second superlattice and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 1, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the second superlattice: the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 1, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer.
A semiconductor device, comprising: a substrate; a first aluminum gallium nitride layer over the substrate, the first aluminum gallium nitride layer including a first carbon concentration; 35 a second aluminum gallium nitride layer over the first aluminum gallium nitride layer, the second aluminum gallium nitride layer including a second carbon con-centration; a third aluminum gallium nitride layer over the second aluminum gallium nitride layer, the third aluminum gallium nitride layer including a third carbon concen-tration; a carbon doped gallium nitride layer over the third alu-minum gallium nitride layer; 45 a gallium nitride layer over the carbon doped gallium nitride layer; a hetero-epitaxy structure over the gallium nitride layer; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and 50 a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 12, further com-prising: an aluminum nitride layer over the substrate, wherein the first aluminum gallium nitride layer is disposed over the aluminum nitride layer.
The semiconductor device of claim 12, wherein the first, second, and third aluminum gallium nitride layer are formed based on using an extrinsic carbon source.
The semiconductor device of claim 12, wherein: the first carbon concentration ranges between 1×1017 and 1×1018 atoms/cm3; the second carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3; and the third carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration by at least two orders of magnitude.
The semiconductor device of claim 12, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the gallium nitride layer and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 12, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the gallium nitride layer; the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 12, wherein: the first aluminum gallium nitride layer includes a first aluminum concentration; the second aluminum gallium nitride layer includes a second aluminum concentration that is less than the first aluminum concentration; and the third aluminum gallium nitride layer includes a third aluminum concentration that is less than the second aluminum concentration.
The semiconductor device of claim 12, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with dual superlattice buffer
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
second AlGaN:C layer carbon concentration (claim 16) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 17
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US 12,142,639 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 3.
FIGS. 4-21 are partial sectional side elevation views of the electronic device of
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 7 shows one example, in which an epitaxial deposition process 700 is performed that deposits the second aluminum nitride 60 sublayer 108 over the first …
FIG. 8 shows one example in which an epitaxial 65 deposition process 800 is performed that deposits the second aluminum gallium nitride sublayer 109 over the …
FIG. 9. The method 300 continues at 306 with performing an epitaxial deposition process 1000 that forms an aluminum gallium nitride interlayer 110 over the …
FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the aluminum gallium nitride layer 110 over the top …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIGS. 13 and 14 show epitaxial deposition processes 1300 and 1400 that respectively form the next pair of aluminum nitride and gallium nitride sublayers 113 …
FIG. 14 deposits the second gallium nitride sublayer 114, for example, using process parameters as described above in connection with
FIG. 15. The method 300 continues at 310 with performing an 10 epitaxial deposition process that deposits at least one layer of the buffer structure using an …
FIG. 16 shows one example, in which an epitaxial deposi- tion process 1600 is performed that deposits the carbon doped gallium nitride layer 116 (GAN:C) over …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 21. The method 300 further also includes forming the gate, drain and source structures (e.g., 131, 132, 134, 135, 136 and 138 in
FIG. 22 is a perspective view of a packaged electronic device fabricated according to the method of
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 25 is a flow diagram of a method for making an 5 electronic device according to a further aspect.
FIGS. 26-35 are partial sectional side elevation views of the electronic device of
FIG. 27 shows one example, in which an epitaxial deposition process 2700 is performed that deposits the first aluminum gallium nitride sublayer 2311 over the …
FIG. 28 shows one example, in which a second epitaxial deposition process 2800 is performed that deposits the second aluminum gal- lium nitride sublayer 2312 …
FIG. 29 shows one example, in which a third epitaxial deposition process 2900 is performed that deposits the third aluminum gallium nitride sublayer 2313 with …
FIG. 30 shows one example, in which an epitaxial deposition process 3000 is performed that deposits the carbon doped gallium nitride layer 2316 (GAN:C) over …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
FIG. 35. The method 2500 further also includes forming the gate, 65 drain and source structures (e.g., 23323, 2332, 2334, 2335, 2336 and 2338 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a first superlattice over the substrate, the first superlattice including alternating pairs of respective aluminum nitride and aluminum gallium nitride layers; a second superlattice over the first superlattice, the second superlattice including alternating pairs of respective aluminum nitride and gallium nitride layers; a hetero-epitaxy structure over the second superlattice; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 1, further compris-ing: an aluminum nitride layer over the substrate, wherein the first superlattice is disposed over the aluminum nitride layer.
The semiconductor device of claim 1, further compris-ing: an aluminum gallium nitride layer over the first superla-ttice, wherein the second superlattice is disposed over the aluminum gallium nitride layer.
The semiconductor device of claim 1, further compris-ing: a carbon doped gallium nitride layer disposed over the second superlattice; and a gallium nitride layer disposed over the carbon doped gallium nitride layer.
The semiconductor device of claim 1, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the second superlattice and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 1, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the second superlattice: the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 1, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer.
A semiconductor device, comprising: a substrate; a first aluminum gallium nitride layer over the substrate, the first aluminum gallium nitride layer including a first carbon concentration; 35 a second aluminum gallium nitride layer over the first aluminum gallium nitride layer, the second aluminum gallium nitride layer including a second carbon con-centration; a third aluminum gallium nitride layer over the second aluminum gallium nitride layer, the third aluminum gallium nitride layer including a third carbon concen-tration; a carbon doped gallium nitride layer over the third alu-minum gallium nitride layer; 45 a gallium nitride layer over the carbon doped gallium nitride layer; a hetero-epitaxy structure over the gallium nitride layer; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and 50 a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 12, further com-prising: an aluminum nitride layer over the substrate, wherein the first aluminum gallium nitride layer is disposed over the aluminum nitride layer.
The semiconductor device of claim 12, wherein the first, second, and third aluminum gallium nitride layer are formed based on using an extrinsic carbon source.
The semiconductor device of claim 12, wherein: the first carbon concentration ranges between 1×1017 and 1×1018 atoms/cm3; the second carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3; and the third carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration by at least two orders of magnitude.
The semiconductor device of claim 12, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the gallium nitride layer and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 12, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the gallium nitride layer; the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 12, wherein: the first aluminum gallium nitride layer includes a first aluminum concentration; the second aluminum gallium nitride layer includes a second aluminum concentration that is less than the first aluminum concentration; and the third aluminum gallium nitride layer includes a third aluminum concentration that is less than the second aluminum concentration.
The semiconductor device of claim 12, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with dual superlattice buffer
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
second AlGaN:C layer carbon concentration (claim 16) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 17
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,142,639 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 3.
FIGS. 4-21 are partial sectional side elevation views of the electronic device of
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 7 shows one example, in which an epitaxial deposition process 700 is performed that deposits the second aluminum nitride 60 sublayer 108 over the first …
FIG. 8 shows one example in which an epitaxial 65 deposition process 800 is performed that deposits the second aluminum gallium nitride sublayer 109 over the …
FIG. 9. The method 300 continues at 306 with performing an epitaxial deposition process 1000 that forms an aluminum gallium nitride interlayer 110 over the …
FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the aluminum gallium nitride layer 110 over the top …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIGS. 13 and 14 show epitaxial deposition processes 1300 and 1400 that respectively form the next pair of aluminum nitride and gallium nitride sublayers 113 …
FIG. 14 deposits the second gallium nitride sublayer 114, for example, using process parameters as described above in connection with
FIG. 15. The method 300 continues at 310 with performing an 10 epitaxial deposition process that deposits at least one layer of the buffer structure using an …
FIG. 16 shows one example, in which an epitaxial deposi- tion process 1600 is performed that deposits the carbon doped gallium nitride layer 116 (GAN:C) over …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 21. The method 300 further also includes forming the gate, drain and source structures (e.g., 131, 132, 134, 135, 136 and 138 in
FIG. 22 is a perspective view of a packaged electronic device fabricated according to the method of
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 25 is a flow diagram of a method for making an 5 electronic device according to a further aspect.
FIGS. 26-35 are partial sectional side elevation views of the electronic device of
FIG. 27 shows one example, in which an epitaxial deposition process 2700 is performed that deposits the first aluminum gallium nitride sublayer 2311 over the …
FIG. 28 shows one example, in which a second epitaxial deposition process 2800 is performed that deposits the second aluminum gal- lium nitride sublayer 2312 …
FIG. 29 shows one example, in which a third epitaxial deposition process 2900 is performed that deposits the third aluminum gallium nitride sublayer 2313 with …
FIG. 30 shows one example, in which an epitaxial deposition process 3000 is performed that deposits the carbon doped gallium nitride layer 2316 (GAN:C) over …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
FIG. 35. The method 2500 further also includes forming the gate, 65 drain and source structures (e.g., 23323, 2332, 2334, 2335, 2336 and 2338 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a first superlattice over the substrate, the first superlattice including alternating pairs of respective aluminum nitride and aluminum gallium nitride layers; a second superlattice over the first superlattice, the second superlattice including alternating pairs of respective aluminum nitride and gallium nitride layers; a hetero-epitaxy structure over the second superlattice; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 1, further compris-ing: an aluminum nitride layer over the substrate, wherein the first superlattice is disposed over the aluminum nitride layer.
The semiconductor device of claim 1, further compris-ing: an aluminum gallium nitride layer over the first superla-ttice, wherein the second superlattice is disposed over the aluminum gallium nitride layer.
The semiconductor device of claim 1, further compris-ing: a carbon doped gallium nitride layer disposed over the second superlattice; and a gallium nitride layer disposed over the carbon doped gallium nitride layer.
The semiconductor device of claim 1, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the second superlattice and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 1, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the second superlattice: the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 1, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer.
A semiconductor device, comprising: a substrate; a first aluminum gallium nitride layer over the substrate, the first aluminum gallium nitride layer including a first carbon concentration; 35 a second aluminum gallium nitride layer over the first aluminum gallium nitride layer, the second aluminum gallium nitride layer including a second carbon con-centration; a third aluminum gallium nitride layer over the second aluminum gallium nitride layer, the third aluminum gallium nitride layer including a third carbon concen-tration; a carbon doped gallium nitride layer over the third alu-minum gallium nitride layer; 45 a gallium nitride layer over the carbon doped gallium nitride layer; a hetero-epitaxy structure over the gallium nitride layer; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and 50 a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 12, further com-prising: an aluminum nitride layer over the substrate, wherein the first aluminum gallium nitride layer is disposed over the aluminum nitride layer.
The semiconductor device of claim 12, wherein the first, second, and third aluminum gallium nitride layer are formed based on using an extrinsic carbon source.
The semiconductor device of claim 12, wherein: the first carbon concentration ranges between 1×1017 and 1×1018 atoms/cm3; the second carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3; and the third carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration by at least two orders of magnitude.
The semiconductor device of claim 12, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the gallium nitride layer and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 12, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the gallium nitride layer; the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 12, wherein: the first aluminum gallium nitride layer includes a first aluminum concentration; the second aluminum gallium nitride layer includes a second aluminum concentration that is less than the first aluminum concentration; and the third aluminum gallium nitride layer includes a third aluminum concentration that is less than the second aluminum concentration.
The semiconductor device of claim 12, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with dual superlattice buffer
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
second AlGaN:C layer carbon concentration (claim 16) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 17
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,142,639 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 3.
FIGS. 4-21 are partial sectional side elevation views of the electronic device of
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 7 shows one example, in which an epitaxial deposition process 700 is performed that deposits the second aluminum nitride 60 sublayer 108 over the first …
FIG. 8 shows one example in which an epitaxial 65 deposition process 800 is performed that deposits the second aluminum gallium nitride sublayer 109 over the …
FIG. 9. The method 300 continues at 306 with performing an epitaxial deposition process 1000 that forms an aluminum gallium nitride interlayer 110 over the …
FIG. 10 shows one example, in which an epitaxial deposition process 1000 is performed that deposits the aluminum gallium nitride layer 110 over the top …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIGS. 13 and 14 show epitaxial deposition processes 1300 and 1400 that respectively form the next pair of aluminum nitride and gallium nitride sublayers 113 …
FIG. 14 deposits the second gallium nitride sublayer 114, for example, using process parameters as described above in connection with
FIG. 15. The method 300 continues at 310 with performing an 10 epitaxial deposition process that deposits at least one layer of the buffer structure using an …
FIG. 16 shows one example, in which an epitaxial deposi- tion process 1600 is performed that deposits the carbon doped gallium nitride layer 116 (GAN:C) over …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 21. The method 300 further also includes forming the gate, drain and source structures (e.g., 131, 132, 134, 135, 136 and 138 in
FIG. 22 is a perspective view of a packaged electronic device fabricated according to the method of
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 25 is a flow diagram of a method for making an 5 electronic device according to a further aspect.
FIGS. 26-35 are partial sectional side elevation views of the electronic device of
FIG. 27 shows one example, in which an epitaxial deposition process 2700 is performed that deposits the first aluminum gallium nitride sublayer 2311 over the …
FIG. 28 shows one example, in which a second epitaxial deposition process 2800 is performed that deposits the second aluminum gal- lium nitride sublayer 2312 …
FIG. 29 shows one example, in which a third epitaxial deposition process 2900 is performed that deposits the third aluminum gallium nitride sublayer 2313 with …
FIG. 30 shows one example, in which an epitaxial deposition process 3000 is performed that deposits the carbon doped gallium nitride layer 2316 (GAN:C) over …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
FIG. 35. The method 2500 further also includes forming the gate, 65 drain and source structures (e.g., 23323, 2332, 2334, 2335, 2336 and 2338 in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a substrate; a first superlattice over the substrate, the first superlattice including alternating pairs of respective aluminum nitride and aluminum gallium nitride layers; a second superlattice over the first superlattice, the second superlattice including alternating pairs of respective aluminum nitride and gallium nitride layers; a hetero-epitaxy structure over the second superlattice; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 1, further compris-ing: an aluminum nitride layer over the substrate, wherein the first superlattice is disposed over the aluminum nitride layer.
The semiconductor device of claim 1, further compris-ing: an aluminum gallium nitride layer over the first superla-ttice, wherein the second superlattice is disposed over the aluminum gallium nitride layer.
The semiconductor device of claim 1, further compris-ing: a carbon doped gallium nitride layer disposed over the second superlattice; and a gallium nitride layer disposed over the carbon doped gallium nitride layer.
The semiconductor device of claim 1, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the second superlattice and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 1, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the second superlattice: the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 1, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer.
A semiconductor device, comprising: a substrate; a first aluminum gallium nitride layer over the substrate, the first aluminum gallium nitride layer including a first carbon concentration; 35 a second aluminum gallium nitride layer over the first aluminum gallium nitride layer, the second aluminum gallium nitride layer including a second carbon con-centration; a third aluminum gallium nitride layer over the second aluminum gallium nitride layer, the third aluminum gallium nitride layer including a third carbon concen-tration; a carbon doped gallium nitride layer over the third alu-minum gallium nitride layer; 45 a gallium nitride layer over the carbon doped gallium nitride layer; a hetero-epitaxy structure over the gallium nitride layer; a silicon nitride cap layer over the hetero-epitaxy struc-ture; and 50 a transistor having a gate over the hetero-epitaxy struc-ture, a drain extended into the hetero-epitaxy structure and spaced apart from the gate, and a source extended into the hetero-epitaxy structure and spaced apart from the gate and from the drain.
The semiconductor device of claim 12, further com-prising: an aluminum nitride layer over the substrate, wherein the first aluminum gallium nitride layer is disposed over the aluminum nitride layer.
The semiconductor device of claim 12, wherein the first, second, and third aluminum gallium nitride layer are formed based on using an extrinsic carbon source.
The semiconductor device of claim 12, wherein: the first carbon concentration ranges between 1×1017 and 1×1018 atoms/cm3; the second carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3; and the third carbon concentration ranges between 1×1017 and 1×1019 atoms/cm3.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration.
The semiconductor device of claim 12, wherein: the carbon doped gallium nitride layer includes a fourth carbon concentration; and the gallium nitride layer includes a fifth carbon concen-tration less than the fourth carbon concentration by at least two orders of magnitude.
The semiconductor device of claim 12, wherein the hetero-epitaxy structure includes an aluminum nitride layer over the gallium nitride layer and an aluminum gallium nitride layer over the aluminum nitride layer.
The semiconductor device of claim 12, wherein: the hetero-epitaxy structure includes an aluminum gal-lium nitride layer over the gallium nitride layer; the drain partially extends into the aluminum gallium nitride layer; and the source partially extends into the aluminum gallium nitride layer.
The semiconductor device of claim 12, wherein: the first aluminum gallium nitride layer includes a first aluminum concentration; the second aluminum gallium nitride layer includes a second aluminum concentration that is less than the first aluminum concentration; and the third aluminum gallium nitride layer includes a third aluminum concentration that is less than the second aluminum concentration.
The semiconductor device of claim 12, further com-prising: a p-doped gallium nitride layer spaced apart from the source and from the drain over the hetero-epitaxy structure, the gate being over the p-doped gallium nitride layer. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with dual superlattice buffer
Materials described outside the worked examples.
aluminum nitride
AlN
aluminum gallium nitride
AlGaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a partial sectional side elevation view of an electronic device with a depletion mode GaN transistor and an enhancement mode GaN transistor having …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
second AlGaN:C layer carbon concentration (claim 16) | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 17
Related documents with shared materials, methods, properties, or citations.
GaN transistor with multilayer composition-graded AlGaN buffer
first superlattice (AlN/AlGaN)
hetero-epitaxy structure
silicon nitride cap layer
Si₃N₄
carbon doped gallium nitride
GaN:C
gallium nitride (undoped/low carbon)
GaN
ethene
C₂H₄
hexene
C₆H₁₂
p-doped gallium nitride
p-GaN
first aluminum gallium nitride layer (carbon doped, high Al)
AlGaN:C
second superlattice (AlN/GaN)
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
third AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
undoped GaN layer carbon concentration (upper bound, description) | — | GaN |
AlN nucleation layer thickness | — | AlN |
first superlattice AlN sublayer thickness | — | AlN |
first superlattice AlGaN sublayer thickness | — | AlGaN |
first superlattice AlGaN sublayer Al concentration | — | AlGaN |
AlGaN interlayer thickness | — | AlGaN |
AlGaN interlayer Al concentration | — | AlGaN |
second superlattice AlN sublayer thickness | — | AlN |
second superlattice GaN sublayer thickness | — | GaN |
carbon doped GaN layer thickness | — | GaN:C |
undoped GaN layer thickness | — | GaN |
Pressure | 20–50 pa | — |
Thickness | 10–25 nm | — |
Thickness | 300–600 nm | — |
Thickness | 10–20 nm | — |
Thickness | 15–35 nm | — |
Thickness | 10–100 nm | — |
Pressure | 30–70 pa | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–0.5 µm | — |
Thickness | 10–30 nm | — |
Thickness | 50–200 nm | — |
Thickness | 4–6 µm | — |
Thickness | 5–15 Å | — |
Thickness | 20–25 nm | — |
Thickness | 2–10 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–3 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Thickness | 2–20 nm | — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 1–2.5 µm | — |
GaN transistor with multilayer composition-graded AlGaN buffer
first superlattice (AlN/AlGaN)
hetero-epitaxy structure
silicon nitride cap layer
Si₃N₄
carbon doped gallium nitride
GaN:C
gallium nitride (undoped/low carbon)
GaN
ethene
C₂H₄
hexene
C₆H₁₂
p-doped gallium nitride
p-GaN
first aluminum gallium nitride layer (carbon doped, high Al)
AlGaN:C
second superlattice (AlN/GaN)
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
third AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
undoped GaN layer carbon concentration (upper bound, description) | — | GaN |
AlN nucleation layer thickness | — | AlN |
first superlattice AlN sublayer thickness | — | AlN |
first superlattice AlGaN sublayer thickness | — | AlGaN |
first superlattice AlGaN sublayer Al concentration | — | AlGaN |
AlGaN interlayer thickness | — | AlGaN |
AlGaN interlayer Al concentration | — | AlGaN |
second superlattice AlN sublayer thickness | — | AlN |
second superlattice GaN sublayer thickness | — | GaN |
carbon doped GaN layer thickness | — | GaN:C |
undoped GaN layer thickness | — | GaN |
Pressure | 20–50 pa | — |
Thickness | 10–25 nm | — |
Thickness | 300–600 nm | — |
Thickness | 10–20 nm | — |
Thickness | 15–35 nm | — |
Thickness | 10–100 nm | — |
Pressure | 30–70 pa | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–0.5 µm | — |
Thickness | 10–30 nm | — |
Thickness | 50–200 nm | — |
Thickness | 4–6 µm | — |
Thickness | 5–15 Å | — |
Thickness | 20–25 nm | — |
Thickness | 2–10 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–3 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Thickness | 2–20 nm | — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 1–2.5 µm | — |
GaN transistor with multilayer composition-graded AlGaN buffer
first superlattice (AlN/AlGaN)
hetero-epitaxy structure
silicon nitride cap layer
Si₃N₄
carbon doped gallium nitride
GaN:C
gallium nitride (undoped/low carbon)
GaN
ethene
C₂H₄
hexene
C₆H₁₂
p-doped gallium nitride
p-GaN
first aluminum gallium nitride layer (carbon doped, high Al)
AlGaN:C
second superlattice (AlN/GaN)
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
third AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
undoped GaN layer carbon concentration (upper bound, description) | — | GaN |
AlN nucleation layer thickness | — | AlN |
first superlattice AlN sublayer thickness | — | AlN |
first superlattice AlGaN sublayer thickness | — | AlGaN |
first superlattice AlGaN sublayer Al concentration | — | AlGaN |
AlGaN interlayer thickness | — | AlGaN |
AlGaN interlayer Al concentration | — | AlGaN |
second superlattice AlN sublayer thickness | — | AlN |
second superlattice GaN sublayer thickness | — | GaN |
carbon doped GaN layer thickness | — | GaN:C |
undoped GaN layer thickness | — | GaN |
Pressure | 20–50 pa | — |
Thickness | 10–25 nm | — |
Thickness | 300–600 nm | — |
Thickness | 10–20 nm | — |
Thickness | 15–35 nm | — |
Thickness | 10–100 nm | — |
Pressure | 30–70 pa | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–0.5 µm | — |
Thickness | 10–30 nm | — |
Thickness | 50–200 nm | — |
Thickness | 4–6 µm | — |
Thickness | 5–15 Å | — |
Thickness | 20–25 nm | — |
Thickness | 2–10 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–3 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Thickness | 2–20 nm | — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 1–2.5 µm | — |
GaN transistor with multilayer composition-graded AlGaN buffer
first superlattice (AlN/AlGaN)
hetero-epitaxy structure
silicon nitride cap layer
Si₃N₄
carbon doped gallium nitride
GaN:C
gallium nitride (undoped/low carbon)
GaN
ethene
C₂H₄
hexene
C₆H₁₂
p-doped gallium nitride
p-GaN
first aluminum gallium nitride layer (carbon doped, high Al)
AlGaN:C
second superlattice (AlN/GaN)
FIG. 2 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers, a dual …
FIG. 5 to form the second aluminum nitride sublayer 108 to a thickness of 10-25 nm.
FIG. 6 to form the second aluminum gallium nitride sublayer 109 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this …
FIG. 11 to form the second aluminum nitride sublayer 113 to a thickness of 10 to 25 nm. The epitaxial deposition process 1400 in
FIG. 12 to form the second gallium nitride sublayer 114 to a thickness of 15-35 nm. The alternating epitaxial deposition processing continues in this fashion …
FIG. 17 shows one example, in which an epitaxial deposition process 1700 is performed that deposits the gallium nitride layer 118 to a 40 thickness 143 in the …
FIG. 18. In one example, the process 1800 deposits the aluminum nitride layer 120 to a thickness of about 10 Å at a process temperature of 900-1100° C. At 318, …
FIG. 19. In one example, the process 1900 forms the aluminum gallium nitride layer 121 to a thickness of 10-30 nm at a process temperature of 900-1100° C. As …
FIG. 20 shows one example, in which the silicon nitride cap layer 202 is formed over the aluminum gallium nitride layer 121, for example, to a thickness of …
FIG. 23 is a partial sectional side elevation view of another electronic device with a depletion mode GaN tran- sistor and an enhancement mode GaN transistor …
FIG. 24 is a partial sectional side elevation view of another electronic device with GaN transistors having extrinsically carbon doped buffer layers and a SiN …
FIG. 31 shows one example, in which an epitaxial deposition process 3100 is performed that deposits the gallium nitride layer 10 2318 to a thickness 2343 in …
FIG. 32. In one example, the process 3200 deposits the aluminum nitride layer 2320 to a thickness of about 10 Å at a process 25 temperature of 900-1100° C. At …
FIG. 33. In one example, the process 3300 forms the aluminum gallium nitride layer 2321 to a thickness of 10-30 30 nm at a process temperature of 900-1100° C. …
FIG. 34 shows one example, in which the silicon nitride cap layer 2402 is formed over the aluminum gallium nitride layer 2321, for example, to a thickness of …
third AlGaN:C layer carbon concentration (claim 16) | — | AlGaN:C |
undoped GaN layer carbon concentration (upper bound, description) | — | GaN |
AlN nucleation layer thickness | — | AlN |
first superlattice AlN sublayer thickness | — | AlN |
first superlattice AlGaN sublayer thickness | — | AlGaN |
first superlattice AlGaN sublayer Al concentration | — | AlGaN |
AlGaN interlayer thickness | — | AlGaN |
AlGaN interlayer Al concentration | — | AlGaN |
second superlattice AlN sublayer thickness | — | AlN |
second superlattice GaN sublayer thickness | — | GaN |
carbon doped GaN layer thickness | — | GaN:C |
undoped GaN layer thickness | — | GaN |
Pressure | 20–50 pa | — |
Thickness | 10–25 nm | — |
Thickness | 300–600 nm | — |
Thickness | 10–20 nm | — |
Thickness | 15–35 nm | — |
Thickness | 10–100 nm | — |
Pressure | 30–70 pa | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.1–0.5 µm | — |
Thickness | 10–30 nm | — |
Thickness | 50–200 nm | — |
Thickness | 4–6 µm | — |
Thickness | 5–15 Å | — |
Thickness | 20–25 nm | — |
Thickness | 2–10 nm | — |
Temperature | 1000–1150 °C | — |
Temperature | 900–1100 °C | — |
Temperature | 1000–1100 °C | — |
Thickness | 0.5–3 µm | — |
Temperature | 900–1050 °C | — |
Temperature | 950–1050 °C | — |
Thickness | 2–20 nm | — |
Thickness | 1.4–1.8 µm | — |
Thickness | 1.4–2 µm | — |
Thickness | 1–2.5 µm | — |
