GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

Han Wui Then; Marko Radosavljevic; Pratik Koirala; Nicole K. Thomas; Paul B. Fischer; Adel A. Elsherbini; Tushar Talukdar; Johanna M. Swan; Wilfred Gomes; Robert S. Chau; Beomseok Choi

Patent

Atlas literature

Patent

US 12,148,747 B2

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY

Han Wui Then, Marko Radosavljevic, Pratik Koirala, Nicole K. Thomas et al.

Intel Corporation, Santa Clara, CA (US)·Nov. 19, 2024·US

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 illustrates a cross-sectional view of a transistor having a drain ﬁeld plate, in accordance with embodiments of the present disclosure.

FIG. 2

FIG. 2 illustrates a cross-sectional view of a GaN tran- sistor having a drain ﬁeld plate and having multiple gates, in 35 accordance with embodiments of the …

FIG. 3

FIG. 3F. An anisotropic dry etch process may be used to remove exposed portions of spacers/hard mask layer 330 from horizontal surfaces while leaving …

FIG. 4

FIG. 4 illustrates a cross-sectional view of a high voltage scaled GaN device with multi-gate technology, in accor- dance with an embodiment of the present …

FIG. 5

FIG. 5 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with 45 multi-gate technology, in accordance with …

FIG. 6

FIG. 6 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …

FIG. 7

FIG. 7 illustrates cross-sectional views of various struc- tural options for a high voltage scaled GaN device with multi-gate technology, in accordance with …

FIG. 8

FIGS. 8A-8C illustrate a GaN transistor in accordance with embodiments of the present disclosure.

FIG. 9

FIG. 9 illustrates a GaN transistor having multiple thresh- old voltages in accordance with an embodiment of the present disclosure. 60

FIG. 10

FIG. 10 illustrates a cross-sectional view of a nonplanar or tri-gate GaN transistor having multiple threshold voltages in accordance with embodiments of the …

FIG. 11

FIG. 11D. Recesses 1126 are formed through polarization layer 1106 and into GaN layer 1104. Recess 1126 may enable a subsequently deposited source/drain …

FIG. 12

FIG. 12B illustrates a cross-sectional view of a GaN NMOS bottom gated multi-gate architecture, in accordance with an embodiment of the present disclosure.

FIG. 13

FIGS. 13A-13F illustrate cross-sectional views represent- ing various operations in a method of fabricating a GaN NMOS bottom gated device, in accordance with …

FIG. 14

FIG. 14C illustrates a cross-sectional view of a GaN-on- insulator integrated circuit structure including air gaps and a high aspect ratio (super) copper (Cu) …

FIG. 15

FIG. 15C illustrates a fuse which is in an open state or a “blown” state in accordance with an embodiment of the present disclosure.

FIG. 16

FIG. 16G.

FIG. 17

FIG. 17 illustrates cross-sectional views representing various operations in a process involving monolithic three- dimensional (3D) integration of GaN NMOS and …

FIG. 18

FIGS. 18A and 18B are schematics illustrating GaN 3D IC devices and integration based on 3D best-in-class per- formance building blocks, in accordance with an …

FIG. 19

FIGS. 19A and 19B illustrate cross-sectional views rep- resenting various operations in a process involving three- dimensional (3D) stacking, in accordance …

FIG. 20

FIG. 20 illustrates cross-sectional views representing various operations in a process involving monolithic het- erogeneous integration by three-dimensional …

FIG. 21

FIG. 21 illustrates cross-sectional views representing various operations in a process involving heterogeneous integration of a light-emitting diode (LED) …

FIG. 22

FIG. 22 illustrates a cross-sectional view and associated schematic representing Si CMOS and photonics integration on a same wafer, in accordance with an …

FIG. 23

FIG. 23 illustrates cross-sectional views and associated 10 schematic representing Si CMOS, RF and photonics inte- gration on a same wafer, in accordance with …

FIG. 24

FIG. 24 illustrates a cross-sectional view and associated schematic representing wide bandwidth ﬁlters and RF front end integration on a same wafer, in …

FIG. 25

FIG. 25C illustrates a cross-sectional view of a GaN 25 nanopyramid or micropyramid based LED highlighting cer- tain layers of the LED, in accordance with an …

FIG. 26

FIG. 26 illustrates a cross-sectional view and accompa- nying expanded cross-section of an integrated circuit struc- ture including a silicon-based CMOS layer …

FIG. 27

FIG. 27 illustrates cross-sectional views representing a stacked gate-all-around integrated circuit structure, in accor- dance with an embodiment of the …

FIG. 28

FIG. 28 illustrates cross-sectional views representing a 40 stacked gate-all-around integrated circuit structure having a depopulated channel structure, in …

FIG. 29

FIG. 29 includes a schematic, a cross-sectional view of a semiconductor package, and a circuit diagram representing 45 a power delivery solution, in accordance …

FIG. 30

FIG. 30 illustrates a cross-sectional view of a GaN multi-chip package (MCP), in accordance with an embodi- ment of the present disclosure. 50

FIG. 31

FIG. 31 illustrates a cross-sectional view of a GaN plus Si CMOS package, in accordance with an embodiment of the present disclosure.

FIG. 32

FIG. 32 illustrates a cross-sectional view of a GaN chiplet plus Omnidirectional-Interconnect (ODI) package, in accor- 55 dance with an embodiment of the …

FIG. 33

FIG. 33 illustrates a cross-sectional view of a GaN chiplet and compute complex package, in accordance with an embodiment of the present disclosure.

FIG. 34

FIG. 34 illustrates a cross-sectional view of a semicon- 60 ductor package including an embedded GaN power delivery chiplet bridge, in accordance with an …

FIG. 35

FIG. 35 illustrates a cross-sectional view of a semicon- ductor package including an embedded GaN power delivery 65 chiplet bridge and embedded capacitors, in …

FIG. 36

FIG. 36 illustrates a cross-sectional view of a GaN chiplet base die package, in accordance with an embodiment of the present disclosure.

FIG. 37

FIG. 37 illustrates a cross-sectional view of an integrated circuit structure including an integrated micro chiplet struc- ture, in accordance with an …

FIG. 38

FIG. 38 illustrates cross-sectional views of (a) a structure with a monolithic implementation and (b) a structure with integrated micro-regulators/power gates …

FIG. 39

FIG. 39 illustrates a cross-sectional view of a GaN bottom gated device and associated metal-insulator-metal (MIM) capacitor and interconnect, in accordance …

FIG. 40

FIG. 40 illustrates a cross-sectional view of a structure including BEOL embedded GaN fully integrated voltage regulator (FIVR) micro-chiplets, in accordance …

FIG. 41

FIG. 41 illustrates a cross-sectional view of a GaN bottom gated device and associated FIVR providing a FIVR micro- chiplet, in accordance with an embodiment …

FIG. 42

FIG. 42 illustrates a cross-sectional view of a GaN bottom gated multi-gate architecture with a devices-middle con- struction allowing connections to both …

FIG. 43

FIG. 43 illustrates a computing device in accordance with one implementation of the disclosure.

FIG. 44

FIG. 44 illustrates an interposer that includes one or more embodiments of the disclosure.

FIG. 45

FIG. 45 is an isometric view of a mobile computing platform employing an IC fabricated according to one or more processes described herein or including one or …

FIG. 46

FIG. 47

FIG. 48

FIG. 49

FIG. 50

FIG. 51

FIG. 52

FIG. 53

FIG. 54

FIG. 55

FIG. 55 2. Second gate structure 202 may be recessed into polariza- tion layer 140 so that a 2DEG layer of effect is not formed under second gate structure 202 …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

6 independent · 15 dependent

1
IndependentGaNSi-based CMOSsemiconductor package with GaN+CMOS first IC die and stacked second IC die
A semiconductor package, comprising: 55 a package substrate; a ﬁrst integrated circuit (IC) die coupled to the package substrate, the ﬁrst IC die comprising a GaN device layer and a Si-based CMOS layer, wherein the package substrate is a ceramic package substrate or an organic package substrate; a plurality of interconnects coupled to and extending from the package substrate; and a second IC die over and coupled to the ﬁrst IC die and to the plurality of interconnects, wherein the second IC die is coupled to the ﬁrst IC die by through structure vias of the ﬁrst IC die.
1. 2
  Dependent← claim 1semiconductor package with GaN+CMOS first IC die and stacked second IC die
  The semiconductor package of claim 1, wherein the ﬁrst IC die is coupled to the package substrate by a plurality of second interconnects.
2. 3
  Dependent← claim 1semiconductor package with GaN+CMOS first IC die and stacked second IC die
  The semiconductor package of claim 1, further com-prising: a third IC die coupled to the package substrate.
3. 6
  Dependent← claim 1semiconductor package with GaN+CMOS first IC die and stacked second IC die
  The semiconductor package of claim 1, further com-prising: one or more additional IC dies coupled to a top surface of the ﬁrst IC die.
8
IndependentGaNSi-based CMOSGaN power delivery chipletsemiconductor package with GaN power delivery chiplet embedded in package substrate cavity
A semiconductor package, comprising: a package substrate comprising a plurality of dielectric layers and metallization layers; a cavity within the plurality of dielectric layers and metallization layers of the package substrate; a GaN power delivery chiplet in the cavity of the package substrate, the GaN power delivery chiplet comprising a GaN device layer and a Si-based CMOS layer; a ﬁrst die coupled to the package substrate and to the GaN power delivery chiplet; and a second die coupled to the package substrate and to the GaN power delivery chiplet.
1. 9
  Dependent← claim 8semiconductor package with GaN power delivery chiplet embedded in package substrate cavity
  The semiconductor package of claim 8, wherein the ﬁrst die is a compute complex die, and the second die is a companion die selected from the group consisting of an analog IC or an RF IC.
2. 10
  Dependent← claim 8semiconductor package with GaN power delivery chiplet embedded in package substrate cavity
  The semiconductor package of claim 8, further com-prising: one or more package thin ﬁlm capacitors embedded in the package substrate.
12
Independentintegrated circuit structure with micro chiplet embedded in insulating layer cavity
An integrated circuit structure, comprising: a substrate; a lower back end of line (BEOL) structure above the substrate, the BEOL structure comprising alternating dielectric layers and metallization layers; an insulating layer on the lower BEOL structure; an intermediate metallization layer on the insulating layer; a micro chiplet structure in a cavity in the insulating layer; an upper BEOL structure comprising a dielectric layer, a metallization layer and external contacts, the upper BEOL structure on the intermediate metallization layer.
1. 13
  Dependent← claim 12integrated circuit structure with micro chiplet embedded in insulating layer cavity
  The integrated circuit structure of claim 12, wherein the micro chiplet structure is directly between and electri-cally coupled to the intermediate metallization layer and to the lower BEOL structure.
2. 14
  Dependent← claim 12GaNintegrated circuit structure with micro chiplet embedded in insulating layer cavity
  The integrated circuit structure of claim 12, wherein the micro chiplet structure is a GaN-based structure.
3. 15
  Dependent← claim 12integrated circuit structure with micro chiplet embedded in insulating layer cavity
  The integrated circuit structure of claim 12, wherein the micro chiplet structure comprises metallization layers and a passivation layer.
4. 17
  Dependent← claim 12integrated circuit structure with micro chiplet embedded in insulating layer cavity
  The integrated circuit structure of claim 12, further comprising: through vias extending through the insulating layer.
19
IndependentGaNSi-based CMOSsemiconductor package with GaN+CMOS first IC die and stacked second IC dieGaN power delivery chiplet
A semiconductor package, comprising: a package substrate; a ﬁrst integrated circuit (IC) die coupled to the package substrate, the ﬁrst IC die comprising a GaN device layer and a Si-based CMOS layer; a second IC die coupled to the package substrate; a plurality of second interconnects coupled to and extend-ing from the package substrate; and a third IC die over and coupled to the ﬁrst IC die and to the plurality of second interconnects, wherein the third IC die is coupled to the ﬁrst IC die by through structure vias of the ﬁrst IC die, wherein the plurality of second interconnects is located between the ﬁrst and second IC dies, wherein the ﬁrst IC die comprises a GaN power delivery chiplet, wherein the second IC die comprises a base die chiplet, and wherein the third IC die com-prises a complex compute die.
20
IndependentGaNSi-based CMOSsemiconductor package with GaN+CMOS first IC die and stacked second IC die
A semiconductor package, comprising: a package substrate; a ﬁrst integrated circuit (IC) die coupled to the package substrate, the ﬁrst IC die comprising a GaN device layer and a Si-based CMOS layer; and one or more IC dies coupled to a top surface of the ﬁrst IC die, wherein at least one of the one or more IC dies is an IC die selected from the group consisting of an IO complex die, a graphics die, and a compute cores die.
21
IndependentGaNSi-based CMOSsemiconductor package with GaN+CMOS first IC die and stacked second IC die
A semiconductor package, comprising: a package substrate; a ﬁrst integrated circuit (IC) die coupled to the package substrate, the ﬁrst IC die comprising a GaN device layer and a Si-based CMOS layer, wherein the package substrate is a ceramic package substrate or an organic package substrate; a second IC die coupled to the package substrate; a plurality of interconnects coupled to and extending from the package substrate; and a third IC die over and coupled to the ﬁrst IC die and to the plurality of interconnects, wherein the third IC die is coupled to the ﬁrst IC die by through structure vias of the ﬁrst IC die. ∗ ∗ ∗ ∗ ∗

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor package with GaN+CMOS first IC die and stacked second IC die

second_IC_die_stacked_via_through_structure_viassecond IC die stacked via through structure vias

Si-based CMOSfirst IC die Si CMOS layer

GaNfirst IC die GaN device layer

package_substratepackage substrate

GaN power delivery chiplet

Materials

Materials described outside the worked examples.

Gallium Nitride

GaN

Device Layer Material

Si-based CMOS

Cmos Layer Material

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

fet electrical

Fet Electrical

FIG. 1 illustrates a cross-sectional view of a transistor having a drain ﬁeld plate, in accordance with embodiments of the present disclosure.

Figure references

FIG. 1

fet electrical

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Thickness	10–100 µm	—
—	4.9–5.2 eV

Cited prior art

Patents and literature cited by this patent (applicant and examiner references).

Cited patents · 18

US 9,368,622 B19,368,622 B1 6/2016 Boutros
US 11,342,248 B211,342,248 B2 * 5/2022 Mcknight-Macneil......................examiner
US 11,887,945 B211,887,945 B2 * 1/2024 Zhao....................... H01L 24/48examiner
US 2012/0126287 A12012/0126287 A1 5/2012 Aoki
US 2012/0217544 A12012/0217544 A1 8/2012 Ohki

Why these are connected

Related documents with shared materials, methods, properties, or citations.

GALLIUM NITRIDE (GAN) THREE-DIMENSIONAL INTEGRATED CIRCUIT TECHNOLOGY | Matter42 Literature