Patent
Atlas literature
Patent
US 11,640,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts an example portion of a heterolithic microwave integrated circuit (HMIC) according to a first embodiment;
FIG. 2 depicts an example portion of an HMIC according to a second embodiment;
FIG. 3 depicts an example portion of an HMIC according to a third embodiment;
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
FIG. 5 illustrates circuitry formed for an HMIC;
FIG. 6 illustrates passivation of HMIC circuitry;
FIG. 7 illustrates an example portion of an HMIC sub- strate in which a portion of the wafer’s backside has been removed and a conductive ground plane has been …
FIG. 8B depicts an elevation view of an example package that can contain an HMIC die. Features and advantages of the illustrated embodiments 60 will become …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a first region of the integrated circuit, the first region containing a diode formed on a substrate from a first semiconductor material of a first base elemental com-position that is common with the substrate; 15 a second region of the integrated circuit, the second region containing a transistor comprising gallium-oxide formed over the substrate from a second semiconductor material that is different than the first semiconductor material of the first base elemental composition; and 20 a third region of the integrated circuit containing an electrically-insulating dielectric material.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material extends through the substrate and separates the substrate between the first region and the second region.
The integrated circuit of claim 1, wherein the diode comprises a p-i-n or n-i-p diode.
The integrated circuit of claim 1, further comprising an intrinsic region of the first semiconductor material located between the second semiconductor material and the substrate in the second region.
The integrated circuit of claim 1, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The integrated circuit of claim 1, wherein the transistor comprises a high-electron-mobility transistor.
The integrated circuit of claim 1, further comprising at least a portion of a conductive interconnect formed over the third region.
The integrated circuit of claim 1, further comprising at least a portion of a passive circuit element formed over the third region.
The integrated circuit of claim 1, further comprising a ground plane formed on a back side of the substrate below the first region, second region, and third region.
The integrated circuit of claim 1, further comprising a passivation layer formed over the first region, second region, and third region.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material comprises glass.
The integrated circuit of claim 1, further comprising doped region of the first semiconductor material under the second semiconductor material in the second region.
A method of manufacturing an integrated circuit, the method comprising: forming a first semiconductor device from a first semiconductor material in a first region of a wafer; forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconduc-tor material; forming a second semiconductor device comprising gal-lium-oxide formed from the second semiconductor material; etching a cavity in a third region of the wafer; filling the cavity with an electrically-insulating material; planarizing the electrically-insulating material; and removing a portion of a backside of the wafer to expose the electrically-insulating material.
The method of claim 14, wherein: forming the first semiconductor device comprises forming a diode; and forming the second semiconductor device comprises forming a transistor.
The method of claim 14, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The method of claim 14, wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on the first semiconductor material.
The method of claim 14, further comprising covering the second semiconductor material with a protective layer before filling the cavity.
The method of claim 14, further comprising forming a conductive interconnect over the electrically-insulating material in the third region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
heterolithic microwave integrated circuit (HMIC)
p-i-n or n-i-p diode
Materials described outside the worked examples.
first semiconductor material (silicon-based)
second semiconductor material (gallium-oxide-containing transistor material)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Resistivity | — | Si |
Resistivity | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 97
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,640,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts an example portion of a heterolithic microwave integrated circuit (HMIC) according to a first embodiment;
FIG. 2 depicts an example portion of an HMIC according to a second embodiment;
FIG. 3 depicts an example portion of an HMIC according to a third embodiment;
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
FIG. 5 illustrates circuitry formed for an HMIC;
FIG. 6 illustrates passivation of HMIC circuitry;
FIG. 7 illustrates an example portion of an HMIC sub- strate in which a portion of the wafer’s backside has been removed and a conductive ground plane has been …
FIG. 8B depicts an elevation view of an example package that can contain an HMIC die. Features and advantages of the illustrated embodiments 60 will become …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a first region of the integrated circuit, the first region containing a diode formed on a substrate from a first semiconductor material of a first base elemental com-position that is common with the substrate; 15 a second region of the integrated circuit, the second region containing a transistor comprising gallium-oxide formed over the substrate from a second semiconductor material that is different than the first semiconductor material of the first base elemental composition; and 20 a third region of the integrated circuit containing an electrically-insulating dielectric material.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material extends through the substrate and separates the substrate between the first region and the second region.
The integrated circuit of claim 1, wherein the diode comprises a p-i-n or n-i-p diode.
The integrated circuit of claim 1, further comprising an intrinsic region of the first semiconductor material located between the second semiconductor material and the substrate in the second region.
The integrated circuit of claim 1, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The integrated circuit of claim 1, wherein the transistor comprises a high-electron-mobility transistor.
The integrated circuit of claim 1, further comprising at least a portion of a conductive interconnect formed over the third region.
The integrated circuit of claim 1, further comprising at least a portion of a passive circuit element formed over the third region.
The integrated circuit of claim 1, further comprising a ground plane formed on a back side of the substrate below the first region, second region, and third region.
The integrated circuit of claim 1, further comprising a passivation layer formed over the first region, second region, and third region.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material comprises glass.
The integrated circuit of claim 1, further comprising doped region of the first semiconductor material under the second semiconductor material in the second region.
A method of manufacturing an integrated circuit, the method comprising: forming a first semiconductor device from a first semiconductor material in a first region of a wafer; forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconduc-tor material; forming a second semiconductor device comprising gal-lium-oxide formed from the second semiconductor material; etching a cavity in a third region of the wafer; filling the cavity with an electrically-insulating material; planarizing the electrically-insulating material; and removing a portion of a backside of the wafer to expose the electrically-insulating material.
The method of claim 14, wherein: forming the first semiconductor device comprises forming a diode; and forming the second semiconductor device comprises forming a transistor.
The method of claim 14, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The method of claim 14, wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on the first semiconductor material.
The method of claim 14, further comprising covering the second semiconductor material with a protective layer before filling the cavity.
The method of claim 14, further comprising forming a conductive interconnect over the electrically-insulating material in the third region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
heterolithic microwave integrated circuit (HMIC)
p-i-n or n-i-p diode
Materials described outside the worked examples.
first semiconductor material (silicon-based)
second semiconductor material (gallium-oxide-containing transistor material)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Resistivity | — | Si |
Resistivity | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 97
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,640,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts an example portion of a heterolithic microwave integrated circuit (HMIC) according to a first embodiment;
FIG. 2 depicts an example portion of an HMIC according to a second embodiment;
FIG. 3 depicts an example portion of an HMIC according to a third embodiment;
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
FIG. 5 illustrates circuitry formed for an HMIC;
FIG. 6 illustrates passivation of HMIC circuitry;
FIG. 7 illustrates an example portion of an HMIC sub- strate in which a portion of the wafer’s backside has been removed and a conductive ground plane has been …
FIG. 8B depicts an elevation view of an example package that can contain an HMIC die. Features and advantages of the illustrated embodiments 60 will become …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a first region of the integrated circuit, the first region containing a diode formed on a substrate from a first semiconductor material of a first base elemental com-position that is common with the substrate; 15 a second region of the integrated circuit, the second region containing a transistor comprising gallium-oxide formed over the substrate from a second semiconductor material that is different than the first semiconductor material of the first base elemental composition; and 20 a third region of the integrated circuit containing an electrically-insulating dielectric material.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material extends through the substrate and separates the substrate between the first region and the second region.
The integrated circuit of claim 1, wherein the diode comprises a p-i-n or n-i-p diode.
The integrated circuit of claim 1, further comprising an intrinsic region of the first semiconductor material located between the second semiconductor material and the substrate in the second region.
The integrated circuit of claim 1, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The integrated circuit of claim 1, wherein the transistor comprises a high-electron-mobility transistor.
The integrated circuit of claim 1, further comprising at least a portion of a conductive interconnect formed over the third region.
The integrated circuit of claim 1, further comprising at least a portion of a passive circuit element formed over the third region.
The integrated circuit of claim 1, further comprising a ground plane formed on a back side of the substrate below the first region, second region, and third region.
The integrated circuit of claim 1, further comprising a passivation layer formed over the first region, second region, and third region.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material comprises glass.
The integrated circuit of claim 1, further comprising doped region of the first semiconductor material under the second semiconductor material in the second region.
A method of manufacturing an integrated circuit, the method comprising: forming a first semiconductor device from a first semiconductor material in a first region of a wafer; forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconduc-tor material; forming a second semiconductor device comprising gal-lium-oxide formed from the second semiconductor material; etching a cavity in a third region of the wafer; filling the cavity with an electrically-insulating material; planarizing the electrically-insulating material; and removing a portion of a backside of the wafer to expose the electrically-insulating material.
The method of claim 14, wherein: forming the first semiconductor device comprises forming a diode; and forming the second semiconductor device comprises forming a transistor.
The method of claim 14, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The method of claim 14, wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on the first semiconductor material.
The method of claim 14, further comprising covering the second semiconductor material with a protective layer before filling the cavity.
The method of claim 14, further comprising forming a conductive interconnect over the electrically-insulating material in the third region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
heterolithic microwave integrated circuit (HMIC)
p-i-n or n-i-p diode
Materials described outside the worked examples.
first semiconductor material (silicon-based)
second semiconductor material (gallium-oxide-containing transistor material)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Resistivity | — | Si |
Resistivity | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 97
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,640,960 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts an example portion of a heterolithic microwave integrated circuit (HMIC) according to a first embodiment;
FIG. 2 depicts an example portion of an HMIC according to a second embodiment;
FIG. 3 depicts an example portion of an HMIC according to a third embodiment;
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
FIG. 5 illustrates circuitry formed for an HMIC;
FIG. 6 illustrates passivation of HMIC circuitry;
FIG. 7 illustrates an example portion of an HMIC sub- strate in which a portion of the wafer’s backside has been removed and a conductive ground plane has been …
FIG. 8B depicts an elevation view of an example package that can contain an HMIC die. Features and advantages of the illustrated embodiments 60 will become …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit, comprising: a first region of the integrated circuit, the first region containing a diode formed on a substrate from a first semiconductor material of a first base elemental com-position that is common with the substrate; 15 a second region of the integrated circuit, the second region containing a transistor comprising gallium-oxide formed over the substrate from a second semiconductor material that is different than the first semiconductor material of the first base elemental composition; and 20 a third region of the integrated circuit containing an electrically-insulating dielectric material.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material extends through the substrate and separates the substrate between the first region and the second region.
The integrated circuit of claim 1, wherein the diode comprises a p-i-n or n-i-p diode.
The integrated circuit of claim 1, further comprising an intrinsic region of the first semiconductor material located between the second semiconductor material and the substrate in the second region.
The integrated circuit of claim 1, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The integrated circuit of claim 1, wherein the transistor comprises a high-electron-mobility transistor.
The integrated circuit of claim 1, further comprising at least a portion of a conductive interconnect formed over the third region.
The integrated circuit of claim 1, further comprising at least a portion of a passive circuit element formed over the third region.
The integrated circuit of claim 1, further comprising a ground plane formed on a back side of the substrate below the first region, second region, and third region.
The integrated circuit of claim 1, further comprising a passivation layer formed over the first region, second region, and third region.
The integrated circuit of claim 1, wherein the electri-cally-insulating dielectric material comprises glass.
The integrated circuit of claim 1, further comprising doped region of the first semiconductor material under the second semiconductor material in the second region.
A method of manufacturing an integrated circuit, the method comprising: forming a first semiconductor device from a first semiconductor material in a first region of a wafer; forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconduc-tor material; forming a second semiconductor device comprising gal-lium-oxide formed from the second semiconductor material; etching a cavity in a third region of the wafer; filling the cavity with an electrically-insulating material; planarizing the electrically-insulating material; and removing a portion of a backside of the wafer to expose the electrically-insulating material.
The method of claim 14, wherein: forming the first semiconductor device comprises forming a diode; and forming the second semiconductor device comprises forming a transistor.
The method of claim 14, wherein: the first semiconductor material has a base elemental composition of silicon; and the second semiconductor material comprises gallium-nitride material.
The method of claim 14, wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on the first semiconductor material.
The method of claim 14, further comprising covering the second semiconductor material with a protective layer before filling the cavity.
The method of claim 14, further comprising forming a conductive interconnect over the electrically-insulating material in the third region. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
heterolithic microwave integrated circuit (HMIC)
p-i-n or n-i-p diode
Materials described outside the worked examples.
first semiconductor material (silicon-based)
second semiconductor material (gallium-oxide-containing transistor material)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 4-4C illustrates formation of one or more epitaxial layers of a different semiconductor material on a highly doped region of an intrinsic semiconductor …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Resistivity | — | Si |
Resistivity | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 97
Related documents with shared materials, methods, properties, or citations.
high-electron-mobility transistor (HEMT)
electrically-insulating dielectric material
silicon
Si
gallium-nitride material
GaN
glass
Doping Density | — | Si |
Thickness | 1.5–4 µm | — |
Thickness | 50–300 nm | — |
Thickness | 120–200 µm | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Pressure | 0.5–3 Torr | — |
Duration | 10–120 s | — |
Thickness | 50–200 µm | — |
Thickness | 10–50 µm | — |
Thickness | 1.5–6 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≥ 50 µm | — |
Cited non-patent literature · 4
GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE
high-electron-mobility transistor (HEMT)
electrically-insulating dielectric material
silicon
Si
gallium-nitride material
GaN
glass
Doping Density | — | Si |
Thickness | 1.5–4 µm | — |
Thickness | 50–300 nm | — |
Thickness | 120–200 µm | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Pressure | 0.5–3 Torr | — |
Duration | 10–120 s | — |
Thickness | 50–200 µm | — |
Thickness | 10–50 µm | — |
Thickness | 1.5–6 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≥ 50 µm | — |
Cited non-patent literature · 4
GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE
high-electron-mobility transistor (HEMT)
electrically-insulating dielectric material
silicon
Si
gallium-nitride material
GaN
glass
Doping Density | — | Si |
Thickness | 1.5–4 µm | — |
Thickness | 50–300 nm | — |
Thickness | 120–200 µm | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Pressure | 0.5–3 Torr | — |
Duration | 10–120 s | — |
Thickness | 50–200 µm | — |
Thickness | 10–50 µm | — |
Thickness | 1.5–6 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≥ 50 µm | — |
Cited non-patent literature · 4
GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE
high-electron-mobility transistor (HEMT)
electrically-insulating dielectric material
silicon
Si
gallium-nitride material
GaN
glass
Doping Density | — | Si |
Thickness | 1.5–4 µm | — |
Thickness | 50–300 nm | — |
Thickness | 120–200 µm | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Pressure | 0.5–3 Torr | — |
Duration | 10–120 s | — |
Thickness | 50–200 µm | — |
Thickness | 10–50 µm | — |
Thickness | 1.5–6 µm | — |
Thickness | ≤ 10 µm | — |
Thickness | ≥ 50 µm | — |
Cited non-patent literature · 4
