Patent
Atlas literature
Patent
US 12,581,728 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a portion of an example integrated 30 circuit according to various examples described herein.
FIG. 2 illustrates a portion of another example integrated circuit according to various examples described herein.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
FIG. 4A illustrates a plan view of an example package for a semiconductor die including an integrated circuit accord- ing to various examples described herein.
FIG. 30 3-11. The process can also include depositing a conductive film, to form the ground plane 165, on at least a portion of the backside of the …
FIGS. 55 4A and 4B can be suitable for an amplifier device. Other package shapes and form factors can be used for amplifiers and other devices. The die can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit, the method comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; forming a passive component over the insulating material in the third region of the integrated circuit; and B₂ grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure.
The method of claim 1, wherein: the first semiconductor structure comprises an island of gallium nitride material formed over a semiconductor substrate; and the first integrated device is formed in the island of gallium nitride material.
The method of claim 1, wherein the insulating material comprises glass.
The method of claim 1, wherein: the first semiconductor structure comprises a first island of gallium nitride material formed over a semiconduc-tor substrate; the first integrated device is formed in the first island of gallium nitride material; the second semiconductor structure comprises a second island of gallium nitride material formed over the semiconductor substrate; and the second integrated device is formed in the second island of gallium nitride material.
The method of claim 1, further comprising encapsu-lating the integrated circuit with a passivation layer.
The method of claim 1, further comprising depositing a conductive film over a back side of a semiconductor substrate of the integrated circuit.
The method of claim 1, further comprising, after the grinding, forming a ground plane over the back side of the semiconductor substrate.
The method of claim 1, further comprising forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit before the etching.
A method of forming an integrated circuit, comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein: the passive component comprises a network of passive components; and the network of passive components comprises at least one capacitor and at least one inductor.
A method of forming an integrated circuit, compris-ing: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein, after the etching, the integrated circuit comprises a semiconductor pedestal in the third region.
The method of claim 13, further comprising deposit-ing a conductive film over the semiconductor pedestal after the etching.
A method of forming an integrated circuit, the method comprising: forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between a first region and a second region of the integrated circuit; B₂ filling the cavity with an insulating material; forming a first integrated device over a first semiconduc-tor structure in the first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in the second region of the inte-grated circuit; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and forming a ground plane over the back side of the semiconductor substrate.
The method of claim 17, wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.
The method of claim 17, wherein after the etching, the integrated circuit comprises a semiconductor pedestal in the third region, and the method further comprises: depositing a conductive film over the semiconductor pedestal; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.
Layer stacks claimed or described, ordered top of device to substrate.
microwave integrated circuit (MMIC) with GaN devices and passive components over insulating region
Materials described outside the worked examples.
insulating material
gallium nitride material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 121
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,581,728 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a portion of an example integrated 30 circuit according to various examples described herein.
FIG. 2 illustrates a portion of another example integrated circuit according to various examples described herein.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
FIG. 4A illustrates a plan view of an example package for a semiconductor die including an integrated circuit accord- ing to various examples described herein.
FIG. 30 3-11. The process can also include depositing a conductive film, to form the ground plane 165, on at least a portion of the backside of the …
FIGS. 55 4A and 4B can be suitable for an amplifier device. Other package shapes and form factors can be used for amplifiers and other devices. The die can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit, the method comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; forming a passive component over the insulating material in the third region of the integrated circuit; and B₂ grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure.
The method of claim 1, wherein: the first semiconductor structure comprises an island of gallium nitride material formed over a semiconductor substrate; and the first integrated device is formed in the island of gallium nitride material.
The method of claim 1, wherein the insulating material comprises glass.
The method of claim 1, wherein: the first semiconductor structure comprises a first island of gallium nitride material formed over a semiconduc-tor substrate; the first integrated device is formed in the first island of gallium nitride material; the second semiconductor structure comprises a second island of gallium nitride material formed over the semiconductor substrate; and the second integrated device is formed in the second island of gallium nitride material.
The method of claim 1, further comprising encapsu-lating the integrated circuit with a passivation layer.
The method of claim 1, further comprising depositing a conductive film over a back side of a semiconductor substrate of the integrated circuit.
The method of claim 1, further comprising, after the grinding, forming a ground plane over the back side of the semiconductor substrate.
The method of claim 1, further comprising forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit before the etching.
A method of forming an integrated circuit, comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein: the passive component comprises a network of passive components; and the network of passive components comprises at least one capacitor and at least one inductor.
A method of forming an integrated circuit, compris-ing: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein, after the etching, the integrated circuit comprises a semiconductor pedestal in the third region.
The method of claim 13, further comprising deposit-ing a conductive film over the semiconductor pedestal after the etching.
A method of forming an integrated circuit, the method comprising: forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between a first region and a second region of the integrated circuit; B₂ filling the cavity with an insulating material; forming a first integrated device over a first semiconduc-tor structure in the first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in the second region of the inte-grated circuit; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and forming a ground plane over the back side of the semiconductor substrate.
The method of claim 17, wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.
The method of claim 17, wherein after the etching, the integrated circuit comprises a semiconductor pedestal in the third region, and the method further comprises: depositing a conductive film over the semiconductor pedestal; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.
Layer stacks claimed or described, ordered top of device to substrate.
microwave integrated circuit (MMIC) with GaN devices and passive components over insulating region
Materials described outside the worked examples.
insulating material
gallium nitride material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 121
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,581,728 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a portion of an example integrated 30 circuit according to various examples described herein.
FIG. 2 illustrates a portion of another example integrated circuit according to various examples described herein.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
FIG. 4A illustrates a plan view of an example package for a semiconductor die including an integrated circuit accord- ing to various examples described herein.
FIG. 30 3-11. The process can also include depositing a conductive film, to form the ground plane 165, on at least a portion of the backside of the …
FIGS. 55 4A and 4B can be suitable for an amplifier device. Other package shapes and form factors can be used for amplifiers and other devices. The die can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit, the method comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; forming a passive component over the insulating material in the third region of the integrated circuit; and B₂ grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure.
The method of claim 1, wherein: the first semiconductor structure comprises an island of gallium nitride material formed over a semiconductor substrate; and the first integrated device is formed in the island of gallium nitride material.
The method of claim 1, wherein the insulating material comprises glass.
The method of claim 1, wherein: the first semiconductor structure comprises a first island of gallium nitride material formed over a semiconduc-tor substrate; the first integrated device is formed in the first island of gallium nitride material; the second semiconductor structure comprises a second island of gallium nitride material formed over the semiconductor substrate; and the second integrated device is formed in the second island of gallium nitride material.
The method of claim 1, further comprising encapsu-lating the integrated circuit with a passivation layer.
The method of claim 1, further comprising depositing a conductive film over a back side of a semiconductor substrate of the integrated circuit.
The method of claim 1, further comprising, after the grinding, forming a ground plane over the back side of the semiconductor substrate.
The method of claim 1, further comprising forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit before the etching.
A method of forming an integrated circuit, comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein: the passive component comprises a network of passive components; and the network of passive components comprises at least one capacitor and at least one inductor.
A method of forming an integrated circuit, compris-ing: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein, after the etching, the integrated circuit comprises a semiconductor pedestal in the third region.
The method of claim 13, further comprising deposit-ing a conductive film over the semiconductor pedestal after the etching.
A method of forming an integrated circuit, the method comprising: forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between a first region and a second region of the integrated circuit; B₂ filling the cavity with an insulating material; forming a first integrated device over a first semiconduc-tor structure in the first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in the second region of the inte-grated circuit; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and forming a ground plane over the back side of the semiconductor substrate.
The method of claim 17, wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.
The method of claim 17, wherein after the etching, the integrated circuit comprises a semiconductor pedestal in the third region, and the method further comprises: depositing a conductive film over the semiconductor pedestal; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.
Layer stacks claimed or described, ordered top of device to substrate.
microwave integrated circuit (MMIC) with GaN devices and passive components over insulating region
Materials described outside the worked examples.
insulating material
gallium nitride material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 121
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,581,728 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a portion of an example integrated 30 circuit according to various examples described herein.
FIG. 2 illustrates a portion of another example integrated circuit according to various examples described herein.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
FIG. 4A illustrates a plan view of an example package for a semiconductor die including an integrated circuit accord- ing to various examples described herein.
FIG. 30 3-11. The process can also include depositing a conductive film, to form the ground plane 165, on at least a portion of the backside of the …
FIGS. 55 4A and 4B can be suitable for an amplifier device. Other package shapes and form factors can be used for amplifiers and other devices. The die can be …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit, the method comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; forming a passive component over the insulating material in the third region of the integrated circuit; and B₂ grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure.
The method of claim 1, wherein: the first semiconductor structure comprises an island of gallium nitride material formed over a semiconductor substrate; and the first integrated device is formed in the island of gallium nitride material.
The method of claim 1, wherein the insulating material comprises glass.
The method of claim 1, wherein: the first semiconductor structure comprises a first island of gallium nitride material formed over a semiconduc-tor substrate; the first integrated device is formed in the first island of gallium nitride material; the second semiconductor structure comprises a second island of gallium nitride material formed over the semiconductor substrate; and the second integrated device is formed in the second island of gallium nitride material.
The method of claim 1, further comprising encapsu-lating the integrated circuit with a passivation layer.
The method of claim 1, further comprising depositing a conductive film over a back side of a semiconductor substrate of the integrated circuit.
The method of claim 1, further comprising, after the grinding, forming a ground plane over the back side of the semiconductor substrate.
The method of claim 1, further comprising forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit before the etching.
A method of forming an integrated circuit, comprising: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein: the passive component comprises a network of passive components; and the network of passive components comprises at least one capacitor and at least one inductor.
A method of forming an integrated circuit, compris-ing: forming a first integrated device over a first semiconduc-tor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein, after the etching, the integrated circuit comprises a semiconductor pedestal in the third region.
The method of claim 13, further comprising deposit-ing a conductive film over the semiconductor pedestal after the etching.
A method of forming an integrated circuit, the method comprising: forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between a first region and a second region of the integrated circuit; B₂ filling the cavity with an insulating material; forming a first integrated device over a first semiconduc-tor structure in the first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in the second region of the inte-grated circuit; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and forming a ground plane over the back side of the semiconductor substrate.
The method of claim 17, wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.
The method of claim 17, wherein after the etching, the integrated circuit comprises a semiconductor pedestal in the third region, and the method further comprises: depositing a conductive film over the semiconductor pedestal; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.
Layer stacks claimed or described, ordered top of device to substrate.
microwave integrated circuit (MMIC) with GaN devices and passive components over insulating region
Materials described outside the worked examples.
insulating material
gallium nitride material
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3-1 illustrates an example structure and patterned resist associated with a method of manufacturing an inte- 35 grated circuit according to various …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 121
Related documents with shared materials, methods, properties, or citations.
semiconductor substrate
glass
| — |
Pressure | 150–250 mTorr | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Thickness | 1.5–50 µm | — |
Thickness | 100–200 µm | — |
Thickness | 5–200 µm | — |
Thickness | 10–250 nm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 4
semiconductor substrate
glass
| — |
Pressure | 150–250 mTorr | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Thickness | 1.5–50 µm | — |
Thickness | 100–200 µm | — |
Thickness | 5–200 µm | — |
Thickness | 10–250 nm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 4
semiconductor substrate
glass
| — |
Pressure | 150–250 mTorr | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Thickness | 1.5–50 µm | — |
Thickness | 100–200 µm | — |
Thickness | 5–200 µm | — |
Thickness | 10–250 nm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 4
semiconductor substrate
glass
| — |
Pressure | 150–250 mTorr | — |
Thickness | 250–750 µm | — |
Pressure | 10–50 mTorr | — |
Temperature | 700–900 °C | — |
Thickness | 1.5–50 µm | — |
Thickness | 100–200 µm | — |
Thickness | 5–200 µm | — |
Thickness | 10–250 nm | — |
Thickness | ≥ 5 µm | — |
Thickness | ≥ 10 µm | — |
Cited non-patent literature · 4
