Patent
US 10,998,188GALLIUM NITRIDE LAMINATED SUBSTRATE AND SEMICONDUCTOR DEVICE
Tomoyoshi MISHIMA
US
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Figure 1 is a schematic cross-sectional view illustrating a gallium nitride laminated substrate according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride laminated substrate comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the intermediate level layer is 5.0 x 10 19 cm⁻³ or more.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the intermediate level layer is 5 nm or more and 50 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein an avalanche breakdown voltage is VA when the breakdown occurs due to the avalanche phenomenon, and a punchthrough breakdown voltage is V P when the breakdown occurs due to the punchthrough phenomenon, and in this case, VA VP is established when a temperature is lower than a predetermined threshold value, and the punchthrough phenomenon is induced due to the occurrence of the avalanche phenomenon, or the punchthrough phenomenon occurs simultaneously with the avalanche phenomenon, and VA > V P is established when the temperature is a predetermined threshold value or more, and the punchthrough phenomenon occurs before the avalanche phenomenon, and therefore the breakdown occurs due to the punchthrough phenomenon before the breakdown due to the avalanche phenomenon.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the p-type gallium nitride layer is 1.0 x 10 17 cm- 3 or more and 1.0 x 10 18 cm⁻³ or less.
The gallium nitride laminated substrate according to claim 1, wherein the p-type gallium nitride layer is configured such that a p-type impurity concentration becomes higher toward the intermediate level layer in the thickness direction.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the p-type gallium nitride layer is 700 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level is formed by defects having been introduced into the gallium nitride by the p-type impurity.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level layer is configured such that the defect forming the intermediate level is uniform in a plane.
A semiconductor device comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
A semiconductor device including a gallium nitride laminated substrate having a pn-junction, and having a durability that prevents an electrical breakdown from occurring even if the reverse bias voltage which causes a breakdown is repeatedly applied, wherein the breakdown means a case where a current with a current value of 1 pA or more is generated by applying a reverse bias voltage to the pn-junction.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride laminated substrate
semiconductor device
Materials described outside the worked examples.
n-type gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type impurity concentration in intermediate level layer | ≥ 50000000000000000000 cm⁻³ | GaN |
thickness of intermediate level layer | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,188Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic cross-sectional view illustrating a gallium nitride laminated substrate according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride laminated substrate comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the intermediate level layer is 5.0 x 10 19 cm⁻³ or more.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the intermediate level layer is 5 nm or more and 50 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein an avalanche breakdown voltage is VA when the breakdown occurs due to the avalanche phenomenon, and a punchthrough breakdown voltage is V P when the breakdown occurs due to the punchthrough phenomenon, and in this case, VA VP is established when a temperature is lower than a predetermined threshold value, and the punchthrough phenomenon is induced due to the occurrence of the avalanche phenomenon, or the punchthrough phenomenon occurs simultaneously with the avalanche phenomenon, and VA > V P is established when the temperature is a predetermined threshold value or more, and the punchthrough phenomenon occurs before the avalanche phenomenon, and therefore the breakdown occurs due to the punchthrough phenomenon before the breakdown due to the avalanche phenomenon.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the p-type gallium nitride layer is 1.0 x 10 17 cm- 3 or more and 1.0 x 10 18 cm⁻³ or less.
The gallium nitride laminated substrate according to claim 1, wherein the p-type gallium nitride layer is configured such that a p-type impurity concentration becomes higher toward the intermediate level layer in the thickness direction.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the p-type gallium nitride layer is 700 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level is formed by defects having been introduced into the gallium nitride by the p-type impurity.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level layer is configured such that the defect forming the intermediate level is uniform in a plane.
A semiconductor device comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
A semiconductor device including a gallium nitride laminated substrate having a pn-junction, and having a durability that prevents an electrical breakdown from occurring even if the reverse bias voltage which causes a breakdown is repeatedly applied, wherein the breakdown means a case where a current with a current value of 1 pA or more is generated by applying a reverse bias voltage to the pn-junction.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride laminated substrate
semiconductor device
Materials described outside the worked examples.
n-type gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type impurity concentration in intermediate level layer | ≥ 50000000000000000000 cm⁻³ | GaN |
thickness of intermediate level layer | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,188Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic cross-sectional view illustrating a gallium nitride laminated substrate according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride laminated substrate comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the intermediate level layer is 5.0 x 10 19 cm⁻³ or more.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the intermediate level layer is 5 nm or more and 50 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein an avalanche breakdown voltage is VA when the breakdown occurs due to the avalanche phenomenon, and a punchthrough breakdown voltage is V P when the breakdown occurs due to the punchthrough phenomenon, and in this case, VA VP is established when a temperature is lower than a predetermined threshold value, and the punchthrough phenomenon is induced due to the occurrence of the avalanche phenomenon, or the punchthrough phenomenon occurs simultaneously with the avalanche phenomenon, and VA > V P is established when the temperature is a predetermined threshold value or more, and the punchthrough phenomenon occurs before the avalanche phenomenon, and therefore the breakdown occurs due to the punchthrough phenomenon before the breakdown due to the avalanche phenomenon.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the p-type gallium nitride layer is 1.0 x 10 17 cm- 3 or more and 1.0 x 10 18 cm⁻³ or less.
The gallium nitride laminated substrate according to claim 1, wherein the p-type gallium nitride layer is configured such that a p-type impurity concentration becomes higher toward the intermediate level layer in the thickness direction.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the p-type gallium nitride layer is 700 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level is formed by defects having been introduced into the gallium nitride by the p-type impurity.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level layer is configured such that the defect forming the intermediate level is uniform in a plane.
A semiconductor device comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
A semiconductor device including a gallium nitride laminated substrate having a pn-junction, and having a durability that prevents an electrical breakdown from occurring even if the reverse bias voltage which causes a breakdown is repeatedly applied, wherein the breakdown means a case where a current with a current value of 1 pA or more is generated by applying a reverse bias voltage to the pn-junction.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride laminated substrate
semiconductor device
Materials described outside the worked examples.
n-type gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type impurity concentration in intermediate level layer | ≥ 50000000000000000000 cm⁻³ | GaN |
thickness of intermediate level layer | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,998,188Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a schematic cross-sectional view illustrating a gallium nitride laminated substrate according to an embodiment of the present invention.
Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A gallium nitride laminated substrate comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the intermediate level layer is 5.0 x 10 19 cm⁻³ or more.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the intermediate level layer is 5 nm or more and 50 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein an avalanche breakdown voltage is VA when the breakdown occurs due to the avalanche phenomenon, and a punchthrough breakdown voltage is V P when the breakdown occurs due to the punchthrough phenomenon, and in this case, VA VP is established when a temperature is lower than a predetermined threshold value, and the punchthrough phenomenon is induced due to the occurrence of the avalanche phenomenon, or the punchthrough phenomenon occurs simultaneously with the avalanche phenomenon, and VA > V P is established when the temperature is a predetermined threshold value or more, and the punchthrough phenomenon occurs before the avalanche phenomenon, and therefore the breakdown occurs due to the punchthrough phenomenon before the breakdown due to the avalanche phenomenon.
The gallium nitride laminated substrate according to claim 1, wherein the p-type impurity concentration in the p-type gallium nitride layer is 1.0 x 10 17 cm- 3 or more and 1.0 x 10 18 cm⁻³ or less.
The gallium nitride laminated substrate according to claim 1, wherein the p-type gallium nitride layer is configured such that a p-type impurity concentration becomes higher toward the intermediate level layer in the thickness direction.
The gallium nitride laminated substrate according to claim 1, wherein a thickness of the p-type gallium nitride layer is 700 nm or less.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level is formed by defects having been introduced into the gallium nitride by the p-type impurity.
The gallium nitride laminated substrate according to claim 1, wherein the intermediate level layer is configured such that the defect forming the intermediate level is uniform in a plane.
A semiconductor device comprising: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.
A semiconductor device including a gallium nitride laminated substrate having a pn-junction, and having a durability that prevents an electrical breakdown from occurring even if the reverse bias voltage which causes a breakdown is repeatedly applied, wherein the breakdown means a case where a current with a current value of 1 pA or more is generated by applying a reverse bias voltage to the pn-junction.
Layer stacks claimed or described, ordered top of device to substrate.
gallium nitride laminated substrate
semiconductor device
Materials described outside the worked examples.
n-type gallium nitride layer
GaN
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 3 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Example 1.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
p-type impurity concentration in intermediate level layer | ≥ 50000000000000000000 cm⁻³ | GaN |
thickness of intermediate level layer | 5–50 nm |
Related documents with shared materials, methods, properties, or citations.
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
durability tends to be low when a reverse voltage is repeatedly applied. The inventors of the present invention have considered a unique problem of such a GaN laminate substrate and focused on an effect of a current (hereinafter referred to as punchthrough curr
p-type impurity concentration in p-type GaN layer | 100000000000000000–1000000000000000000 cm⁻³ | GaN |
thickness of p-type GaN layer | ≤ 700 nm | GaN |
n-type impurity concentration in n-type GaN layer | — | GaN |
thickness of n-type GaN layer | 10000–40000 nm | GaN |
thickness of GaN substrate | 0.4–1 mm | GaN |
Pressure | 0.02–0.08 MPa | — |
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
durability tends to be low when a reverse voltage is repeatedly applied. The inventors of the present invention have considered a unique problem of such a GaN laminate substrate and focused on an effect of a current (hereinafter referred to as punchthrough curr
p-type impurity concentration in p-type GaN layer | 100000000000000000–1000000000000000000 cm⁻³ | GaN |
thickness of p-type GaN layer | ≤ 700 nm | GaN |
n-type impurity concentration in n-type GaN layer | — | GaN |
thickness of n-type GaN layer | 10000–40000 nm | GaN |
thickness of GaN substrate | 0.4–1 mm | GaN |
Pressure | 0.02–0.08 MPa | — |
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
durability tends to be low when a reverse voltage is repeatedly applied. The inventors of the present invention have considered a unique problem of such a GaN laminate substrate and focused on an effect of a current (hereinafter referred to as punchthrough curr
p-type impurity concentration in p-type GaN layer | 100000000000000000–1000000000000000000 cm⁻³ | GaN |
thickness of p-type GaN layer | ≤ 700 nm | GaN |
n-type impurity concentration in n-type GaN layer | — | GaN |
thickness of n-type GaN layer | 10000–40000 nm | GaN |
thickness of GaN substrate | 0.4–1 mm | GaN |
Pressure | 0.02–0.08 MPa | — |
Figure 4 illustrates a temperature dependence of IV characteristics when a reverse bias is applied to a semiconductor device according to Example I while varying a temperature.
Figure 5 illustrates IV characteristics when a reverse bias is applied to a semiconductor device according to Comparative Example 1.
durability tends to be low when a reverse voltage is repeatedly applied. The inventors of the present invention have considered a unique problem of such a GaN laminate substrate and focused on an effect of a current (hereinafter referred to as punchthrough curr
p-type impurity concentration in p-type GaN layer | 100000000000000000–1000000000000000000 cm⁻³ | GaN |
thickness of p-type GaN layer | ≤ 700 nm | GaN |
n-type impurity concentration in n-type GaN layer | — | GaN |
thickness of n-type GaN layer | 10000–40000 nm | GaN |
thickness of GaN substrate | 0.4–1 mm | GaN |
Pressure | 0.02–0.08 MPa | — |