Patent
US 9,391,179VERTICAL GaN JFET WITH LOW GATE-DRAIN CAPACITANCE
Donald R. Disney
US
Copyright © 2026 Matter42. All rights reserved.
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US 9,391,179Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In a power switching application, it is generally preferable to minimize the value of the gate-drain capacitance Cgd, becau s e this capacitance is …
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: 2 providing a I II -nitride substrate; 3 forming a channel region and a drift region, wherein: 4 the drift region and the channel region comprise a I II -nitride material of a 5 first conductivity type, and 6 the drift region is coupled to the I II -nitride substrate; 7 forming a source region coupled to the channel region; 8 forming a gate region coupled to the channel region, wherein the gate region 9 comprises a I II -nitride material of a second conductivity type; 10 forming a source-coupled region coupled to the drift region; and 11 electrically connecting the source-coupled region to the source region.
1 2. The method of claim 1 wherein an area defined by a junction of the gate 2 region and the drift region is smaller than an area defined by a junction of the source-coupled 3 region and the drift region.
1 3. The method of claim 1 wherein forming either or both of the channel 2 region or the drift region comprises: 3 forming a I II -nitride epitaxial layer coupled to the I II -nitride substrate; and 4 removing at least a portion of the I II -nitride epitaxial layer.
1 4. The method of claim 1 f u rther comprising forming an edge termination 2 structure surrounding the gate region, the source-coupled region, and the channel region.
1 5. The method of claim 1 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 6. The method of claim 1 f u rther comprising forming a p-ohmic contact layer 2 electrically coupled to the source-coupled region.
1 9. The method of claim 1 wherein electrically connecting the source-coupled 2 region to the source region comprises forming at least one metal layer coupled to the source- 3 coupled region and the source region.
1 10. The method of claim 1 wherein the drift region and the channel region are 2 formed from a single I II -nitride epitaxial layer.
1 11. The method of claim 1 further comprising forming a source electrode such 2 that a dielectric layer is disposed between at least a portion of the source region and at least a 3 portion of the source electrode.
1 12. A method comprising: 2 providing a I II -nitride substrate; 3 forming a first I II -nitride epitaxial layer coupled to the I II -nitride substrate; 4 forming a source region coupled to the first I II -nitride epitaxial layer; 5 removing at least a portion of the first I II -nitride epitaxial layer and at least a 6 portion of the source region to form a channel region, a drift region, and a separation region; 7 forming a second I II -nitride epitaxial layer coupled to the channel region and the 8 drift region, the second I II -nitride epitaxial layer comprising a gate region and a source-coupled 9 region, wherein the gate region and the source-coupled region are separated by the separation 10 region; and 11 forming a metal structure electrically connecting the source region with the 12 source-coupled region.
21 1 13. The method of claim 12 further comprising forming an Ohmic metal 2 contact coupled to the source-coupled region, wherein the metal structure is coupled to the 3 Ohmic metal contact.
1 14. The method of claim 12 further comprising: 2 forming a dielectric layer; and 3 forming a second metal structure; 4 wherein: 5 the second metal structure is electrically connected to the gate region; and 6 the dielectric layer is disposed between at least a portion of the source- 7 coupled region and at least a portion of the second metal structure.
1 15. The method of claim 12 wherein: 2 the gate region is coupled to the drift region at a first area of a surface of the drift 3 region; and 4 the source-coupled region is coupled to the drift region at a second area of the 5 surface of the drift region, the second area being larger than the first area.
1 16. The method of claim 12 further comprising forming an edge termination 2 structure surrounding the source-coupled region, the gate region, and the channel region..
1 17. The method of claim 12 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 18. The method of claim 12 further comprising a drain electrode electrically 2 coupled to the I II -nitride substrate. 22
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET with low gate-drain capacitance
Materials described outside the worked examples.
III-nitride substrate
III-nitride material of first conductivity type
III-nitride material of second conductivity type
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+ III-nitride substrate dopant concentration range | 100000000000000000–10000000000000000000 cm⁻³ | GaN |
n- III-nitride drift region dopant concentration range | 100000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,391,179Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In a power switching application, it is generally preferable to minimize the value of the gate-drain capacitance Cgd, becau s e this capacitance is …
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: 2 providing a I II -nitride substrate; 3 forming a channel region and a drift region, wherein: 4 the drift region and the channel region comprise a I II -nitride material of a 5 first conductivity type, and 6 the drift region is coupled to the I II -nitride substrate; 7 forming a source region coupled to the channel region; 8 forming a gate region coupled to the channel region, wherein the gate region 9 comprises a I II -nitride material of a second conductivity type; 10 forming a source-coupled region coupled to the drift region; and 11 electrically connecting the source-coupled region to the source region.
1 2. The method of claim 1 wherein an area defined by a junction of the gate 2 region and the drift region is smaller than an area defined by a junction of the source-coupled 3 region and the drift region.
1 3. The method of claim 1 wherein forming either or both of the channel 2 region or the drift region comprises: 3 forming a I II -nitride epitaxial layer coupled to the I II -nitride substrate; and 4 removing at least a portion of the I II -nitride epitaxial layer.
1 4. The method of claim 1 f u rther comprising forming an edge termination 2 structure surrounding the gate region, the source-coupled region, and the channel region.
1 5. The method of claim 1 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 6. The method of claim 1 f u rther comprising forming a p-ohmic contact layer 2 electrically coupled to the source-coupled region.
1 9. The method of claim 1 wherein electrically connecting the source-coupled 2 region to the source region comprises forming at least one metal layer coupled to the source- 3 coupled region and the source region.
1 10. The method of claim 1 wherein the drift region and the channel region are 2 formed from a single I II -nitride epitaxial layer.
1 11. The method of claim 1 further comprising forming a source electrode such 2 that a dielectric layer is disposed between at least a portion of the source region and at least a 3 portion of the source electrode.
1 12. A method comprising: 2 providing a I II -nitride substrate; 3 forming a first I II -nitride epitaxial layer coupled to the I II -nitride substrate; 4 forming a source region coupled to the first I II -nitride epitaxial layer; 5 removing at least a portion of the first I II -nitride epitaxial layer and at least a 6 portion of the source region to form a channel region, a drift region, and a separation region; 7 forming a second I II -nitride epitaxial layer coupled to the channel region and the 8 drift region, the second I II -nitride epitaxial layer comprising a gate region and a source-coupled 9 region, wherein the gate region and the source-coupled region are separated by the separation 10 region; and 11 forming a metal structure electrically connecting the source region with the 12 source-coupled region.
21 1 13. The method of claim 12 further comprising forming an Ohmic metal 2 contact coupled to the source-coupled region, wherein the metal structure is coupled to the 3 Ohmic metal contact.
1 14. The method of claim 12 further comprising: 2 forming a dielectric layer; and 3 forming a second metal structure; 4 wherein: 5 the second metal structure is electrically connected to the gate region; and 6 the dielectric layer is disposed between at least a portion of the source- 7 coupled region and at least a portion of the second metal structure.
1 15. The method of claim 12 wherein: 2 the gate region is coupled to the drift region at a first area of a surface of the drift 3 region; and 4 the source-coupled region is coupled to the drift region at a second area of the 5 surface of the drift region, the second area being larger than the first area.
1 16. The method of claim 12 further comprising forming an edge termination 2 structure surrounding the source-coupled region, the gate region, and the channel region..
1 17. The method of claim 12 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 18. The method of claim 12 further comprising a drain electrode electrically 2 coupled to the I II -nitride substrate. 22
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET with low gate-drain capacitance
Materials described outside the worked examples.
III-nitride substrate
III-nitride material of first conductivity type
III-nitride material of second conductivity type
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+ III-nitride substrate dopant concentration range | 100000000000000000–10000000000000000000 cm⁻³ | GaN |
n- III-nitride drift region dopant concentration range | 100000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,391,179Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In a power switching application, it is generally preferable to minimize the value of the gate-drain capacitance Cgd, becau s e this capacitance is …
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: 2 providing a I II -nitride substrate; 3 forming a channel region and a drift region, wherein: 4 the drift region and the channel region comprise a I II -nitride material of a 5 first conductivity type, and 6 the drift region is coupled to the I II -nitride substrate; 7 forming a source region coupled to the channel region; 8 forming a gate region coupled to the channel region, wherein the gate region 9 comprises a I II -nitride material of a second conductivity type; 10 forming a source-coupled region coupled to the drift region; and 11 electrically connecting the source-coupled region to the source region.
1 2. The method of claim 1 wherein an area defined by a junction of the gate 2 region and the drift region is smaller than an area defined by a junction of the source-coupled 3 region and the drift region.
1 3. The method of claim 1 wherein forming either or both of the channel 2 region or the drift region comprises: 3 forming a I II -nitride epitaxial layer coupled to the I II -nitride substrate; and 4 removing at least a portion of the I II -nitride epitaxial layer.
1 4. The method of claim 1 f u rther comprising forming an edge termination 2 structure surrounding the gate region, the source-coupled region, and the channel region.
1 5. The method of claim 1 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 6. The method of claim 1 f u rther comprising forming a p-ohmic contact layer 2 electrically coupled to the source-coupled region.
1 9. The method of claim 1 wherein electrically connecting the source-coupled 2 region to the source region comprises forming at least one metal layer coupled to the source- 3 coupled region and the source region.
1 10. The method of claim 1 wherein the drift region and the channel region are 2 formed from a single I II -nitride epitaxial layer.
1 11. The method of claim 1 further comprising forming a source electrode such 2 that a dielectric layer is disposed between at least a portion of the source region and at least a 3 portion of the source electrode.
1 12. A method comprising: 2 providing a I II -nitride substrate; 3 forming a first I II -nitride epitaxial layer coupled to the I II -nitride substrate; 4 forming a source region coupled to the first I II -nitride epitaxial layer; 5 removing at least a portion of the first I II -nitride epitaxial layer and at least a 6 portion of the source region to form a channel region, a drift region, and a separation region; 7 forming a second I II -nitride epitaxial layer coupled to the channel region and the 8 drift region, the second I II -nitride epitaxial layer comprising a gate region and a source-coupled 9 region, wherein the gate region and the source-coupled region are separated by the separation 10 region; and 11 forming a metal structure electrically connecting the source region with the 12 source-coupled region.
21 1 13. The method of claim 12 further comprising forming an Ohmic metal 2 contact coupled to the source-coupled region, wherein the metal structure is coupled to the 3 Ohmic metal contact.
1 14. The method of claim 12 further comprising: 2 forming a dielectric layer; and 3 forming a second metal structure; 4 wherein: 5 the second metal structure is electrically connected to the gate region; and 6 the dielectric layer is disposed between at least a portion of the source- 7 coupled region and at least a portion of the second metal structure.
1 15. The method of claim 12 wherein: 2 the gate region is coupled to the drift region at a first area of a surface of the drift 3 region; and 4 the source-coupled region is coupled to the drift region at a second area of the 5 surface of the drift region, the second area being larger than the first area.
1 16. The method of claim 12 further comprising forming an edge termination 2 structure surrounding the source-coupled region, the gate region, and the channel region..
1 17. The method of claim 12 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 18. The method of claim 12 further comprising a drain electrode electrically 2 coupled to the I II -nitride substrate. 22
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET with low gate-drain capacitance
Materials described outside the worked examples.
III-nitride substrate
III-nitride material of first conductivity type
III-nitride material of second conductivity type
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+ III-nitride substrate dopant concentration range | 100000000000000000–10000000000000000000 cm⁻³ | GaN |
n- III-nitride drift region dopant concentration range | 100000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,391,179Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1. In a power switching application, it is generally preferable to minimize the value of the gate-drain capacitance Cgd, becau s e this capacitance is …
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
1 1. A method comprising: 2 providing a I II -nitride substrate; 3 forming a channel region and a drift region, wherein: 4 the drift region and the channel region comprise a I II -nitride material of a 5 first conductivity type, and 6 the drift region is coupled to the I II -nitride substrate; 7 forming a source region coupled to the channel region; 8 forming a gate region coupled to the channel region, wherein the gate region 9 comprises a I II -nitride material of a second conductivity type; 10 forming a source-coupled region coupled to the drift region; and 11 electrically connecting the source-coupled region to the source region.
1 2. The method of claim 1 wherein an area defined by a junction of the gate 2 region and the drift region is smaller than an area defined by a junction of the source-coupled 3 region and the drift region.
1 3. The method of claim 1 wherein forming either or both of the channel 2 region or the drift region comprises: 3 forming a I II -nitride epitaxial layer coupled to the I II -nitride substrate; and 4 removing at least a portion of the I II -nitride epitaxial layer.
1 4. The method of claim 1 f u rther comprising forming an edge termination 2 structure surrounding the gate region, the source-coupled region, and the channel region.
1 5. The method of claim 1 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 6. The method of claim 1 f u rther comprising forming a p-ohmic contact layer 2 electrically coupled to the source-coupled region.
1 9. The method of claim 1 wherein electrically connecting the source-coupled 2 region to the source region comprises forming at least one metal layer coupled to the source- 3 coupled region and the source region.
1 10. The method of claim 1 wherein the drift region and the channel region are 2 formed from a single I II -nitride epitaxial layer.
1 11. The method of claim 1 further comprising forming a source electrode such 2 that a dielectric layer is disposed between at least a portion of the source region and at least a 3 portion of the source electrode.
1 12. A method comprising: 2 providing a I II -nitride substrate; 3 forming a first I II -nitride epitaxial layer coupled to the I II -nitride substrate; 4 forming a source region coupled to the first I II -nitride epitaxial layer; 5 removing at least a portion of the first I II -nitride epitaxial layer and at least a 6 portion of the source region to form a channel region, a drift region, and a separation region; 7 forming a second I II -nitride epitaxial layer coupled to the channel region and the 8 drift region, the second I II -nitride epitaxial layer comprising a gate region and a source-coupled 9 region, wherein the gate region and the source-coupled region are separated by the separation 10 region; and 11 forming a metal structure electrically connecting the source region with the 12 source-coupled region.
21 1 13. The method of claim 12 further comprising forming an Ohmic metal 2 contact coupled to the source-coupled region, wherein the metal structure is coupled to the 3 Ohmic metal contact.
1 14. The method of claim 12 further comprising: 2 forming a dielectric layer; and 3 forming a second metal structure; 4 wherein: 5 the second metal structure is electrically connected to the gate region; and 6 the dielectric layer is disposed between at least a portion of the source- 7 coupled region and at least a portion of the second metal structure.
1 15. The method of claim 12 wherein: 2 the gate region is coupled to the drift region at a first area of a surface of the drift 3 region; and 4 the source-coupled region is coupled to the drift region at a second area of the 5 surface of the drift region, the second area being larger than the first area.
1 16. The method of claim 12 further comprising forming an edge termination 2 structure surrounding the source-coupled region, the gate region, and the channel region..
1 17. The method of claim 12 wherein: 2 the gate region and the source-coupled region are formed such that a gap is 3 disposed between the gate region and the source-coupled region; and 4 the gap has a width smaller than a width of the channel region.
1 18. The method of claim 12 further comprising a drain electrode electrically 2 coupled to the I II -nitride substrate. 22
Layer stacks claimed or described, ordered top of device to substrate.
vertical GaN JFET with low gate-drain capacitance
Materials described outside the worked examples.
III-nitride substrate
III-nitride material of first conductivity type
III-nitride material of second conductivity type
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 illustrates a circuit schematic of a JFET transistor showing the gate-source, drain- source, and gate-drain capacitances. [0010]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
n+ III-nitride substrate dopant concentration range | 100000000000000000–10000000000000000000 cm⁻³ | GaN |
n- III-nitride drift region dopant concentration range | 100000000000000–1000000000000000000 cm⁻³ |
Related documents with shared materials, methods, properties, or citations.
first III-nitride epitaxial layer
GaN
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
GaN |
Thickness | 20–500 nm | — |
Thickness | 100–1000 nm | — |
Thickness | 20–400 nm | — |
Thickness | 2–4 µm | — |
Voltage | ≤ 20 V | — |
first III-nitride epitaxial layer
GaN
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
GaN |
Thickness | 20–500 nm | — |
Thickness | 100–1000 nm | — |
Thickness | 20–400 nm | — |
Thickness | 2–4 µm | — |
Voltage | ≤ 20 V | — |
first III-nitride epitaxial layer
GaN
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
GaN |
Thickness | 20–500 nm | — |
Thickness | 100–1000 nm | — |
Thickness | 20–400 nm | — |
Thickness | 2–4 µm | — |
Voltage | ≤ 20 V | — |
first III-nitride epitaxial layer
GaN
FIG. 3A and 3B illustrate top and cross-sectional views of a power transistor according to one embodiment of the present invention. [0011]
FIGS. 4A-4F illustrate cross-sectional views during various steps in the fabrication of a vertical power transistor according to an embodiment of the present …
FIG. 5 illustrates a method of fabrication of a vertical power transistor, according to an embodiment of the present invention.
GaN |
Thickness | 20–500 nm | — |
Thickness | 100–1000 nm | — |
Thickness | 20–400 nm | — |
Thickness | 2–4 µm | — |
Voltage | ≤ 20 V | — |