Patent
US 7,863,172GALLIUM NITRIDE SEMICONDUCTOR DEVICE
TingGang Zhu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
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US 7,863,172Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
FIG. 2 B is a highly simplified cross-sectional view of the GaN diode of FIG. IB showing the periodic mesa structures; [0024]
FIG. 3 is a highly simplified cross-sectional view of a GaN diode as known in the prior art in a third embodiment; [0025]
FIG. 4 showing the mesa structure after a subsequent stage in the fabrication process in which a passivation layer of silicon dioxide or polyimide is applied …
FIG. 5C is a detailed cross-sectional view of the GaN diode according to a first embodiment of the present invention through the C-C plane of
FIG. 6A. The passivation layer covers the Schot t ky metal contacts, and the passivation layer is then patterned to expose a contact to the active ohmic metal. …
FIG. 7B is a detailed cross-sectiona l view of the GaN diode according to the second embodiment of the present invention through the B-B plane of
FIG. 8 B is a detailed cross-sectional view of the GaN diode according to the first embodiment of the present invention through the B-B plane of
FIG. 9D is an enlarged cross-sectional of the Schottky contact portion of the GaN diode according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a gallium based semiconductor diode, comprising: providing a substrate; forming an n+ doped GaN layer having a thickness between one and six microns on said substrate; forming an n- GaN layer having a thickness greater than three microns on said n+ GaN layer; depositing a first metal layer on said n- doped GaN layer so as to form a first Schottky junction therewith, resulting in said diode having a forward voltage of less than two volts with a current capacity of at least four amperes; and patterning said n- doped layer into a sequence of parallel, elongated finger regions extending normally from a common central region in opposite directions.
The method as defined in claim 1, further comprising depositing a an ohmic metal layer over at least a portion of the n+ GaN layer so as to make ohmic contact with said n+ GaN layer and to form a contact bonding surface of the device.
The method as defined in claim 1 further comprising thinning the substrate to a thickness less than 10 mils to reduce thermal resistance of the substrate for device heat dissipation.
The method as defined in claim 1, further comprising depositing an AI GaN layer between said n-doped GaN layer and said first metal layer.
The method as defined in claim 1 further comprising depositing a second metal layer on said n-doped GaN layer so as to form a second Schottky junction.
-10- Appin. No. 1 2/249.099 18. The method of claim 1 further comprising placing a passivation layer entirely over the n- GaN layer and the n+ GaN layer.
3.
4.
-8- Appin. No. 12/249.099 5. The method of claim 4 1 wherein said finger regions provide for current transport within said diode.
The method of claim 4 2 wherein said ohmic metal layer is deposited over said finger regions.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 and 150 microns so that the resulting diode has a breakdown voltage greater than 500V.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 a n d 150 microns so that the resulting diode has a breakdown voltage between 200 and 500 volts.
The method as defined in claim 4 1 further comprising depositing an aluminum contact layer over the first metal layer and extending over each of the finger regions so as to form a large, low resistance contact binding surface of the device.
The method of claim i1 wherein said first and second metal layers include one of the metals selected from the group comprising Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi and NiSi.
The method of claim I further comprising placing a guard ring selectively on surface of said n-GaN layer.
The method of claim 17 wherein said passivation
The method of claim 17 further comprising pad regions. layer covers the Schottky junction. patterning said passivation layer to create bonding
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode
Materials described outside the worked examples.
n+ doped GaN layer
GaN
first metal layer (Schottky)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
forward voltage (claimed upper limit) | ≤ 2 V | — |
forward current capacity (claimed lower limit) | ≥ 4 A | — |
reverse breakdown voltage (claimed, finger width ~50 um, spacing 5-150 um) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,863,172Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
FIG. 2 B is a highly simplified cross-sectional view of the GaN diode of FIG. IB showing the periodic mesa structures; [0024]
FIG. 3 is a highly simplified cross-sectional view of a GaN diode as known in the prior art in a third embodiment; [0025]
FIG. 4 showing the mesa structure after a subsequent stage in the fabrication process in which a passivation layer of silicon dioxide or polyimide is applied …
FIG. 5C is a detailed cross-sectional view of the GaN diode according to a first embodiment of the present invention through the C-C plane of
FIG. 6A. The passivation layer covers the Schot t ky metal contacts, and the passivation layer is then patterned to expose a contact to the active ohmic metal. …
FIG. 7B is a detailed cross-sectiona l view of the GaN diode according to the second embodiment of the present invention through the B-B plane of
FIG. 8 B is a detailed cross-sectional view of the GaN diode according to the first embodiment of the present invention through the B-B plane of
FIG. 9D is an enlarged cross-sectional of the Schottky contact portion of the GaN diode according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a gallium based semiconductor diode, comprising: providing a substrate; forming an n+ doped GaN layer having a thickness between one and six microns on said substrate; forming an n- GaN layer having a thickness greater than three microns on said n+ GaN layer; depositing a first metal layer on said n- doped GaN layer so as to form a first Schottky junction therewith, resulting in said diode having a forward voltage of less than two volts with a current capacity of at least four amperes; and patterning said n- doped layer into a sequence of parallel, elongated finger regions extending normally from a common central region in opposite directions.
The method as defined in claim 1, further comprising depositing a an ohmic metal layer over at least a portion of the n+ GaN layer so as to make ohmic contact with said n+ GaN layer and to form a contact bonding surface of the device.
The method as defined in claim 1 further comprising thinning the substrate to a thickness less than 10 mils to reduce thermal resistance of the substrate for device heat dissipation.
The method as defined in claim 1, further comprising depositing an AI GaN layer between said n-doped GaN layer and said first metal layer.
The method as defined in claim 1 further comprising depositing a second metal layer on said n-doped GaN layer so as to form a second Schottky junction.
-10- Appin. No. 1 2/249.099 18. The method of claim 1 further comprising placing a passivation layer entirely over the n- GaN layer and the n+ GaN layer.
3.
4.
-8- Appin. No. 12/249.099 5. The method of claim 4 1 wherein said finger regions provide for current transport within said diode.
The method of claim 4 2 wherein said ohmic metal layer is deposited over said finger regions.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 and 150 microns so that the resulting diode has a breakdown voltage greater than 500V.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 a n d 150 microns so that the resulting diode has a breakdown voltage between 200 and 500 volts.
The method as defined in claim 4 1 further comprising depositing an aluminum contact layer over the first metal layer and extending over each of the finger regions so as to form a large, low resistance contact binding surface of the device.
The method of claim i1 wherein said first and second metal layers include one of the metals selected from the group comprising Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi and NiSi.
The method of claim I further comprising placing a guard ring selectively on surface of said n-GaN layer.
The method of claim 17 wherein said passivation
The method of claim 17 further comprising pad regions. layer covers the Schottky junction. patterning said passivation layer to create bonding
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode
Materials described outside the worked examples.
n+ doped GaN layer
GaN
first metal layer (Schottky)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
forward voltage (claimed upper limit) | ≤ 2 V | — |
forward current capacity (claimed lower limit) | ≥ 4 A | — |
reverse breakdown voltage (claimed, finger width ~50 um, spacing 5-150 um) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,863,172Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
FIG. 2 B is a highly simplified cross-sectional view of the GaN diode of FIG. IB showing the periodic mesa structures; [0024]
FIG. 3 is a highly simplified cross-sectional view of a GaN diode as known in the prior art in a third embodiment; [0025]
FIG. 4 showing the mesa structure after a subsequent stage in the fabrication process in which a passivation layer of silicon dioxide or polyimide is applied …
FIG. 5C is a detailed cross-sectional view of the GaN diode according to a first embodiment of the present invention through the C-C plane of
FIG. 6A. The passivation layer covers the Schot t ky metal contacts, and the passivation layer is then patterned to expose a contact to the active ohmic metal. …
FIG. 7B is a detailed cross-sectiona l view of the GaN diode according to the second embodiment of the present invention through the B-B plane of
FIG. 8 B is a detailed cross-sectional view of the GaN diode according to the first embodiment of the present invention through the B-B plane of
FIG. 9D is an enlarged cross-sectional of the Schottky contact portion of the GaN diode according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a gallium based semiconductor diode, comprising: providing a substrate; forming an n+ doped GaN layer having a thickness between one and six microns on said substrate; forming an n- GaN layer having a thickness greater than three microns on said n+ GaN layer; depositing a first metal layer on said n- doped GaN layer so as to form a first Schottky junction therewith, resulting in said diode having a forward voltage of less than two volts with a current capacity of at least four amperes; and patterning said n- doped layer into a sequence of parallel, elongated finger regions extending normally from a common central region in opposite directions.
The method as defined in claim 1, further comprising depositing a an ohmic metal layer over at least a portion of the n+ GaN layer so as to make ohmic contact with said n+ GaN layer and to form a contact bonding surface of the device.
The method as defined in claim 1 further comprising thinning the substrate to a thickness less than 10 mils to reduce thermal resistance of the substrate for device heat dissipation.
The method as defined in claim 1, further comprising depositing an AI GaN layer between said n-doped GaN layer and said first metal layer.
The method as defined in claim 1 further comprising depositing a second metal layer on said n-doped GaN layer so as to form a second Schottky junction.
-10- Appin. No. 1 2/249.099 18. The method of claim 1 further comprising placing a passivation layer entirely over the n- GaN layer and the n+ GaN layer.
3.
4.
-8- Appin. No. 12/249.099 5. The method of claim 4 1 wherein said finger regions provide for current transport within said diode.
The method of claim 4 2 wherein said ohmic metal layer is deposited over said finger regions.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 and 150 microns so that the resulting diode has a breakdown voltage greater than 500V.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 a n d 150 microns so that the resulting diode has a breakdown voltage between 200 and 500 volts.
The method as defined in claim 4 1 further comprising depositing an aluminum contact layer over the first metal layer and extending over each of the finger regions so as to form a large, low resistance contact binding surface of the device.
The method of claim i1 wherein said first and second metal layers include one of the metals selected from the group comprising Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi and NiSi.
The method of claim I further comprising placing a guard ring selectively on surface of said n-GaN layer.
The method of claim 17 wherein said passivation
The method of claim 17 further comprising pad regions. layer covers the Schottky junction. patterning said passivation layer to create bonding
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode
Materials described outside the worked examples.
n+ doped GaN layer
GaN
first metal layer (Schottky)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
forward voltage (claimed upper limit) | ≤ 2 V | — |
forward current capacity (claimed lower limit) | ≥ 4 A | — |
reverse breakdown voltage (claimed, finger width ~50 um, spacing 5-150 um) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 7,863,172Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
FIG. 2 B is a highly simplified cross-sectional view of the GaN diode of FIG. IB showing the periodic mesa structures; [0024]
FIG. 3 is a highly simplified cross-sectional view of a GaN diode as known in the prior art in a third embodiment; [0025]
FIG. 4 showing the mesa structure after a subsequent stage in the fabrication process in which a passivation layer of silicon dioxide or polyimide is applied …
FIG. 5C is a detailed cross-sectional view of the GaN diode according to a first embodiment of the present invention through the C-C plane of
FIG. 6A. The passivation layer covers the Schot t ky metal contacts, and the passivation layer is then patterned to expose a contact to the active ohmic metal. …
FIG. 7B is a detailed cross-sectiona l view of the GaN diode according to the second embodiment of the present invention through the B-B plane of
FIG. 8 B is a detailed cross-sectional view of the GaN diode according to the first embodiment of the present invention through the B-B plane of
FIG. 9D is an enlarged cross-sectional of the Schottky contact portion of the GaN diode according to another embodiment of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for fabricating a gallium based semiconductor diode, comprising: providing a substrate; forming an n+ doped GaN layer having a thickness between one and six microns on said substrate; forming an n- GaN layer having a thickness greater than three microns on said n+ GaN layer; depositing a first metal layer on said n- doped GaN layer so as to form a first Schottky junction therewith, resulting in said diode having a forward voltage of less than two volts with a current capacity of at least four amperes; and patterning said n- doped layer into a sequence of parallel, elongated finger regions extending normally from a common central region in opposite directions.
The method as defined in claim 1, further comprising depositing a an ohmic metal layer over at least a portion of the n+ GaN layer so as to make ohmic contact with said n+ GaN layer and to form a contact bonding surface of the device.
The method as defined in claim 1 further comprising thinning the substrate to a thickness less than 10 mils to reduce thermal resistance of the substrate for device heat dissipation.
The method as defined in claim 1, further comprising depositing an AI GaN layer between said n-doped GaN layer and said first metal layer.
The method as defined in claim 1 further comprising depositing a second metal layer on said n-doped GaN layer so as to form a second Schottky junction.
-10- Appin. No. 1 2/249.099 18. The method of claim 1 further comprising placing a passivation layer entirely over the n- GaN layer and the n+ GaN layer.
3.
4.
-8- Appin. No. 12/249.099 5. The method of claim 4 1 wherein said finger regions provide for current transport within said diode.
The method of claim 4 2 wherein said ohmic metal layer is deposited over said finger regions.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 and 150 microns so that the resulting diode has a breakdown voltage greater than 500V.
The method as defined in claim 4 1, wherein the width of each finger regions is approximately 50 microns and spacing between 5 a n d 150 microns so that the resulting diode has a breakdown voltage between 200 and 500 volts.
The method as defined in claim 4 1 further comprising depositing an aluminum contact layer over the first metal layer and extending over each of the finger regions so as to form a large, low resistance contact binding surface of the device.
The method of claim i1 wherein said first and second metal layers include one of the metals selected from the group comprising Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi and NiSi.
The method of claim I further comprising placing a guard ring selectively on surface of said n-GaN layer.
The method of claim 17 wherein said passivation
The method of claim 17 further comprising pad regions. layer covers the Schottky junction. patterning said passivation layer to create bonding
Layer stacks claimed or described, ordered top of device to substrate.
GaN Schottky diode
Materials described outside the worked examples.
n+ doped GaN layer
GaN
first metal layer (Schottky)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A. [0055] Portions of the n- G aN layer 203 are etched down to the n+ layer and ohmic metal contacts 205 are provided on the n+ G aN layer in the etched …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
forward voltage (claimed upper limit) | ≤ 2 V | — |
forward current capacity (claimed lower limit) | ≥ 4 A | — |
reverse breakdown voltage (claimed, finger width ~50 um, spacing 5-150 um) |
Related documents with shared materials, methods, properties, or citations.
ohmic metal layer
aluminum contact layer
Al
AlGaN layer
AlGaN
Schottky metal (Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi, NiSi)
sapphire substrate
Al₂O₃
| ≥ 500 V |
| — |
reverse breakdown voltage (claimed range, finger width ~50 um, spacing 5-150 um) | 200–500 V | — |
reverse breakdown voltage (abstract, optimized device) | ≥ 500 V | — |
forward voltage (abstract, optimized device) | ≤ 3 V | — |
current capacity (abstract, optimized device) | ≥ 1 A | — |
current capacity (described embodiment) | ≥ 5 A | — |
n+ GaN layer thickness (prior art description) | 0.1–1.5 um | GaN |
n- GaN layer thickness (prior art description) | 0.5–1 um | GaN |
Thickness | 0.1–1.5 µm | — |
Thickness | 1–6 µm | — |
Thickness | 1–12 µm | — |
Thickness | 30–200 µm | — |
Thickness | 5–150 µm | — |
Thickness | 0.5–1 µm | — |
Thickness | ≥ 5 µm | — |
ohmic metal layer
aluminum contact layer
Al
AlGaN layer
AlGaN
Schottky metal (Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi, NiSi)
sapphire substrate
Al₂O₃
| ≥ 500 V |
| — |
reverse breakdown voltage (claimed range, finger width ~50 um, spacing 5-150 um) | 200–500 V | — |
reverse breakdown voltage (abstract, optimized device) | ≥ 500 V | — |
forward voltage (abstract, optimized device) | ≤ 3 V | — |
current capacity (abstract, optimized device) | ≥ 1 A | — |
current capacity (described embodiment) | ≥ 5 A | — |
n+ GaN layer thickness (prior art description) | 0.1–1.5 um | GaN |
n- GaN layer thickness (prior art description) | 0.5–1 um | GaN |
Thickness | 0.1–1.5 µm | — |
Thickness | 1–6 µm | — |
Thickness | 1–12 µm | — |
Thickness | 30–200 µm | — |
Thickness | 5–150 µm | — |
Thickness | 0.5–1 µm | — |
Thickness | ≥ 5 µm | — |
ohmic metal layer
aluminum contact layer
Al
AlGaN layer
AlGaN
Schottky metal (Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi, NiSi)
sapphire substrate
Al₂O₃
| ≥ 500 V |
| — |
reverse breakdown voltage (claimed range, finger width ~50 um, spacing 5-150 um) | 200–500 V | — |
reverse breakdown voltage (abstract, optimized device) | ≥ 500 V | — |
forward voltage (abstract, optimized device) | ≤ 3 V | — |
current capacity (abstract, optimized device) | ≥ 1 A | — |
current capacity (described embodiment) | ≥ 5 A | — |
n+ GaN layer thickness (prior art description) | 0.1–1.5 um | GaN |
n- GaN layer thickness (prior art description) | 0.5–1 um | GaN |
Thickness | 0.1–1.5 µm | — |
Thickness | 1–6 µm | — |
Thickness | 1–12 µm | — |
Thickness | 30–200 µm | — |
Thickness | 5–150 µm | — |
Thickness | 0.5–1 µm | — |
Thickness | ≥ 5 µm | — |
ohmic metal layer
aluminum contact layer
Al
AlGaN layer
AlGaN
Schottky metal (Ni, Pt, Au, Co, Pd, Mo, Cr, Rh, Re, PtSi, NiSi)
sapphire substrate
Al₂O₃
| ≥ 500 V |
| — |
reverse breakdown voltage (claimed range, finger width ~50 um, spacing 5-150 um) | 200–500 V | — |
reverse breakdown voltage (abstract, optimized device) | ≥ 500 V | — |
forward voltage (abstract, optimized device) | ≤ 3 V | — |
current capacity (abstract, optimized device) | ≥ 1 A | — |
current capacity (described embodiment) | ≥ 5 A | — |
n+ GaN layer thickness (prior art description) | 0.1–1.5 um | GaN |
n- GaN layer thickness (prior art description) | 0.5–1 um | GaN |
Thickness | 0.1–1.5 µm | — |
Thickness | 1–6 µm | — |
Thickness | 1–12 µm | — |
Thickness | 30–200 µm | — |
Thickness | 5–150 µm | — |
Thickness | 0.5–1 µm | — |
Thickness | ≥ 5 µm | — |