Patent
US 11,114,556GATE STACK DESIGN FOR GAN E-MODE TRANSISTOR PERFORMANCE
Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz K. Gardner et al.
US
Copyright © 2026 Matter42. All rights reserved.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a first layer including a group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising aluminum, gallium, and nitrogen, and the third and fourth layers each comprising aluminum and nitrogen; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, the third regions including a group I II -V semiconductor material. Original
The integrated circuit structure of claim 1, wherein the first layer is gallium nitride (G aN). Original
The integrated circuit structure of claim 1, wherein the gate stack further includes: a gate electrode; and a gate dielectric structure, wherein the gate dielectric structure is a multi-layer structure including a layer of interface material and a layer of high-k dielectric material, wherein the layer of interface material is a group I II-V semiconductor oxide. Original
The integrated circuit structure of claim 1, wherein the second layer has an aluminum concentration in the range of 5 % to 15 %. Original
The integrated circuit structure of claim 1, wherein the first and second regions are n-doped and include nitrogen and one or both of gallium and indium. Original
The integrated circuit structure of claim 1, wherein the group I II-V semiconductor material of the third regions includes aluminum and nitrogen. Original
The integrated circuit structure of claim 1, wherein the group III-V semiconductor material of the third regions has an aluminum concentration that is greater than the aluminum concentration of the second layer. Original
The integrated circuit structure of claim 1, wherein the gate stack includes a layer of high-k dielectric material directly on the third layer. Original
A system-on-chip comprising the integrated circuit structure of claim 1. Original
A mobile computing system comprising the integrated circuit structure of claim 1. Original
An integrated circuit structure, comprising: a dielectric structure; a first layer including gallium and nitrogen, the first layer on a top surface and at least one sidewall surface of the dielectric structure; a gate stack over the first layer, the gate stack including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, the charge spillover reducing layer comprising a first group I II -N semiconductor compound and the lattice grading layer comprising a second group I II -N semiconductor compound that is different from the first group I II -N semiconductor compound, wherein the lattice grading layer includes aluminum; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, wherein the first and second regions are n-doped and include nitrogen and one or both of indium and gallium, and wherein the third regions include a group I II -V semiconductor material having an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer. Original
The integrated circuit structure of claim 11, wherein the gate stack further includes a gate electrode and a work function tuning structure, wherein the work function tuning structure is a multi-layer structure. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer comprises aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer comprises aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 5 % to 15 %, and wherein the lattice grading layer has a thickness in the range of 1 nm to 3 nm, and the charge spillover reducing layer has a thickness in the range of 0.5 nm to 2 nm. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, indium, and nitrogen and has an aluminum concentration in the range of 80 % to 85 %. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 20 % to 40 %. Original
The integrated circuit structure of claim 11, wherein the gate stack includes a layer of high-k dielectric material directly on the charge spillover reducing layer. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer consists essentially of aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer consists essentially of aluminum, gallium, and nitrogen. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between and in contact with third and fourth layers, the second layer comprising a second group I II-V semiconductor material, and the third and fourth layers each comprising a third group III- V semiconductor material; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance. Currently amended
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen; the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. Original
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group III -V semiconductor material includes an aluminum concentration of less than 15 % and the second layer has a thickness in the range of 1 nm to 3 nm; and the third and fourth layers each has a thickness in the range of 0.5 nm to 2 nm. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material, wherein the first group I II -V semiconductor material consists essentially of gallium and nitrogen; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising a second group I II -V semiconductor material, and the third and fourth layers each comprising a third group I II -V semiconductor material, wherein the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen, and wherein the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material, wherein the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance, and wherein the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. New
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit structure with III-V gate stack (claims 1-10)
integrated circuit structure with GaN channel and barrier structure (claims 11-17)
integrated circuit structure with asymmetric source-drain access regions (claims 18-21)
prior art GaN MOSHEMT gate stack (background)
Materials described outside the worked examples.
group III-V semiconductor material (first layer/generic)
AlGaN (lattice grading layer/second layer)
AlGaN
AlN (charge spillover reducing layer/third and fourth layers)
AlN
group III-V semiconductor material (access/third regions, Al+N containing)
gallium nitride
GaN
high-k dielectric material
group III-V semiconductor oxide (interface/interlayer dielectric)
n-doped group III-V semiconductor (source/drain regions, Ga/In+N)
AlInN (access regions, 80-85% Al)
AlInN
n-doped GaN (source/drain regions with n-type dopant)
GaN:n
aluminum oxide (interface layer, ~1.5 nm, background/prior art)
Al₂O₃
hafnium oxide (gate dielectric, ~4.5 nm, background/prior art)
HfO₂
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–8 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 1–4 nm | — |
Thickness | 0.5–5 nm | — |
Thickness | 10–2000 nm | — |
Thickness | 20–200 nm | — |
Thickness | 10–15 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–25 nm | — |
Thickness | ≥ 1 nm | — |
Related documents with shared materials, methods, properties, or citations.
GAN DEVICE WITH N2 PRE-TREATMENT AND METHOD OF PERFORMING N2 PRE-TREATMENT
AIGAN/GAN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES
ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
GaN Dual Field Plate Device with Single Field Plate Metal
GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GAN-BASED SEMICONDUCTOR ELEMENT
A GALLIUM NITRIDE TRANSISTOR WITH A HYBRID ALUMINUM OXIDE LAYER AS A GATE DIELECTRIC
Growth of Planar Non-Polar {1 -1 0 0} M-Plane and Semi-Polar {1 1 -2 2} Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE)
GALLIUM NITRIDE SEMICONDUCTOR DEVICES AND METHOD MAKING THEREOF
Hybrid Classical-Quantum Neural Networks for Multi-Characteristic Co-Optimization of Recessed-Gate AlGaN/GaN MIS-HEMTs
NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET)
ENHANCEMENT MODE MISHEMT WITH GAN CHANNEL REGROWTH UNDER A GATE AREA
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a first layer including a group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising aluminum, gallium, and nitrogen, and the third and fourth layers each comprising aluminum and nitrogen; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, the third regions including a group I II -V semiconductor material. Original
The integrated circuit structure of claim 1, wherein the first layer is gallium nitride (G aN). Original
The integrated circuit structure of claim 1, wherein the gate stack further includes: a gate electrode; and a gate dielectric structure, wherein the gate dielectric structure is a multi-layer structure including a layer of interface material and a layer of high-k dielectric material, wherein the layer of interface material is a group I II-V semiconductor oxide. Original
The integrated circuit structure of claim 1, wherein the second layer has an aluminum concentration in the range of 5 % to 15 %. Original
The integrated circuit structure of claim 1, wherein the first and second regions are n-doped and include nitrogen and one or both of gallium and indium. Original
The integrated circuit structure of claim 1, wherein the group I II-V semiconductor material of the third regions includes aluminum and nitrogen. Original
The integrated circuit structure of claim 1, wherein the group III-V semiconductor material of the third regions has an aluminum concentration that is greater than the aluminum concentration of the second layer. Original
The integrated circuit structure of claim 1, wherein the gate stack includes a layer of high-k dielectric material directly on the third layer. Original
A system-on-chip comprising the integrated circuit structure of claim 1. Original
A mobile computing system comprising the integrated circuit structure of claim 1. Original
An integrated circuit structure, comprising: a dielectric structure; a first layer including gallium and nitrogen, the first layer on a top surface and at least one sidewall surface of the dielectric structure; a gate stack over the first layer, the gate stack including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, the charge spillover reducing layer comprising a first group I II -N semiconductor compound and the lattice grading layer comprising a second group I II -N semiconductor compound that is different from the first group I II -N semiconductor compound, wherein the lattice grading layer includes aluminum; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, wherein the first and second regions are n-doped and include nitrogen and one or both of indium and gallium, and wherein the third regions include a group I II -V semiconductor material having an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer. Original
The integrated circuit structure of claim 11, wherein the gate stack further includes a gate electrode and a work function tuning structure, wherein the work function tuning structure is a multi-layer structure. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer comprises aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer comprises aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 5 % to 15 %, and wherein the lattice grading layer has a thickness in the range of 1 nm to 3 nm, and the charge spillover reducing layer has a thickness in the range of 0.5 nm to 2 nm. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, indium, and nitrogen and has an aluminum concentration in the range of 80 % to 85 %. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 20 % to 40 %. Original
The integrated circuit structure of claim 11, wherein the gate stack includes a layer of high-k dielectric material directly on the charge spillover reducing layer. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer consists essentially of aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer consists essentially of aluminum, gallium, and nitrogen. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between and in contact with third and fourth layers, the second layer comprising a second group I II-V semiconductor material, and the third and fourth layers each comprising a third group III- V semiconductor material; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance. Currently amended
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen; the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. Original
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group III -V semiconductor material includes an aluminum concentration of less than 15 % and the second layer has a thickness in the range of 1 nm to 3 nm; and the third and fourth layers each has a thickness in the range of 0.5 nm to 2 nm. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material, wherein the first group I II -V semiconductor material consists essentially of gallium and nitrogen; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising a second group I II -V semiconductor material, and the third and fourth layers each comprising a third group I II -V semiconductor material, wherein the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen, and wherein the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material, wherein the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance, and wherein the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. New
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit structure with III-V gate stack (claims 1-10)
integrated circuit structure with GaN channel and barrier structure (claims 11-17)
integrated circuit structure with asymmetric source-drain access regions (claims 18-21)
prior art GaN MOSHEMT gate stack (background)
Materials described outside the worked examples.
group III-V semiconductor material (first layer/generic)
AlGaN (lattice grading layer/second layer)
AlGaN
AlN (charge spillover reducing layer/third and fourth layers)
AlN
group III-V semiconductor material (access/third regions, Al+N containing)
gallium nitride
GaN
high-k dielectric material
group III-V semiconductor oxide (interface/interlayer dielectric)
n-doped group III-V semiconductor (source/drain regions, Ga/In+N)
AlInN (access regions, 80-85% Al)
AlInN
n-doped GaN (source/drain regions with n-type dopant)
GaN:n
aluminum oxide (interface layer, ~1.5 nm, background/prior art)
Al₂O₃
hafnium oxide (gate dielectric, ~4.5 nm, background/prior art)
HfO₂
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–8 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 1–4 nm | — |
Thickness | 0.5–5 nm | — |
Thickness | 10–2000 nm | — |
Thickness | 20–200 nm | — |
Thickness | 10–15 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–25 nm | — |
Thickness | ≥ 1 nm | — |
Related documents with shared materials, methods, properties, or citations.
GAN DEVICE WITH N2 PRE-TREATMENT AND METHOD OF PERFORMING N2 PRE-TREATMENT
AIGAN/GAN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES
ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
GaN Dual Field Plate Device with Single Field Plate Metal
GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GAN-BASED SEMICONDUCTOR ELEMENT
A GALLIUM NITRIDE TRANSISTOR WITH A HYBRID ALUMINUM OXIDE LAYER AS A GATE DIELECTRIC
Growth of Planar Non-Polar {1 -1 0 0} M-Plane and Semi-Polar {1 1 -2 2} Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE)
GALLIUM NITRIDE SEMICONDUCTOR DEVICES AND METHOD MAKING THEREOF
Hybrid Classical-Quantum Neural Networks for Multi-Characteristic Co-Optimization of Recessed-Gate AlGaN/GaN MIS-HEMTs
NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET)
ENHANCEMENT MODE MISHEMT WITH GAN CHANNEL REGROWTH UNDER A GATE AREA
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a first layer including a group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising aluminum, gallium, and nitrogen, and the third and fourth layers each comprising aluminum and nitrogen; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, the third regions including a group I II -V semiconductor material. Original
The integrated circuit structure of claim 1, wherein the first layer is gallium nitride (G aN). Original
The integrated circuit structure of claim 1, wherein the gate stack further includes: a gate electrode; and a gate dielectric structure, wherein the gate dielectric structure is a multi-layer structure including a layer of interface material and a layer of high-k dielectric material, wherein the layer of interface material is a group I II-V semiconductor oxide. Original
The integrated circuit structure of claim 1, wherein the second layer has an aluminum concentration in the range of 5 % to 15 %. Original
The integrated circuit structure of claim 1, wherein the first and second regions are n-doped and include nitrogen and one or both of gallium and indium. Original
The integrated circuit structure of claim 1, wherein the group I II-V semiconductor material of the third regions includes aluminum and nitrogen. Original
The integrated circuit structure of claim 1, wherein the group III-V semiconductor material of the third regions has an aluminum concentration that is greater than the aluminum concentration of the second layer. Original
The integrated circuit structure of claim 1, wherein the gate stack includes a layer of high-k dielectric material directly on the third layer. Original
A system-on-chip comprising the integrated circuit structure of claim 1. Original
A mobile computing system comprising the integrated circuit structure of claim 1. Original
An integrated circuit structure, comprising: a dielectric structure; a first layer including gallium and nitrogen, the first layer on a top surface and at least one sidewall surface of the dielectric structure; a gate stack over the first layer, the gate stack including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, the charge spillover reducing layer comprising a first group I II -N semiconductor compound and the lattice grading layer comprising a second group I II -N semiconductor compound that is different from the first group I II -N semiconductor compound, wherein the lattice grading layer includes aluminum; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, wherein the first and second regions are n-doped and include nitrogen and one or both of indium and gallium, and wherein the third regions include a group I II -V semiconductor material having an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer. Original
The integrated circuit structure of claim 11, wherein the gate stack further includes a gate electrode and a work function tuning structure, wherein the work function tuning structure is a multi-layer structure. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer comprises aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer comprises aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 5 % to 15 %, and wherein the lattice grading layer has a thickness in the range of 1 nm to 3 nm, and the charge spillover reducing layer has a thickness in the range of 0.5 nm to 2 nm. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, indium, and nitrogen and has an aluminum concentration in the range of 80 % to 85 %. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 20 % to 40 %. Original
The integrated circuit structure of claim 11, wherein the gate stack includes a layer of high-k dielectric material directly on the charge spillover reducing layer. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer consists essentially of aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer consists essentially of aluminum, gallium, and nitrogen. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between and in contact with third and fourth layers, the second layer comprising a second group I II-V semiconductor material, and the third and fourth layers each comprising a third group III- V semiconductor material; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance. Currently amended
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen; the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. Original
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group III -V semiconductor material includes an aluminum concentration of less than 15 % and the second layer has a thickness in the range of 1 nm to 3 nm; and the third and fourth layers each has a thickness in the range of 0.5 nm to 2 nm. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material, wherein the first group I II -V semiconductor material consists essentially of gallium and nitrogen; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising a second group I II -V semiconductor material, and the third and fourth layers each comprising a third group I II -V semiconductor material, wherein the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen, and wherein the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material, wherein the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance, and wherein the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. New
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit structure with III-V gate stack (claims 1-10)
integrated circuit structure with GaN channel and barrier structure (claims 11-17)
integrated circuit structure with asymmetric source-drain access regions (claims 18-21)
prior art GaN MOSHEMT gate stack (background)
Materials described outside the worked examples.
group III-V semiconductor material (first layer/generic)
AlGaN (lattice grading layer/second layer)
AlGaN
AlN (charge spillover reducing layer/third and fourth layers)
AlN
group III-V semiconductor material (access/third regions, Al+N containing)
gallium nitride
GaN
high-k dielectric material
group III-V semiconductor oxide (interface/interlayer dielectric)
n-doped group III-V semiconductor (source/drain regions, Ga/In+N)
AlInN (access regions, 80-85% Al)
AlInN
n-doped GaN (source/drain regions with n-type dopant)
GaN:n
aluminum oxide (interface layer, ~1.5 nm, background/prior art)
Al₂O₃
hafnium oxide (gate dielectric, ~4.5 nm, background/prior art)
HfO₂
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–8 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 1–4 nm | — |
Thickness | 0.5–5 nm | — |
Thickness | 10–2000 nm | — |
Thickness | 20–200 nm | — |
Thickness | 10–15 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–25 nm | — |
Thickness | ≥ 1 nm | — |
Related documents with shared materials, methods, properties, or citations.
GAN DEVICE WITH N2 PRE-TREATMENT AND METHOD OF PERFORMING N2 PRE-TREATMENT
AIGAN/GAN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES
ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
GaN Dual Field Plate Device with Single Field Plate Metal
GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GAN-BASED SEMICONDUCTOR ELEMENT
A GALLIUM NITRIDE TRANSISTOR WITH A HYBRID ALUMINUM OXIDE LAYER AS A GATE DIELECTRIC
Growth of Planar Non-Polar {1 -1 0 0} M-Plane and Semi-Polar {1 1 -2 2} Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE)
GALLIUM NITRIDE SEMICONDUCTOR DEVICES AND METHOD MAKING THEREOF
Hybrid Classical-Quantum Neural Networks for Multi-Characteristic Co-Optimization of Recessed-Gate AlGaN/GaN MIS-HEMTs
NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET)
ENHANCEMENT MODE MISHEMT WITH GAN CHANNEL REGROWTH UNDER A GATE AREA
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit structure, comprising: a first layer including a group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising aluminum, gallium, and nitrogen, and the third and fourth layers each comprising aluminum and nitrogen; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, the third regions including a group I II -V semiconductor material. Original
The integrated circuit structure of claim 1, wherein the first layer is gallium nitride (G aN). Original
The integrated circuit structure of claim 1, wherein the gate stack further includes: a gate electrode; and a gate dielectric structure, wherein the gate dielectric structure is a multi-layer structure including a layer of interface material and a layer of high-k dielectric material, wherein the layer of interface material is a group I II-V semiconductor oxide. Original
The integrated circuit structure of claim 1, wherein the second layer has an aluminum concentration in the range of 5 % to 15 %. Original
The integrated circuit structure of claim 1, wherein the first and second regions are n-doped and include nitrogen and one or both of gallium and indium. Original
The integrated circuit structure of claim 1, wherein the group I II-V semiconductor material of the third regions includes aluminum and nitrogen. Original
The integrated circuit structure of claim 1, wherein the group III-V semiconductor material of the third regions has an aluminum concentration that is greater than the aluminum concentration of the second layer. Original
The integrated circuit structure of claim 1, wherein the gate stack includes a layer of high-k dielectric material directly on the third layer. Original
A system-on-chip comprising the integrated circuit structure of claim 1. Original
A mobile computing system comprising the integrated circuit structure of claim 1. Original
An integrated circuit structure, comprising: a dielectric structure; a first layer including gallium and nitrogen, the first layer on a top surface and at least one sidewall surface of the dielectric structure; a gate stack over the first layer, the gate stack including a barrier structure configured with a charge spillover reducing layer on a lattice grading layer, the charge spillover reducing layer comprising a first group I II -N semiconductor compound and the lattice grading layer comprising a second group I II -N semiconductor compound that is different from the first group I II -N semiconductor compound, wherein the lattice grading layer includes aluminum; and a first region and a second region each including a group I II -V semiconductor material and separated from at least a portion of the gate stack by respective third regions, wherein the first and second regions are n-doped and include nitrogen and one or both of indium and gallium, and wherein the third regions include a group I II -V semiconductor material having an aluminum concentration that is greater than the aluminum concentration of the lattice grading layer. Original
The integrated circuit structure of claim 11, wherein the gate stack further includes a gate electrode and a work function tuning structure, wherein the work function tuning structure is a multi-layer structure. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer comprises aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer comprises aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 5 % to 15 %, and wherein the lattice grading layer has a thickness in the range of 1 nm to 3 nm, and the charge spillover reducing layer has a thickness in the range of 0.5 nm to 2 nm. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, indium, and nitrogen and has an aluminum concentration in the range of 80 % to 85 %. Original
The integrated circuit structure of claim 11, wherein the group I II-V semiconductor material of the third regions includes aluminum, gallium, and nitrogen and has an aluminum concentration in the range of 20 % to 40 %. Original
The integrated circuit structure of claim 11, wherein the gate stack includes a layer of high-k dielectric material directly on the charge spillover reducing layer. Original
The integrated circuit structure of claim 11, wherein the first group III- N semiconductor compound of the charge spillover reducing layer consists essentially of aluminum and nitrogen, and the second group I II -N semiconductor compound of the lattice grading layer consists essentially of aluminum, gallium, and nitrogen. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material; a gate stack over the first layer, and including a second layer between and in contact with third and fourth layers, the second layer comprising a second group I II-V semiconductor material, and the third and fourth layers each comprising a third group III- V semiconductor material; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance. Currently amended
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen; the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. Original
The integrated circuit of claim 18, wherein the first group I II-V semiconductor material consists essentially of gallium and nitrogen; the second group III -V semiconductor material includes an aluminum concentration of less than 15 % and the second layer has a thickness in the range of 1 nm to 3 nm; and the third and fourth layers each has a thickness in the range of 0.5 nm to 2 nm. Original
An integrated circuit structure, comprising: a first layer including a first group I II -V semiconductor material, wherein the first group I II -V semiconductor material consists essentially of gallium and nitrogen; a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising a second group I II -V semiconductor material, and the third and fourth layers each comprising a third group I II -V semiconductor material, wherein the second group I II -V semiconductor material consists essentially of aluminum, gallium, and nitrogen, and wherein the third group I II -V semiconductor material consists essentially of aluminum and nitrogen; a source region and a drain region each over the first layer and including a fourth group I II -V semiconductor material, wherein the fourth group I II -V semiconductor material comprises gallium, nitrogen, and an n-type dopant; and a first region between the source region and the gate stack so as to separate the source region from the gate stack by a first distance, and a second region between the drain region and the gate stack so as to separate the drain region from the gate stack by a second distance, the first and second regions including a fifth group I II -V semiconductor material, wherein the second distance is greater than the first distance, and wherein the fifth group I II -V semiconductor material consists essentially of aluminum, indium, and nitrogen. New
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit structure with III-V gate stack (claims 1-10)
integrated circuit structure with GaN channel and barrier structure (claims 11-17)
integrated circuit structure with asymmetric source-drain access regions (claims 18-21)
prior art GaN MOSHEMT gate stack (background)
Materials described outside the worked examples.
group III-V semiconductor material (first layer/generic)
AlGaN (lattice grading layer/second layer)
AlGaN
AlN (charge spillover reducing layer/third and fourth layers)
AlN
group III-V semiconductor material (access/third regions, Al+N containing)
gallium nitride
GaN
high-k dielectric material
group III-V semiconductor oxide (interface/interlayer dielectric)
n-doped group III-V semiconductor (source/drain regions, Ga/In+N)
AlInN (access regions, 80-85% Al)
AlInN
n-doped GaN (source/drain regions with n-type dopant)
GaN:n
aluminum oxide (interface layer, ~1.5 nm, background/prior art)
Al₂O₃
hafnium oxide (gate dielectric, ~4.5 nm, background/prior art)
HfO₂
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–8 nm | — |
Thickness | 0.5–2 nm | — |
Thickness | 1–4 nm | — |
Thickness | 0.5–5 nm | — |
Thickness | 10–2000 nm | — |
Thickness | 20–200 nm | — |
Thickness | 10–15 nm | — |
Thickness | 1–3 nm | — |
Thickness | 5–25 nm | — |
Thickness | ≥ 1 nm | — |
Related documents with shared materials, methods, properties, or citations.
GAN DEVICE WITH N2 PRE-TREATMENT AND METHOD OF PERFORMING N2 PRE-TREATMENT
AIGAN/GAN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES
ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
GaN Dual Field Plate Device with Single Field Plate Metal
GALLIUM NITRIDE SEMICONDUCTOR DEVICE
GAN-BASED SEMICONDUCTOR ELEMENT
A GALLIUM NITRIDE TRANSISTOR WITH A HYBRID ALUMINUM OXIDE LAYER AS A GATE DIELECTRIC
Growth of Planar Non-Polar {1 -1 0 0} M-Plane and Semi-Polar {1 1 -2 2} Gallium Nitride with Hydride Vapor Phase Epitaxy (HVPE)
GALLIUM NITRIDE SEMICONDUCTOR DEVICES AND METHOD MAKING THEREOF
Hybrid Classical-Quantum Neural Networks for Multi-Characteristic Co-Optimization of Recessed-Gate AlGaN/GaN MIS-HEMTs
NORMALLY OFF GALLIUM NITRIDE FIELD EFFECT TRANSISTORS (FET)
ENHANCEMENT MODE MISHEMT WITH GAN CHANNEL REGROWTH UNDER A GATE AREA