GAN DUAL FIELD PLATE DEVICE WITH SINGLE FIELD PLATE METAL

James A. Teplik

Patent

Atlas literature

Patent

US 9,024,324

GAN DUAL FIELD PLATE DEVICE WITH SINGLE FIELD PLATE METAL

James A. Teplik, Bruce M. Green

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

3 independent · 19 dependent

1
IndependentGaNSi₃N₄Al₂O₃dielectric surface layerGaN HFET with multi-region field plate (method claim 1)
AMENDMENTS TO THE CLAIMS 1. A method of forming gallium nitride transistor, comprising: providing a substrate with a gallium nitride layer covered by a dielectric surface layer; forming a conductive gate electrode with a contact base portion in contact with a gate contact surface of the substrate; forming drain and source electrodes spaced apart from the conductive gate electrode and in contact with the substrate; forming a plurality of dielectric layers over the gate, drain, and source electrodes, where the plurality of dielectric layers comprises a dielectric etch stop layer and a capping dielectric layer formed over the dielectric etch stop layer; forming a multi-region ﬁeld plate opening extending from the gate electrode partway toward the drain electrode by selectively etching the capping dielectric layer in a ﬁrst sub-region overlapping with the gate electrode using the dielectric etch stop layer as an etch stop layer; and selectively forming a continuous multi-region ﬁeld plate in the multi-region ﬁeld plate opening to shield the gate electrode from the drain electrode.
1. 2
  Dependent← claim 1GaNAlGaNGaNGaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, where the substrate comprises an upper gallium nitride cap layer, a middle aluminum gallium nitride ba rri er layer, and an underlying gallium nitride buﬀer layer.
2. 3
  Dependent← claim 1GaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, where selectively forming the continuous multi-region ﬁeld plate comprises: depositing a conductor layer in at least the multi-region ﬁeld plate opening; and selectively etching the conductor layer to form the continuous multi-region ﬁeld plate in the ﬁrst sub-region and in a second sub-region over a portion of the capping dielectric layer between the gate electrode and drain electrode.
3. 4
  Dependent← claim 1GaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, where selectively forming the continuous multi-region ﬁeld plate comprises: forming a patterned resist mask with a patterned opening over the multi-region ﬁeld plate opening; 2 depositing a conductor layer over the patterned resist mask and in the multiregion ﬁeld plate opening; and removing the patterned resist mask to form the continuous multiregion ﬁeld plate in the ﬁrst sub-region and in a second sub-region over a portion of the capping dielectric layer between the gate electrode and drain electrode.
4. 5
  Dependent← claim 1Si₃N₄Al₂O₃metal oxide dielectricGaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, where forming the plurality of dielectric layers comprises: forming a ﬁrst dielectric layer of silicon nitride over at least the gate electrode and between the gate electrode and drain electrode; forming the dielectric etch stop layer on the ﬁrst dielectric layer using a metal oxide dielectric layer; and forming the capping dielectric layer on the dielectric etch stop layer using a second dielectric layer of silicon nitride.
5. 8
  Dependent← claim 1GaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, where selectively forming the continuous multi-region ﬁeld plate comprises forming the continuous multi-region ﬁeld plate in contact with the dielectric etch stop layer at a ﬁrst plate region and in contact with the capping dielectric layer at a second plate region, where the ﬁrst and second plate regions are located at diﬀerent distances from the substrate.
6. 10
  Dependent← claim 1GaN HFET with multi-region field plate (method claim 1)
  The method of claim 1, further comprising: forming a second plurality of dielectric layers over the multi-region ﬁeld plate opening and the gate, drain, and source electrodes prior to depositing the conductor layer, where the second plurality of dielectric layers comprises a second dielectric etch stop layer formed over the ﬁrst capping dielectric layer and a second capping dielectric layer formed over the second dielectric etch stop layer; and forming the multi-region ﬁeld plate opening by selectively etching the second capping dielectric layer in a third sub-region between the gate electrode and drain electrode using the second dielectric etch stop layer as an etch stop layer.
11
IndependentGaN transistor with continuous multi-region field plate (method claim 11)
A method for forming a transistor comprising: forming a ﬁrst dielectric layer over a substrate; forming conductive gate and drain electrode structures in ohmic contact with the substrate after forming ﬁrst and second openings in the ﬁrst dielectric layer; forming a plurality of passivation layers over the conductive gate and drain electrode structures to provide a passivation stack, where the plurality of passivation layers comprises a ﬁrst dielectric etch stop layer and a ﬁrst capping dielectric layer formed over the ﬁrst dielectric etch stop layer; selectively etching the passivation stack down to the ﬁrst dielectric etch stop layer to remove the ﬁrst capping dielectric layer from a ﬁrst region which overlaps with the gate electrode structure and extends partway toward the drain electrode structure, thereby forming a ﬁrst opening in the ﬁrst capping dielectric layer; and selectively forming one or more conductive layers in the ﬁrst opening and over at least a portion of the ﬁrst capping dielectric layer wherein a continuous ﬁeld plate is formed from the one or more conductive layers that shields the gate electrode from the drain electrode, where the ﬁeld plate comprises a ﬁrst region separated from the substrate by a ﬁrst distance and a second region separated from the substrate by a second distance.
1. 12
  Dependent← claim 11GaNGaN transistor with continuous multi-region field plate (method claim 11)
  The method of claim 11, where the substrate comprises a gallium nitride layer.
2. 14
  Dependent← claim 11metal oxide dielectricSi₃N₄GaN transistor with continuous multi-region field plate (method claim 11)
  The method of claim 11, where forming plurality of passivation layers comprises: forming the ﬁrst dielectric etch stop layer with a metal oxide dielectric layer; and forming the ﬁrst capping dielectric layer using a layer of silicon nitride.
3. 17
  Dependent← claim 11GaN transistor with continuous multi-region field plate (method claim 11)
  The method of claim 11, further comprising thinning the passivation stack after forming the continuous ﬁeld plate by selectively etching the ﬁrst capping dielectric layer in one or more regions adjacent to the continuous ﬁeld plate.
4. 18
  Dependent← claim 11GaN transistor with continuous multi-region field plate (method claim 11)
  The method of claim 11, further comprising: forming a second plurality of passivation layers over the ﬁeld plate opening and the conductive gate and drain electrode structures prior to depositing one or more conductive layers to provide a second passivation stack comprising a second capping dielectric layer formed over a second dielectric etch stop layer; and forming the ﬁeld plate opening by selectively etching the second capping dielectric layer in a second region between the gate electrode and drain electrode using the second dielectric etch stop layer as an etch stop layer.
5. 19
  Dependent← claim 11GaN transistor with continuous multi-region field plate (method claim 11)
  The method of claim 11, where selectively forming one or more conductive layers comprises: depositing one or more conductor layers in in the ﬁrst opening and over at least the portion of the ﬁrst capping dielectric layer; and 5 selectively etching the one or more conductor layers to form the continuous ﬁeld plate in the ﬁrst opening and over at least the portion of the ﬁrst capping dielectric layer between the conductive gate and drain electrode structures.
20
IndependentGaNGaN transistor device with continuous field plate (device claim 20)
A gallium nitride transistor device, comprising: a substrate comprising a gallium nitride layer; a passivation surface layer covering the gallium nitride layer with a gate electrode opening formed therein; a conductive gate electrode located in the gate electrode opening to be in contact with the gallium nitride layer; a passivation stack formed over the substrate comprising a ﬁrst dielectric etch stop layer formed on the conductive gate electrode and passivation surface layer between the conductive gate and a drain electrode, and a ﬁrst capping dielectric layer formed over the ﬁrst dielectric etch stop layer with a ﬁrst opening formed in the ﬁrst capping dielectric layer which overlaps with the conductive gate electrode and extends partway toward the drain electrode; and a continuous ﬁeld plate comprising a portion in the ﬁrst opening and over at least part of the ﬁrst capping dielectric layer comprising a ﬁrst region separated from the substrate by a ﬁrst distance and a second region separated from the substrate by a second distance. withdrawn
1. 21
  Dependent← claim 20Al₂O₃Si₃N₄GaN transistor device with continuous field plate (device claim 20)
  The gallium nitride transistor device of claim 20, where the ﬁrst dielectric etch stop layer comprises aluminum oxide, and the ﬁrst capping dielectric layer comprises silicon nitride. withdrawn
2. 22
  Dependent← claim 20GaN transistor device with continuous field plate (device claim 20)
  The gallium nitride transistor device of claim 20, where the passivation stack comprises a second dielectric etch stop layer formed over the ﬁrst capping dielectric layer and a second capping dielectric layer formed over the second dielectric etch stop layer with a second opening formed in the second capping dielectric layer; and where the continuous ﬁeld plate formed in the ﬁrst opening and over at least part of the ﬁrst capping dielectric layer is also formed in the second opening and over at least 6 part of the second capping dielectric layer, such that the continuous ﬁeld plate comprises the ﬁrst region separated from the substrate by a ﬁrst distance, the second region separated from the substrate by a second distance, and a third region separated from the substrate by a third distance. 7 withdrawn

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

GaN HFET with multi-region field plate (method claim 1)

Si₃N₄capping dielectric layer

metal oxide dielectricdielectric etch stop layer

dielectric surface layerpassivation surface layer

GaNsubstrate

GaN transistor with continuous multi-region field plate (method claim 11)

Si₃N₄first capping dielectric layer

Materials

Materials described outside the worked examples.

gallium nitride

GaN

Semiconductor Substrate Layer

Buffer LayerSurface Termination Cap Layer

silicon nitride

Si₃N₄

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
Thickness	5–20 µm	—
Thickness	0.3–2 µm

Why these are connected

Related documents with shared materials, methods, properties, or citations.

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