Patent
Atlas literature
Patent
US 12,336,233 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIG. 2 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIGS. 3A-3H depict processes that may be used for form the semiconductor devices of
FIG. 4 (related art) shows a related art technique for forming a p-doped GaN layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride-based semiconductor device, comprising: a substrate; a first nitride-based semiconductor layer disposed over the substrate; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunc-tion therebetween with a two-dimensional electron gas (2DEG) region; a doped III-V nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and having a substantially inverted trapezoidal cross-sec-tional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semiconductor layer, wherein a length of an orthogonal projection of the first surface on the second nitride-based semicon-ductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; a gate electrode disposed on or above the doped III-V semiconductor layer and positioned on or above the second surface; at least two source/drain (S/D) electrodes disposed over the second nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising a first dielectric layer positioned above the second nitride-based semiconductor layer and extending to edges of the doped III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising one or more field plates.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises one or more of tita-nium, tantalum, tungsten, aluminum, cobalt, copper, nickel, platinum, lead, molybdenum, titanium nitride, tantalum nitride.
The nitride-based semiconductor device of claim 1, wherein the first nitride-based semiconductor layer includes gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the second nitride-based semiconductor layer includes aluminum gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface. ∗ ∗ ∗ ∗ ∗
A method for manufacturing a nitride-based semicon-ductor device, comprising: forming a first nitride-based semiconductor layer over a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a band-gap greater than a bandgap of the first nitride-based semiconductor layer; forming a dielectric hard mask layer over the second nitride-based semiconductor layer; creating an opening in the hard mask layer, the opening having an inverted trapezoid cross-sectional shape; depositing a doped nitride-based semiconductor material layer in the opening in the hard mask layer; masking the doped nitride-based semiconductor material layer in the region over the opening in the hard mask layer; etching the doped nitride-based semiconductor material layer to form a doped nitride-based semiconductor layer, wherein the doped nitride-based semiconductor layer has a substantially inverted trapezoidal cross-sectional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semicon-ductor layer, a length of an orthogonal projection of the first surface on the second nitride-based semiconductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; forming two or more source/drain (S/D) electrodes on or over the second nitride-based semiconductor layer; and forming a gate electrode on or over the doped nitride-based semiconductor layer, positioned on or above the second surface, and between the S/D electrodes.
The method of claim 10, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with inverted trapezoidal p-doped gate layer
Materials described outside the worked examples.
first nitride-based semiconductor layer (GaN)
GaN
second nitride-based semiconductor layer (AlGaN)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 10
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,336,233 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIG. 2 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIGS. 3A-3H depict processes that may be used for form the semiconductor devices of
FIG. 4 (related art) shows a related art technique for forming a p-doped GaN layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride-based semiconductor device, comprising: a substrate; a first nitride-based semiconductor layer disposed over the substrate; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunc-tion therebetween with a two-dimensional electron gas (2DEG) region; a doped III-V nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and having a substantially inverted trapezoidal cross-sec-tional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semiconductor layer, wherein a length of an orthogonal projection of the first surface on the second nitride-based semicon-ductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; a gate electrode disposed on or above the doped III-V semiconductor layer and positioned on or above the second surface; at least two source/drain (S/D) electrodes disposed over the second nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising a first dielectric layer positioned above the second nitride-based semiconductor layer and extending to edges of the doped III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising one or more field plates.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises one or more of tita-nium, tantalum, tungsten, aluminum, cobalt, copper, nickel, platinum, lead, molybdenum, titanium nitride, tantalum nitride.
The nitride-based semiconductor device of claim 1, wherein the first nitride-based semiconductor layer includes gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the second nitride-based semiconductor layer includes aluminum gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface. ∗ ∗ ∗ ∗ ∗
A method for manufacturing a nitride-based semicon-ductor device, comprising: forming a first nitride-based semiconductor layer over a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a band-gap greater than a bandgap of the first nitride-based semiconductor layer; forming a dielectric hard mask layer over the second nitride-based semiconductor layer; creating an opening in the hard mask layer, the opening having an inverted trapezoid cross-sectional shape; depositing a doped nitride-based semiconductor material layer in the opening in the hard mask layer; masking the doped nitride-based semiconductor material layer in the region over the opening in the hard mask layer; etching the doped nitride-based semiconductor material layer to form a doped nitride-based semiconductor layer, wherein the doped nitride-based semiconductor layer has a substantially inverted trapezoidal cross-sectional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semicon-ductor layer, a length of an orthogonal projection of the first surface on the second nitride-based semiconductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; forming two or more source/drain (S/D) electrodes on or over the second nitride-based semiconductor layer; and forming a gate electrode on or over the doped nitride-based semiconductor layer, positioned on or above the second surface, and between the S/D electrodes.
The method of claim 10, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with inverted trapezoidal p-doped gate layer
Materials described outside the worked examples.
first nitride-based semiconductor layer (GaN)
GaN
second nitride-based semiconductor layer (AlGaN)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 10
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,336,233 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIG. 2 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIGS. 3A-3H depict processes that may be used for form the semiconductor devices of
FIG. 4 (related art) shows a related art technique for forming a p-doped GaN layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride-based semiconductor device, comprising: a substrate; a first nitride-based semiconductor layer disposed over the substrate; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunc-tion therebetween with a two-dimensional electron gas (2DEG) region; a doped III-V nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and having a substantially inverted trapezoidal cross-sec-tional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semiconductor layer, wherein a length of an orthogonal projection of the first surface on the second nitride-based semicon-ductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; a gate electrode disposed on or above the doped III-V semiconductor layer and positioned on or above the second surface; at least two source/drain (S/D) electrodes disposed over the second nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising a first dielectric layer positioned above the second nitride-based semiconductor layer and extending to edges of the doped III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising one or more field plates.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises one or more of tita-nium, tantalum, tungsten, aluminum, cobalt, copper, nickel, platinum, lead, molybdenum, titanium nitride, tantalum nitride.
The nitride-based semiconductor device of claim 1, wherein the first nitride-based semiconductor layer includes gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the second nitride-based semiconductor layer includes aluminum gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface. ∗ ∗ ∗ ∗ ∗
A method for manufacturing a nitride-based semicon-ductor device, comprising: forming a first nitride-based semiconductor layer over a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a band-gap greater than a bandgap of the first nitride-based semiconductor layer; forming a dielectric hard mask layer over the second nitride-based semiconductor layer; creating an opening in the hard mask layer, the opening having an inverted trapezoid cross-sectional shape; depositing a doped nitride-based semiconductor material layer in the opening in the hard mask layer; masking the doped nitride-based semiconductor material layer in the region over the opening in the hard mask layer; etching the doped nitride-based semiconductor material layer to form a doped nitride-based semiconductor layer, wherein the doped nitride-based semiconductor layer has a substantially inverted trapezoidal cross-sectional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semicon-ductor layer, a length of an orthogonal projection of the first surface on the second nitride-based semiconductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; forming two or more source/drain (S/D) electrodes on or over the second nitride-based semiconductor layer; and forming a gate electrode on or over the doped nitride-based semiconductor layer, positioned on or above the second surface, and between the S/D electrodes.
The method of claim 10, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with inverted trapezoidal p-doped gate layer
Materials described outside the worked examples.
first nitride-based semiconductor layer (GaN)
GaN
second nitride-based semiconductor layer (AlGaN)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 10
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,336,233 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIG. 2 is a side cross-sectional view of a semiconductor device according to some embodiments of the present dis- closure;
FIGS. 3A-3H depict processes that may be used for form the semiconductor devices of
FIG. 4 (related art) shows a related art technique for forming a p-doped GaN layer.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nitride-based semiconductor device, comprising: a substrate; a first nitride-based semiconductor layer disposed over the substrate; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunc-tion therebetween with a two-dimensional electron gas (2DEG) region; a doped III-V nitride-based semiconductor layer disposed over the second nitride-based semiconductor layer and having a substantially inverted trapezoidal cross-sec-tional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semiconductor layer, wherein a length of an orthogonal projection of the first surface on the second nitride-based semicon-ductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; a gate electrode disposed on or above the doped III-V semiconductor layer and positioned on or above the second surface; at least two source/drain (S/D) electrodes disposed over the second nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising a first dielectric layer positioned above the second nitride-based semiconductor layer and extending to edges of the doped III-V nitride-based semiconductor layer.
The nitride-based semiconductor device of claim 1, further comprising one or more field plates.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises one or more of tita-nium, tantalum, tungsten, aluminum, cobalt, copper, nickel, platinum, lead, molybdenum, titanium nitride, tantalum nitride.
The nitride-based semiconductor device of claim 1, wherein the first nitride-based semiconductor layer includes gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the second nitride-based semiconductor layer includes aluminum gallium nitride.
The nitride-based semiconductor device of claim 1, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface. ∗ ∗ ∗ ∗ ∗
A method for manufacturing a nitride-based semicon-ductor device, comprising: forming a first nitride-based semiconductor layer over a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, wherein the second nitride-based semiconductor layer has a band-gap greater than a bandgap of the first nitride-based semiconductor layer; forming a dielectric hard mask layer over the second nitride-based semiconductor layer; creating an opening in the hard mask layer, the opening having an inverted trapezoid cross-sectional shape; depositing a doped nitride-based semiconductor material layer in the opening in the hard mask layer; masking the doped nitride-based semiconductor material layer in the region over the opening in the hard mask layer; etching the doped nitride-based semiconductor material layer to form a doped nitride-based semiconductor layer, wherein the doped nitride-based semiconductor layer has a substantially inverted trapezoidal cross-sectional shape that has a first surface close to the second nitride-based semiconductor layer and a second surface away from the second nitride-based semicon-ductor layer, a length of an orthogonal projection of the first surface on the second nitride-based semiconductor layer is less than a length of an orthogonal projection of the second surface on the second nitride-based semiconductor layer, and a width of the cross-sectional shape decreases as the distance away from the second surface increases; forming two or more source/drain (S/D) electrodes on or over the second nitride-based semiconductor layer; and forming a gate electrode on or over the doped nitride-based semiconductor layer, positioned on or above the second surface, and between the S/D electrodes.
The method of claim 10, wherein the gate electrode comprises a first part in contact with the second surface, and a second part connected to the first part and separated from the second surface, and the second part extends from the first part beyond the second surface.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based HEMT with inverted trapezoidal p-doped gate layer
Materials described outside the worked examples.
first nitride-based semiconductor layer (GaN)
GaN
second nitride-based semiconductor layer (AlGaN)
AlGaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 3.4 eV | GaN |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 10
Related documents with shared materials, methods, properties, or citations.
doped III-V nitride-based semiconductor layer
dielectric hard mask layer/first dielectric layer
second dielectric layer
third dielectric layer
gate electrode metal(s)
AlGaN barrier layer
AlxGa(1-x)N
substrate
nucleation/buffer layer (AlN)
AlN
| 4 eV |
AlxGa(1-x)N |
Cited non-patent literature · 1
doped III-V nitride-based semiconductor layer
dielectric hard mask layer/first dielectric layer
second dielectric layer
third dielectric layer
gate electrode metal(s)
AlGaN barrier layer
AlxGa(1-x)N
substrate
nucleation/buffer layer (AlN)
AlN
| 4 eV |
AlxGa(1-x)N |
Cited non-patent literature · 1
doped III-V nitride-based semiconductor layer
dielectric hard mask layer/first dielectric layer
second dielectric layer
third dielectric layer
gate electrode metal(s)
AlGaN barrier layer
AlxGa(1-x)N
substrate
nucleation/buffer layer (AlN)
AlN
| 4 eV |
AlxGa(1-x)N |
Cited non-patent literature · 1
doped III-V nitride-based semiconductor layer
dielectric hard mask layer/first dielectric layer
second dielectric layer
third dielectric layer
gate electrode metal(s)
AlGaN barrier layer
AlxGa(1-x)N
substrate
nucleation/buffer layer (AlN)
AlN
| 4 eV |
AlxGa(1-x)N |
Cited non-patent literature · 1
