Patent
US 9,601,608A STRUCTURE FOR A GALLIUM NITRIDE (GaN) HIGH ELECTRON MOBILITY TRANSISTOR
Ming-Wei Tsai
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,601,608Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor (HEM T) device comprising: a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; a gate structure arranged over a gate region of the barrier layer, the gate structure including a gate arranged over a cap, wherein the cap is disposed on the barrier layer and comprises a planar upper surface, wherein the planar upper surface that extends laterally between opposing sidewalls of the cap that underlie the planar upper surface, and wherein the gate protrudes towards the cap to culminate at a lower surface overlying the planar upper surface; and a gate protection layer arranged along the sidewalls of the cap, and arranged below the gate, wherein the gate protection layer continuously covers the planar upper surface to separate the planar upper surface of the cap and the lower surface of the gate.
The HEMT according to claim 1, wherein the gate protection layer is further arranged along sidewalls of the gate.
The HEM T according to claim 1, wherein the gate protection layer includes aluminum nitride or aluminum oxide.
The HEMT according to claim 1, wherein the cap includes doped gallium nitride.
The HEM T according to claim 1, further including: a passivation layer arranged over the gate protection layer, wherein the gate extends orthogonal to the planar upper surface, through the passivation layer, to the lower surface of the gate, wherein the lower surface of the gate underlies a lower surface of the passivation layer.
The HEM T according to claim 1, wherein the lower surface is planar and directly contacts the gate protection layer, and wherein the gate protection layer extends continuously from a first side of the lower surface to a second side of the lower surface that opposes the first side.
The HEMT according to claim 1, wherein the HEMT further comprises a pair of source/drain contacts respectively arranged on opposite sides of the gate, wherein an entire profile of the cap is rectangular, and wherein a bottom surface of the cap overlies a top surface of the barrier layer.
The HEMT according to claim 1, wherein a region of the gate protection layer arranged over the planar upper surface of the cap includes a recessed surface that is recessed below a top surface of the region and that contacts the lower surface of the gate, and wherein the recessed surface is laterally spaced from ends of the of the region.
canceled
canceled
The HEMT according to claim [[9]] 1, further including: a first source/drain contact and a second source/drain contact arranged on opposin g sides of the g ate structure, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier laver; and a capping layer covering the first and second source/drain contacts and the gate protection layer, wherein the gate protection layer extends partially over the capping layer, and wherein the gate extends orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
A method for manufacturing a high-electron mobility transistor (HEMT) device, said method comprising: providing a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 4 forming a cap over the barrier layer and comprising a planar upper surface that extends laterally between opposing sidewalls of the cap; forming a gate protection layer over, and along the sidewalls of, the cap; forming a gate opening over the cap and the gate protection layer, the gate opening extending into the gate protection layer, but not into the cap; forming a second gate protection layer lining sidewalls of the gate opening; forming source/drain contacts on opposing sides of the cap; forming a capping layer covering the gate protection layer and the source/drain contacts; and forming a gate over the cap and the gate protection layer, and further in the gate opening between the lined sidewalls of the gate opening, wherein the gate extends from over the capping layer, through the capping layer, and culminates at a lower surface overlying the planar upper surface.
The method according to claim 10, further including: forming the gate protection layer from aluminum nitride or aluminum oxide.
The method according to claim 10, further including: forming the gate protection layer with a thickness of about 5 to about 500 Angstroms.
The method according to claim 10, further including: forming the channel layer with gallium nitride.
The method according to claim 10, further including: forming the cap with doped gallium nitride. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page
The method according to claim 10, further including: forming a passivation layer over the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the passivation layer, to the lower surface.
The method according to claim 10, wherein forming the source/drain contacts comprises forming a first source/drain contact and a second source/drain contact arranged on opposing sides of the cap, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier layer, and wherein the method further comprises: forming the capping layer covering the first and second source/drain contacts and the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
canceled
canceled
A gallium nitride (GaN) enhancement mode transistor comprising: a substrate having a GaN layer arranged over the substrate and having an aluminum gallium nitride (AIGaN) layer arranged over the GaN layer, wherein the GaN and AIGaN layers define a heterojunction; a gate structure arranged over a gate region of the AIGaN layer, the gate structure including a metal gate arranged over a doped GaN cap, wherein the metal gate comprises a bottommost point arranged over a topmost point of the doped GaN cap 1 P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 6 wherein the bottommost point of the metal p ate is bottommost for a whole of the metal p ate, and wherein the topmost point of the doped GaN cap is topmost for a whole of the doped GaN cap; and an aluminum nitride or aluminum oxide gate protection layer arranged along sidewalls of the doped GaN cap and continuously along a top surface of the doped GaN cap to space the topmost point from the bottommost point.
The GaN enhancement mode transistor according to claim 20, further comprising: a passivation layer covering the aluminum nitride or aluminum oxide gate protection layer; a pair of source/drain contacts that are laterally spaced on opposing sides of the gate structure and that extend through the passivation layer from over the passivation layer; and a capping layer covering the source/drain contacts and the passivation layer, wherein the metal gate extends from over the capping layer, through the capping and passivation layers, to culminate at a lower surface that includes the bottommost point.
The GaN enhancement mode transistor according to claim 20, wherein the top surface of the doped GaN cap is planar and arranged at the topmost point, wherein the metal gate comprises a planar bottom surface arranged at the bottommost point, and wherein the aluminum nitride or aluminum oxide gate protection layer directly contacts the top surface and the planar bottom surface. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 7
Layer stacks claimed or described, ordered top of device to substrate.
high-electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate protection layer thickness (claimed range) | 5–500 Angstrom | gate protection layer |
passivation layer thickness | 50–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,601,608Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor (HEM T) device comprising: a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; a gate structure arranged over a gate region of the barrier layer, the gate structure including a gate arranged over a cap, wherein the cap is disposed on the barrier layer and comprises a planar upper surface, wherein the planar upper surface that extends laterally between opposing sidewalls of the cap that underlie the planar upper surface, and wherein the gate protrudes towards the cap to culminate at a lower surface overlying the planar upper surface; and a gate protection layer arranged along the sidewalls of the cap, and arranged below the gate, wherein the gate protection layer continuously covers the planar upper surface to separate the planar upper surface of the cap and the lower surface of the gate.
The HEMT according to claim 1, wherein the gate protection layer is further arranged along sidewalls of the gate.
The HEM T according to claim 1, wherein the gate protection layer includes aluminum nitride or aluminum oxide.
The HEMT according to claim 1, wherein the cap includes doped gallium nitride.
The HEM T according to claim 1, further including: a passivation layer arranged over the gate protection layer, wherein the gate extends orthogonal to the planar upper surface, through the passivation layer, to the lower surface of the gate, wherein the lower surface of the gate underlies a lower surface of the passivation layer.
The HEM T according to claim 1, wherein the lower surface is planar and directly contacts the gate protection layer, and wherein the gate protection layer extends continuously from a first side of the lower surface to a second side of the lower surface that opposes the first side.
The HEMT according to claim 1, wherein the HEMT further comprises a pair of source/drain contacts respectively arranged on opposite sides of the gate, wherein an entire profile of the cap is rectangular, and wherein a bottom surface of the cap overlies a top surface of the barrier layer.
The HEMT according to claim 1, wherein a region of the gate protection layer arranged over the planar upper surface of the cap includes a recessed surface that is recessed below a top surface of the region and that contacts the lower surface of the gate, and wherein the recessed surface is laterally spaced from ends of the of the region.
canceled
canceled
The HEMT according to claim [[9]] 1, further including: a first source/drain contact and a second source/drain contact arranged on opposin g sides of the g ate structure, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier laver; and a capping layer covering the first and second source/drain contacts and the gate protection layer, wherein the gate protection layer extends partially over the capping layer, and wherein the gate extends orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
A method for manufacturing a high-electron mobility transistor (HEMT) device, said method comprising: providing a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 4 forming a cap over the barrier layer and comprising a planar upper surface that extends laterally between opposing sidewalls of the cap; forming a gate protection layer over, and along the sidewalls of, the cap; forming a gate opening over the cap and the gate protection layer, the gate opening extending into the gate protection layer, but not into the cap; forming a second gate protection layer lining sidewalls of the gate opening; forming source/drain contacts on opposing sides of the cap; forming a capping layer covering the gate protection layer and the source/drain contacts; and forming a gate over the cap and the gate protection layer, and further in the gate opening between the lined sidewalls of the gate opening, wherein the gate extends from over the capping layer, through the capping layer, and culminates at a lower surface overlying the planar upper surface.
The method according to claim 10, further including: forming the gate protection layer from aluminum nitride or aluminum oxide.
The method according to claim 10, further including: forming the gate protection layer with a thickness of about 5 to about 500 Angstroms.
The method according to claim 10, further including: forming the channel layer with gallium nitride.
The method according to claim 10, further including: forming the cap with doped gallium nitride. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page
The method according to claim 10, further including: forming a passivation layer over the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the passivation layer, to the lower surface.
The method according to claim 10, wherein forming the source/drain contacts comprises forming a first source/drain contact and a second source/drain contact arranged on opposing sides of the cap, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier layer, and wherein the method further comprises: forming the capping layer covering the first and second source/drain contacts and the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
canceled
canceled
A gallium nitride (GaN) enhancement mode transistor comprising: a substrate having a GaN layer arranged over the substrate and having an aluminum gallium nitride (AIGaN) layer arranged over the GaN layer, wherein the GaN and AIGaN layers define a heterojunction; a gate structure arranged over a gate region of the AIGaN layer, the gate structure including a metal gate arranged over a doped GaN cap, wherein the metal gate comprises a bottommost point arranged over a topmost point of the doped GaN cap 1 P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 6 wherein the bottommost point of the metal p ate is bottommost for a whole of the metal p ate, and wherein the topmost point of the doped GaN cap is topmost for a whole of the doped GaN cap; and an aluminum nitride or aluminum oxide gate protection layer arranged along sidewalls of the doped GaN cap and continuously along a top surface of the doped GaN cap to space the topmost point from the bottommost point.
The GaN enhancement mode transistor according to claim 20, further comprising: a passivation layer covering the aluminum nitride or aluminum oxide gate protection layer; a pair of source/drain contacts that are laterally spaced on opposing sides of the gate structure and that extend through the passivation layer from over the passivation layer; and a capping layer covering the source/drain contacts and the passivation layer, wherein the metal gate extends from over the capping layer, through the capping and passivation layers, to culminate at a lower surface that includes the bottommost point.
The GaN enhancement mode transistor according to claim 20, wherein the top surface of the doped GaN cap is planar and arranged at the topmost point, wherein the metal gate comprises a planar bottom surface arranged at the bottommost point, and wherein the aluminum nitride or aluminum oxide gate protection layer directly contacts the top surface and the planar bottom surface. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 7
Layer stacks claimed or described, ordered top of device to substrate.
high-electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate protection layer thickness (claimed range) | 5–500 Angstrom | gate protection layer |
passivation layer thickness | 50–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,601,608Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor (HEM T) device comprising: a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; a gate structure arranged over a gate region of the barrier layer, the gate structure including a gate arranged over a cap, wherein the cap is disposed on the barrier layer and comprises a planar upper surface, wherein the planar upper surface that extends laterally between opposing sidewalls of the cap that underlie the planar upper surface, and wherein the gate protrudes towards the cap to culminate at a lower surface overlying the planar upper surface; and a gate protection layer arranged along the sidewalls of the cap, and arranged below the gate, wherein the gate protection layer continuously covers the planar upper surface to separate the planar upper surface of the cap and the lower surface of the gate.
The HEMT according to claim 1, wherein the gate protection layer is further arranged along sidewalls of the gate.
The HEM T according to claim 1, wherein the gate protection layer includes aluminum nitride or aluminum oxide.
The HEMT according to claim 1, wherein the cap includes doped gallium nitride.
The HEM T according to claim 1, further including: a passivation layer arranged over the gate protection layer, wherein the gate extends orthogonal to the planar upper surface, through the passivation layer, to the lower surface of the gate, wherein the lower surface of the gate underlies a lower surface of the passivation layer.
The HEM T according to claim 1, wherein the lower surface is planar and directly contacts the gate protection layer, and wherein the gate protection layer extends continuously from a first side of the lower surface to a second side of the lower surface that opposes the first side.
The HEMT according to claim 1, wherein the HEMT further comprises a pair of source/drain contacts respectively arranged on opposite sides of the gate, wherein an entire profile of the cap is rectangular, and wherein a bottom surface of the cap overlies a top surface of the barrier layer.
The HEMT according to claim 1, wherein a region of the gate protection layer arranged over the planar upper surface of the cap includes a recessed surface that is recessed below a top surface of the region and that contacts the lower surface of the gate, and wherein the recessed surface is laterally spaced from ends of the of the region.
canceled
canceled
The HEMT according to claim [[9]] 1, further including: a first source/drain contact and a second source/drain contact arranged on opposin g sides of the g ate structure, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier laver; and a capping layer covering the first and second source/drain contacts and the gate protection layer, wherein the gate protection layer extends partially over the capping layer, and wherein the gate extends orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
A method for manufacturing a high-electron mobility transistor (HEMT) device, said method comprising: providing a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 4 forming a cap over the barrier layer and comprising a planar upper surface that extends laterally between opposing sidewalls of the cap; forming a gate protection layer over, and along the sidewalls of, the cap; forming a gate opening over the cap and the gate protection layer, the gate opening extending into the gate protection layer, but not into the cap; forming a second gate protection layer lining sidewalls of the gate opening; forming source/drain contacts on opposing sides of the cap; forming a capping layer covering the gate protection layer and the source/drain contacts; and forming a gate over the cap and the gate protection layer, and further in the gate opening between the lined sidewalls of the gate opening, wherein the gate extends from over the capping layer, through the capping layer, and culminates at a lower surface overlying the planar upper surface.
The method according to claim 10, further including: forming the gate protection layer from aluminum nitride or aluminum oxide.
The method according to claim 10, further including: forming the gate protection layer with a thickness of about 5 to about 500 Angstroms.
The method according to claim 10, further including: forming the channel layer with gallium nitride.
The method according to claim 10, further including: forming the cap with doped gallium nitride. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page
The method according to claim 10, further including: forming a passivation layer over the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the passivation layer, to the lower surface.
The method according to claim 10, wherein forming the source/drain contacts comprises forming a first source/drain contact and a second source/drain contact arranged on opposing sides of the cap, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier layer, and wherein the method further comprises: forming the capping layer covering the first and second source/drain contacts and the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
canceled
canceled
A gallium nitride (GaN) enhancement mode transistor comprising: a substrate having a GaN layer arranged over the substrate and having an aluminum gallium nitride (AIGaN) layer arranged over the GaN layer, wherein the GaN and AIGaN layers define a heterojunction; a gate structure arranged over a gate region of the AIGaN layer, the gate structure including a metal gate arranged over a doped GaN cap, wherein the metal gate comprises a bottommost point arranged over a topmost point of the doped GaN cap 1 P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 6 wherein the bottommost point of the metal p ate is bottommost for a whole of the metal p ate, and wherein the topmost point of the doped GaN cap is topmost for a whole of the doped GaN cap; and an aluminum nitride or aluminum oxide gate protection layer arranged along sidewalls of the doped GaN cap and continuously along a top surface of the doped GaN cap to space the topmost point from the bottommost point.
The GaN enhancement mode transistor according to claim 20, further comprising: a passivation layer covering the aluminum nitride or aluminum oxide gate protection layer; a pair of source/drain contacts that are laterally spaced on opposing sides of the gate structure and that extend through the passivation layer from over the passivation layer; and a capping layer covering the source/drain contacts and the passivation layer, wherein the metal gate extends from over the capping layer, through the capping and passivation layers, to culminate at a lower surface that includes the bottommost point.
The GaN enhancement mode transistor according to claim 20, wherein the top surface of the doped GaN cap is planar and arranged at the topmost point, wherein the metal gate comprises a planar bottom surface arranged at the bottommost point, and wherein the aluminum nitride or aluminum oxide gate protection layer directly contacts the top surface and the planar bottom surface. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 7
Layer stacks claimed or described, ordered top of device to substrate.
high-electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate protection layer thickness (claimed range) | 5–500 Angstrom | gate protection layer |
passivation layer thickness | 50–500 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,601,608Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-electron mobility transistor (HEM T) device comprising: a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; a gate structure arranged over a gate region of the barrier layer, the gate structure including a gate arranged over a cap, wherein the cap is disposed on the barrier layer and comprises a planar upper surface, wherein the planar upper surface that extends laterally between opposing sidewalls of the cap that underlie the planar upper surface, and wherein the gate protrudes towards the cap to culminate at a lower surface overlying the planar upper surface; and a gate protection layer arranged along the sidewalls of the cap, and arranged below the gate, wherein the gate protection layer continuously covers the planar upper surface to separate the planar upper surface of the cap and the lower surface of the gate.
The HEMT according to claim 1, wherein the gate protection layer is further arranged along sidewalls of the gate.
The HEM T according to claim 1, wherein the gate protection layer includes aluminum nitride or aluminum oxide.
The HEMT according to claim 1, wherein the cap includes doped gallium nitride.
The HEM T according to claim 1, further including: a passivation layer arranged over the gate protection layer, wherein the gate extends orthogonal to the planar upper surface, through the passivation layer, to the lower surface of the gate, wherein the lower surface of the gate underlies a lower surface of the passivation layer.
The HEM T according to claim 1, wherein the lower surface is planar and directly contacts the gate protection layer, and wherein the gate protection layer extends continuously from a first side of the lower surface to a second side of the lower surface that opposes the first side.
The HEMT according to claim 1, wherein the HEMT further comprises a pair of source/drain contacts respectively arranged on opposite sides of the gate, wherein an entire profile of the cap is rectangular, and wherein a bottom surface of the cap overlies a top surface of the barrier layer.
The HEMT according to claim 1, wherein a region of the gate protection layer arranged over the planar upper surface of the cap includes a recessed surface that is recessed below a top surface of the region and that contacts the lower surface of the gate, and wherein the recessed surface is laterally spaced from ends of the of the region.
canceled
canceled
The HEMT according to claim [[9]] 1, further including: a first source/drain contact and a second source/drain contact arranged on opposin g sides of the g ate structure, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier laver; and a capping layer covering the first and second source/drain contacts and the gate protection layer, wherein the gate protection layer extends partially over the capping layer, and wherein the gate extends orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
A method for manufacturing a high-electron mobility transistor (HEMT) device, said method comprising: providing a substrate having a channel layer arranged over the substrate and having a barrier layer arranged over the channel layer, wherein the channel and barrier layers define a heterojunction; P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 4 forming a cap over the barrier layer and comprising a planar upper surface that extends laterally between opposing sidewalls of the cap; forming a gate protection layer over, and along the sidewalls of, the cap; forming a gate opening over the cap and the gate protection layer, the gate opening extending into the gate protection layer, but not into the cap; forming a second gate protection layer lining sidewalls of the gate opening; forming source/drain contacts on opposing sides of the cap; forming a capping layer covering the gate protection layer and the source/drain contacts; and forming a gate over the cap and the gate protection layer, and further in the gate opening between the lined sidewalls of the gate opening, wherein the gate extends from over the capping layer, through the capping layer, and culminates at a lower surface overlying the planar upper surface.
The method according to claim 10, further including: forming the gate protection layer from aluminum nitride or aluminum oxide.
The method according to claim 10, further including: forming the gate protection layer with a thickness of about 5 to about 500 Angstroms.
The method according to claim 10, further including: forming the channel layer with gallium nitride.
The method according to claim 10, further including: forming the cap with doped gallium nitride. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page
The method according to claim 10, further including: forming a passivation layer over the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the passivation layer, to the lower surface.
The method according to claim 10, wherein forming the source/drain contacts comprises forming a first source/drain contact and a second source/drain contact arranged on opposing sides of the cap, wherein the first and second source/drain contacts extend orthogonal to the planar upper surface to or otherwise into the barrier layer, and wherein the method further comprises: forming the capping layer covering the first and second source/drain contacts and the gate protection layer; and forming the gate extending orthogonal to the planar upper surface, through the capping layer, to the lower surface.
canceled
canceled
canceled
A gallium nitride (GaN) enhancement mode transistor comprising: a substrate having a GaN layer arranged over the substrate and having an aluminum gallium nitride (AIGaN) layer arranged over the GaN layer, wherein the GaN and AIGaN layers define a heterojunction; a gate structure arranged over a gate region of the AIGaN layer, the gate structure including a metal gate arranged over a doped GaN cap, wherein the metal gate comprises a bottommost point arranged over a topmost point of the doped GaN cap 1 P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 6 wherein the bottommost point of the metal p ate is bottommost for a whole of the metal p ate, and wherein the topmost point of the doped GaN cap is topmost for a whole of the doped GaN cap; and an aluminum nitride or aluminum oxide gate protection layer arranged along sidewalls of the doped GaN cap and continuously along a top surface of the doped GaN cap to space the topmost point from the bottommost point.
The GaN enhancement mode transistor according to claim 20, further comprising: a passivation layer covering the aluminum nitride or aluminum oxide gate protection layer; a pair of source/drain contacts that are laterally spaced on opposing sides of the gate structure and that extend through the passivation layer from over the passivation layer; and a capping layer covering the source/drain contacts and the passivation layer, wherein the metal gate extends from over the capping layer, through the capping and passivation layers, to culminate at a lower surface that includes the bottommost point.
The GaN enhancement mode transistor according to claim 20, wherein the top surface of the doped GaN cap is planar and arranged at the topmost point, wherein the metal gate comprises a planar bottom surface arranged at the bottommost point, and wherein the aluminum nitride or aluminum oxide gate protection layer directly contacts the top surface and the planar bottom surface. P₂₀₁₄₀₉₆₉ US00 App. No. 14/540,250 Page 7
Layer stacks claimed or described, ordered top of device to substrate.
high-electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
aluminum gallium nitride
AlGaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate protection layer thickness (claimed range) | 5–500 Angstrom | gate protection layer |
passivation layer thickness | 50–500 nm |
Related documents with shared materials, methods, properties, or citations.
GaN enhancement mode transistor
gate protection layer
aluminum nitride
AlN
aluminum oxide
Al₂O₃
passivation layer
silicon nitride
SiN
silicon carbide substrate
SiC
channel layer (GaN) thickness | 10 nm | GaN |
barrier layer (AlGaN) thickness | 15 nm | AlGaN |
AlGaN band gap | 4 eV | AlGaN |
GaN band gap | 3.4 eV | GaN |
Thickness | 5–500 Å | — |
GaN enhancement mode transistor
gate protection layer
aluminum nitride
AlN
aluminum oxide
Al₂O₃
passivation layer
silicon nitride
SiN
silicon carbide substrate
SiC
channel layer (GaN) thickness | 10 nm | GaN |
barrier layer (AlGaN) thickness | 15 nm | AlGaN |
AlGaN band gap | 4 eV | AlGaN |
GaN band gap | 3.4 eV | GaN |
Thickness | 5–500 Å | — |
GaN enhancement mode transistor
gate protection layer
aluminum nitride
AlN
aluminum oxide
Al₂O₃
passivation layer
silicon nitride
SiN
silicon carbide substrate
SiC
channel layer (GaN) thickness | 10 nm | GaN |
barrier layer (AlGaN) thickness | 15 nm | AlGaN |
AlGaN band gap | 4 eV | AlGaN |
GaN band gap | 3.4 eV | GaN |
Thickness | 5–500 Å | — |
GaN enhancement mode transistor
gate protection layer
aluminum nitride
AlN
aluminum oxide
Al₂O₃
passivation layer
silicon nitride
SiN
silicon carbide substrate
SiC
channel layer (GaN) thickness | 10 nm | GaN |
barrier layer (AlGaN) thickness | 15 nm | AlGaN |
AlGaN band gap | 4 eV | AlGaN |
GaN band gap | 3.4 eV | GaN |
Thickness | 5–500 Å | — |