Patent
US 8,487,356GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME
Jin seong Heo
US
Copyright © 2026 Matter42. All rights reserved.
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US 8,487,356Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 through 5 are cross-sectional views illustrating a graphene device according to example embodiments; and [0016]
FIG. 2. In detail, one end of the graphene channel 30 may be formed on an upper surface of one of the first and second electrodes 32 and 34, and other end of …
FIG. 3, and may extend on the first and second electrodes 32 and 34 along surfaces thereof. [0032]
FIG. 4 illustrates a graphene-based inverter as an example of a graphene device, according to example embodiments. Like reference numerals in the following …
FIG. 5 may be manufactured using a manufacturing method illustrated in F I GS. 6 through 9. [0045] l t should be understood that example embodiments described …
FIGS. 6 through 11 are cross-sectional views illustrating a method of manufacturing a graphene device according to example embodiments.
FIG. 7, an interlayer insulating layer 26 surrounding the first through third metal patterns 24A, 24 B, and 24 C may be formed on the lower oxide layer 22. The …
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
FIG. 9. The first and second electrodes 32 and 34 may be located outside of the first through third metal patterns 24A, 24 B, and 24 C. [0044]After the upper …
FIG. 10. As illustrated in
FIG. 11, the graphene channel 30 may be transferred on the first and second electrodes 32 and 34. In example embodiments, ends of the graphene channel 30 are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLAIMS 1. A graphene device, comprising: a plurality of embedded gates within an interla y er insu l atin g la v er on a substrate; an upper oxide layer on the interlayer insulati ng layer including the plurality of embedded gates; and a graphene channel and a plurality of electrodes on the upper oxide layer.
The graphene device of claim 1, wherein the plurality of electrodes are on the graphene channel.
The graphene device of claim 1, wherein the graphene channel is on the plurality of electrodes.
The graphene device of claim 1, wherein the graphene channel is on and between the plurality of electrodes.
The graphene device of claim 1, wherein the substrate includes a semiconductor substrate and an oxide layer which are sequentially stacked.
A method of manufacturing a graphene device, comprising: Application No. 13/307,370 Attorney Docket No. 2557S I -001462/US/COA Page 4 of 12 forming a plurality of embedded gates within an interla y er insulatin g la v er on a substrate; forming an upper oxide layer on the interlayer insulatinglayerinciding the plurality of embedded gates; and forming a graphene channel and a plurality of electrodes on the upper oxide layer.
The method of claim 13, wherein the plurality of electrodes are formed on the graphene channel.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes and on the upper oxide layer between the plurality of electrodes.
The method of claim 13, wherein the graphene device is an inverter.
A method of operating a graphene device comprising: providing a graphene channel and a plurality of electrodes on a plurality of embedded gates and at least one metal pattern between the plurality of electrodes, the at least one metal pattern corresponding with the plurality of embedded gates, an d the Application No. 13/307,370 Attorney Docket No. 2557 SI -001462/US/COA Page 6 of 12 plurality of e m bedded gat es bein g indep enden tly controllable; and applying different voltages to at least two of the plurality of electrodes and the at least one metal pattern, respectively.
The method of claim 26, wherein the voltage applied to one of the plurality of electrodes is a VDD voltage and the voltage applied to another of the plurality of electrodes is a ground voltage.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with embedded gates
graphene inverter
Materials described outside the worked examples.
graphene
interlayer insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,356Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 through 5 are cross-sectional views illustrating a graphene device according to example embodiments; and [0016]
FIG. 2. In detail, one end of the graphene channel 30 may be formed on an upper surface of one of the first and second electrodes 32 and 34, and other end of …
FIG. 3, and may extend on the first and second electrodes 32 and 34 along surfaces thereof. [0032]
FIG. 4 illustrates a graphene-based inverter as an example of a graphene device, according to example embodiments. Like reference numerals in the following …
FIG. 5 may be manufactured using a manufacturing method illustrated in F I GS. 6 through 9. [0045] l t should be understood that example embodiments described …
FIGS. 6 through 11 are cross-sectional views illustrating a method of manufacturing a graphene device according to example embodiments.
FIG. 7, an interlayer insulating layer 26 surrounding the first through third metal patterns 24A, 24 B, and 24 C may be formed on the lower oxide layer 22. The …
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
FIG. 9. The first and second electrodes 32 and 34 may be located outside of the first through third metal patterns 24A, 24 B, and 24 C. [0044]After the upper …
FIG. 10. As illustrated in
FIG. 11, the graphene channel 30 may be transferred on the first and second electrodes 32 and 34. In example embodiments, ends of the graphene channel 30 are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLAIMS 1. A graphene device, comprising: a plurality of embedded gates within an interla y er insu l atin g la v er on a substrate; an upper oxide layer on the interlayer insulati ng layer including the plurality of embedded gates; and a graphene channel and a plurality of electrodes on the upper oxide layer.
The graphene device of claim 1, wherein the plurality of electrodes are on the graphene channel.
The graphene device of claim 1, wherein the graphene channel is on the plurality of electrodes.
The graphene device of claim 1, wherein the graphene channel is on and between the plurality of electrodes.
The graphene device of claim 1, wherein the substrate includes a semiconductor substrate and an oxide layer which are sequentially stacked.
A method of manufacturing a graphene device, comprising: Application No. 13/307,370 Attorney Docket No. 2557S I -001462/US/COA Page 4 of 12 forming a plurality of embedded gates within an interla y er insulatin g la v er on a substrate; forming an upper oxide layer on the interlayer insulatinglayerinciding the plurality of embedded gates; and forming a graphene channel and a plurality of electrodes on the upper oxide layer.
The method of claim 13, wherein the plurality of electrodes are formed on the graphene channel.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes and on the upper oxide layer between the plurality of electrodes.
The method of claim 13, wherein the graphene device is an inverter.
A method of operating a graphene device comprising: providing a graphene channel and a plurality of electrodes on a plurality of embedded gates and at least one metal pattern between the plurality of electrodes, the at least one metal pattern corresponding with the plurality of embedded gates, an d the Application No. 13/307,370 Attorney Docket No. 2557 SI -001462/US/COA Page 6 of 12 plurality of e m bedded gat es bein g indep enden tly controllable; and applying different voltages to at least two of the plurality of electrodes and the at least one metal pattern, respectively.
The method of claim 26, wherein the voltage applied to one of the plurality of electrodes is a VDD voltage and the voltage applied to another of the plurality of electrodes is a ground voltage.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with embedded gates
graphene inverter
Materials described outside the worked examples.
graphene
interlayer insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,356Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 through 5 are cross-sectional views illustrating a graphene device according to example embodiments; and [0016]
FIG. 2. In detail, one end of the graphene channel 30 may be formed on an upper surface of one of the first and second electrodes 32 and 34, and other end of …
FIG. 3, and may extend on the first and second electrodes 32 and 34 along surfaces thereof. [0032]
FIG. 4 illustrates a graphene-based inverter as an example of a graphene device, according to example embodiments. Like reference numerals in the following …
FIG. 5 may be manufactured using a manufacturing method illustrated in F I GS. 6 through 9. [0045] l t should be understood that example embodiments described …
FIGS. 6 through 11 are cross-sectional views illustrating a method of manufacturing a graphene device according to example embodiments.
FIG. 7, an interlayer insulating layer 26 surrounding the first through third metal patterns 24A, 24 B, and 24 C may be formed on the lower oxide layer 22. The …
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
FIG. 9. The first and second electrodes 32 and 34 may be located outside of the first through third metal patterns 24A, 24 B, and 24 C. [0044]After the upper …
FIG. 10. As illustrated in
FIG. 11, the graphene channel 30 may be transferred on the first and second electrodes 32 and 34. In example embodiments, ends of the graphene channel 30 are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLAIMS 1. A graphene device, comprising: a plurality of embedded gates within an interla y er insu l atin g la v er on a substrate; an upper oxide layer on the interlayer insulati ng layer including the plurality of embedded gates; and a graphene channel and a plurality of electrodes on the upper oxide layer.
The graphene device of claim 1, wherein the plurality of electrodes are on the graphene channel.
The graphene device of claim 1, wherein the graphene channel is on the plurality of electrodes.
The graphene device of claim 1, wherein the graphene channel is on and between the plurality of electrodes.
The graphene device of claim 1, wherein the substrate includes a semiconductor substrate and an oxide layer which are sequentially stacked.
A method of manufacturing a graphene device, comprising: Application No. 13/307,370 Attorney Docket No. 2557S I -001462/US/COA Page 4 of 12 forming a plurality of embedded gates within an interla y er insulatin g la v er on a substrate; forming an upper oxide layer on the interlayer insulatinglayerinciding the plurality of embedded gates; and forming a graphene channel and a plurality of electrodes on the upper oxide layer.
The method of claim 13, wherein the plurality of electrodes are formed on the graphene channel.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes and on the upper oxide layer between the plurality of electrodes.
The method of claim 13, wherein the graphene device is an inverter.
A method of operating a graphene device comprising: providing a graphene channel and a plurality of electrodes on a plurality of embedded gates and at least one metal pattern between the plurality of electrodes, the at least one metal pattern corresponding with the plurality of embedded gates, an d the Application No. 13/307,370 Attorney Docket No. 2557 SI -001462/US/COA Page 6 of 12 plurality of e m bedded gat es bein g indep enden tly controllable; and applying different voltages to at least two of the plurality of electrodes and the at least one metal pattern, respectively.
The method of claim 26, wherein the voltage applied to one of the plurality of electrodes is a VDD voltage and the voltage applied to another of the plurality of electrodes is a ground voltage.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with embedded gates
graphene inverter
Materials described outside the worked examples.
graphene
interlayer insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,487,356Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 through 5 are cross-sectional views illustrating a graphene device according to example embodiments; and [0016]
FIG. 2. In detail, one end of the graphene channel 30 may be formed on an upper surface of one of the first and second electrodes 32 and 34, and other end of …
FIG. 3, and may extend on the first and second electrodes 32 and 34 along surfaces thereof. [0032]
FIG. 4 illustrates a graphene-based inverter as an example of a graphene device, according to example embodiments. Like reference numerals in the following …
FIG. 5 may be manufactured using a manufacturing method illustrated in F I GS. 6 through 9. [0045] l t should be understood that example embodiments described …
FIGS. 6 through 11 are cross-sectional views illustrating a method of manufacturing a graphene device according to example embodiments.
FIG. 7, an interlayer insulating layer 26 surrounding the first through third metal patterns 24A, 24 B, and 24 C may be formed on the lower oxide layer 22. The …
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
FIG. 9. The first and second electrodes 32 and 34 may be located outside of the first through third metal patterns 24A, 24 B, and 24 C. [0044]After the upper …
FIG. 10. As illustrated in
FIG. 11, the graphene channel 30 may be transferred on the first and second electrodes 32 and 34. In example embodiments, ends of the graphene channel 30 are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
LISTING OF CLAIMS 1. A graphene device, comprising: a plurality of embedded gates within an interla y er insu l atin g la v er on a substrate; an upper oxide layer on the interlayer insulati ng layer including the plurality of embedded gates; and a graphene channel and a plurality of electrodes on the upper oxide layer.
The graphene device of claim 1, wherein the plurality of electrodes are on the graphene channel.
The graphene device of claim 1, wherein the graphene channel is on the plurality of electrodes.
The graphene device of claim 1, wherein the graphene channel is on and between the plurality of electrodes.
The graphene device of claim 1, wherein the substrate includes a semiconductor substrate and an oxide layer which are sequentially stacked.
A method of manufacturing a graphene device, comprising: Application No. 13/307,370 Attorney Docket No. 2557S I -001462/US/COA Page 4 of 12 forming a plurality of embedded gates within an interla y er insulatin g la v er on a substrate; forming an upper oxide layer on the interlayer insulatinglayerinciding the plurality of embedded gates; and forming a graphene channel and a plurality of electrodes on the upper oxide layer.
The method of claim 13, wherein the plurality of electrodes are formed on the graphene channel.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes.
The method of claim 13, wherein the graphene channel is formed on the plurality of electrodes and on the upper oxide layer between the plurality of electrodes.
The method of claim 13, wherein the graphene device is an inverter.
A method of operating a graphene device comprising: providing a graphene channel and a plurality of electrodes on a plurality of embedded gates and at least one metal pattern between the plurality of electrodes, the at least one metal pattern corresponding with the plurality of embedded gates, an d the Application No. 13/307,370 Attorney Docket No. 2557 SI -001462/US/COA Page 6 of 12 plurality of e m bedded gat es bein g indep enden tly controllable; and applying different voltages to at least two of the plurality of electrodes and the at least one metal pattern, respectively.
The method of claim 26, wherein the voltage applied to one of the plurality of electrodes is a VDD voltage and the voltage applied to another of the plurality of electrodes is a ground voltage.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field-effect transistor with embedded gates
graphene inverter
Materials described outside the worked examples.
graphene
interlayer insulating layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8, an upper oxide layer 28 covering the first through third metal patterns 24A, 24B, and 24C may be formed on the interlayer insulating layer 26. The upper …
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