A method for manufacturing a thin film transistor (T FT) array substrate, comprising: forming a metal layer on a base substrate, and obtaining a gate line and a gate electrode through a first patterning process; forming a gate insulating layer on the gate li n e and the gate electrode; forming a graphene layer on the gate insulating layer and obtaining a semiconductor active layer formed of graphene over the gate electrode by a second patterning process and a hydrogenation treatment: obtaining a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphe n e, by a third patterning process on the graphene layer; wherein the source electrode contacts with the semiconductor active layer and the drain electrode contacts with the semiconductor active layer so as to define a TFT channel, and the pixel electrode contacts with the drain electrode; and forming a protection layer on the data li n e, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; forming a common electrode on the protection la y er and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode are located in a same layer, Pag e 2 of 9 Application Serial No. 13/704,704 PATENT Reply to final office action of March 4, 201 5 Docket: CU-70149 wh erein hfr mi n qof th gpnJ e on the g.In sil tn jyer and ~ obtaining of the semiconductor active layer for medof gr phone over the gatq electrode b y the se cond pat rand the hydr enation teatment comprises: depoitinq al yeafgrpaemat eri ga I eans of plasma enhanced chemical vao r de o sit i on or spin-c oati ng a wateralube iglaered mateia n the gate insulating Iayer s so as to form the graphene layer; coating photoresist on th graphe ne layer, and exp osin~g3raphe ne in the channel region after exposure and development; perforing the hyd roation treatment o" gr aphenein the channel regyon by using 1H₂ or a mixed gas of H₁₂ and Ar2; and removing the remainingptoresist, so a s to obtain the semiconductor active l ayer formed of graphene over the gate electrode.

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A thin film transistor (T FT) array substrate, comprising: a base substrate; a gate line and a gate electrode which are formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphene and formed on the gate insulating la y er; and a semiconductor active layer which is formed of graphene subject to a hydrogenation treatment and formed on the gate insulating layer; wherein the source electrode contacts with the semiconductor active layer, and the drain electrode contacts with the semiconductor active layer, so as to define a T F T channel, and the pixel electrode contacts with the drain electrode; a protection layer formed on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; and a common electrode formed on the protection layer and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active la y er, the drain electrode and the pixel electrode are located in a same layer, wherein the source electrode, th drai n ele ctrode and the semiconductor Pag e 4 of 9 Application Serial No. 13/704, 704 PATENT Reply to final office action of Docket: CU-70149 active layer are formed integrally.

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A method for manufacturing a thin film transistor (T FT) array substrate, comprising: forming a metal layer on a base substrate, and obtaining a gate line and a gate electrode through a first patterning process; forming a gate insulating layer on the gate li n e and the gate electrode; forming a graphene layer on the gate insulating layer and obtaining a semiconductor active layer formed of graphene over the gate electrode by a second patterning process and a hydrogenation treatment: obtaining a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphe n e, by a third patterning process on the graphene layer; wherein the source electrode contacts with the semiconductor active layer and the drain electrode contacts with the semiconductor active layer so as to define a TFT channel, and the pixel electrode contacts with the drain electrode; and forming a protection layer on the data li n e, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; forming a common electrode on the protection la y er and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode are located in a same layer, Pag e 2 of 9 Application Serial No. 13/704,704 PATENT Reply to final office action of March 4, 201 5 Docket: CU-70149 wh erein hfr mi n qof th gpnJ e on the g.In sil tn jyer and ~ obtaining of the semiconductor active layer for medof gr phone over the gatq electrode b y the se cond pat rand the hydr enation teatment comprises: depoitinq al yeafgrpaemat eri ga I eans of plasma enhanced chemical vao r de o sit i on or spin-c oati ng a wateralube iglaered mateia n the gate insulating Iayer s so as to form the graphene layer; coating photoresist on th graphe ne layer, and exp osin~g3raphe ne in the channel region after exposure and development; perforing the hyd roation treatment o" gr aphenein the channel regyon by using 1H₂ or a mixed gas of H₁₂ and Ar2; and removing the remainingptoresist, so a s to obtain the semiconductor active l ayer formed of graphene over the gate electrode.

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A thin film transistor (T FT) array substrate, comprising: a base substrate; a gate line and a gate electrode which are formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphene and formed on the gate insulating la y er; and a semiconductor active layer which is formed of graphene subject to a hydrogenation treatment and formed on the gate insulating layer; wherein the source electrode contacts with the semiconductor active layer, and the drain electrode contacts with the semiconductor active layer, so as to define a T F T channel, and the pixel electrode contacts with the drain electrode; a protection layer formed on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; and a common electrode formed on the protection layer and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active la y er, the drain electrode and the pixel electrode are located in a same layer, wherein the source electrode, th drai n ele ctrode and the semiconductor Pag e 4 of 9 Application Serial No. 13/704, 704 PATENT Reply to final office action of Docket: CU-70149 active layer are formed integrally.

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A method for manufacturing a thin film transistor (T FT) array substrate, comprising: forming a metal layer on a base substrate, and obtaining a gate line and a gate electrode through a first patterning process; forming a gate insulating layer on the gate li n e and the gate electrode; forming a graphene layer on the gate insulating layer and obtaining a semiconductor active layer formed of graphene over the gate electrode by a second patterning process and a hydrogenation treatment: obtaining a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphe n e, by a third patterning process on the graphene layer; wherein the source electrode contacts with the semiconductor active layer and the drain electrode contacts with the semiconductor active layer so as to define a TFT channel, and the pixel electrode contacts with the drain electrode; and forming a protection layer on the data li n e, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; forming a common electrode on the protection la y er and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode are located in a same layer, Pag e 2 of 9 Application Serial No. 13/704,704 PATENT Reply to final office action of March 4, 201 5 Docket: CU-70149 wh erein hfr mi n qof th gpnJ e on the g.In sil tn jyer and ~ obtaining of the semiconductor active layer for medof gr phone over the gatq electrode b y the se cond pat rand the hydr enation teatment comprises: depoitinq al yeafgrpaemat eri ga I eans of plasma enhanced chemical vao r de o sit i on or spin-c oati ng a wateralube iglaered mateia n the gate insulating Iayer s so as to form the graphene layer; coating photoresist on th graphe ne layer, and exp osin~g3raphe ne in the channel region after exposure and development; perforing the hyd roation treatment o" gr aphenein the channel regyon by using 1H₂ or a mixed gas of H₁₂ and Ar2; and removing the remainingptoresist, so a s to obtain the semiconductor active l ayer formed of graphene over the gate electrode.

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A thin film transistor (T FT) array substrate, comprising: a base substrate; a gate line and a gate electrode which are formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphene and formed on the gate insulating la y er; and a semiconductor active layer which is formed of graphene subject to a hydrogenation treatment and formed on the gate insulating layer; wherein the source electrode contacts with the semiconductor active layer, and the drain electrode contacts with the semiconductor active layer, so as to define a T F T channel, and the pixel electrode contacts with the drain electrode; a protection layer formed on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; and a common electrode formed on the protection layer and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active la y er, the drain electrode and the pixel electrode are located in a same layer, wherein the source electrode, th drai n ele ctrode and the semiconductor Pag e 4 of 9 Application Serial No. 13/704, 704 PATENT Reply to final office action of Docket: CU-70149 active layer are formed integrally.

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A method for manufacturing a thin film transistor (T FT) array substrate, comprising: forming a metal layer on a base substrate, and obtaining a gate line and a gate electrode through a first patterning process; forming a gate insulating layer on the gate li n e and the gate electrode; forming a graphene layer on the gate insulating layer and obtaining a semiconductor active layer formed of graphene over the gate electrode by a second patterning process and a hydrogenation treatment: obtaining a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphe n e, by a third patterning process on the graphene layer; wherein the source electrode contacts with the semiconductor active layer and the drain electrode contacts with the semiconductor active layer so as to define a TFT channel, and the pixel electrode contacts with the drain electrode; and forming a protection layer on the data li n e, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; forming a common electrode on the protection la y er and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode are located in a same layer, Pag e 2 of 9 Application Serial No. 13/704,704 PATENT Reply to final office action of March 4, 201 5 Docket: CU-70149 wh erein hfr mi n qof th gpnJ e on the g.In sil tn jyer and ~ obtaining of the semiconductor active layer for medof gr phone over the gatq electrode b y the se cond pat rand the hydr enation teatment comprises: depoitinq al yeafgrpaemat eri ga I eans of plasma enhanced chemical vao r de o sit i on or spin-c oati ng a wateralube iglaered mateia n the gate insulating Iayer s so as to form the graphene layer; coating photoresist on th graphe ne layer, and exp osin~g3raphe ne in the channel region after exposure and development; perforing the hyd roation treatment o" gr aphenein the channel regyon by using 1H₂ or a mixed gas of H₁₂ and Ar2; and removing the remainingptoresist, so a s to obtain the semiconductor active l ayer formed of graphene over the gate electrode.

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A thin film transistor (T FT) array substrate, comprising: a base substrate; a gate line and a gate electrode which are formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a data line, a source electrode, a drain electrode and a pixel electrode, which are formed of graphene and formed on the gate insulating la y er; and a semiconductor active layer which is formed of graphene subject to a hydrogenation treatment and formed on the gate insulating layer; wherein the source electrode contacts with the semiconductor active layer, and the drain electrode contacts with the semiconductor active layer, so as to define a T F T channel, and the pixel electrode contacts with the drain electrode; a protection layer formed on the data line, the source electrode, the semiconductor active layer, the drain electrode and the pixel electrode; and a common electrode formed on the protection layer and over the pixel electrode, wherein the data line, the source electrode, the semiconductor active la y er, the drain electrode and the pixel electrode are located in a same layer, wherein the source electrode, th drai n ele ctrode and the semiconductor Pag e 4 of 9 Application Serial No. 13/704, 704 PATENT Reply to final office action of Docket: CU-70149 active layer are formed integrally.

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