Patent
US 8,361,853GRAPHENE NANORIBBONS, METHOD OF FABRICATION AND THEIR USE IN ELECTRONIC DEVICES
Guy Cohen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,361,853Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial structure including, from bottom to top, a substrate, a graphene …
FIG. 2 after forming a conformal material layer on exposed surfaces of the structure including atop the exposed surfaces of the graphene layer as well as on …
FIG. 3 after removing the patterned hard mask to provide a structure including a nanoribbon- containing layer of alternating graphene nanoribbons separated by …
FIG. 4 is a pictorial representation (through a cross sectional view) depicting the structure of
FIG. 5 after performing a selective directional etching step which converts the conformal material layer into spacers without etching the graphene layer. [0020]
FIG. 6A including an additional mask used to trim the spacer 32 at each ends of the patterned hard mask. [0021]
FIG. 7 after converting the exposed portions of the graphene layer that are not protected by the spacers into insulating ribbons. [0023]
FIG. 8 after removing the spacers to provide a structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating …
FIG. 9 is a pictorial presentation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a top down view) illustrating the structure shown in either
FIGS. 11 A and 11 B are pictorial representations (through a top down view and a cross sectional view, respectively) of a semiconductor device that includes …
FIGS. 12A and 12B are pictorial representations (through a top down view and a cross sectional view, respectively) of another semiconductor device that …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; and a nanoribbon-containing layer located on an upper surface of the substrate, wherein the nanoribbon-containing layer includes alternating graphene nanoribbons that are separated by alternating insulating ribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material is selected from the group consisting of glass, SiO2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (Cx BN) and a mixture of amorphous/hexagonal bonding boron nitride and carbon boron nitride.
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material is selected from the group consisting of Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, and I nP.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 20 nm.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 2 nm.
YO R₉₂₀₁₀₀₄₂₇U S 1 Page 20 of 24 8. The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a hexagonal crystallographic bonding structure.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fully or partially hydrogenated graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fluorinated graphene or fluorographene.
A method of fabricating a semiconductor structure comprising: providing a graphene layer on an upper surface of a substrate; and converting alternating portions of the graphene layer into insulating ribbons, while remaining alternating portions of the graphene layer form graphene nanoribbons.
The method of Claim 12 wherein said providing the graphene layer includes mechanical exfoliation of graphite; epitaxial growth; hydrazine reduction in which a graphene oxide paper is placed in a solution of pure hydrazine which reduces the graphene oxide paper into single-layered graphene; sodium reduction of ethanol to form an ethoxide product, pyrolyzing the ethoxide product and washing to remove sodium salts; formation of carbon nanotubes, or a layer transfer technique.
The method of Claim 12 further comprising forming a patterned hard mask on an upper surface of the graphene layer prior to said converting, wherein other portions of said graphene layer not protected by said patterned hard mask are converted into said insulating ribbons, and YO R₉₂₀₁₀₀₄₂₇US₁ Page 21 of 24 wherein portions of said graphene layer that are protected by said patterned hard mask form said graphene nanoribbons.
The method of Claim 12 further comprising forming spacers on an upper surface of said graphene layer prior to converting, wherein portions of said graphene layer not protected by said spacers are converted into said insulating ribbons, and wherein other portions of said graphene layer that are protected by said spacer form said graphene nanoribbons.
The method of Claim 12 wherein said converting includes exposing alternating portions of the graphene layer to a hydrogen-containing ambient or a fluorine-containing ambient.
A structure comprising: at least one semiconductor device located atop a substrate, wherein the at least one semiconductor devices includes at least one graphene nanoribbon as a device element, and the at least one graphene nanoribbon is a component of a nanoribbon-containing layer comprising alternating graphene nanoribbons separated by alternating insulating ribbons.
YO R₉₂₀₁₀₀₄₂₇US₁ Page 22 of 24 21. An integrated circuit containing at least the structure of Claim 20.
Layer stacks claimed or described, ordered top of device to substrate.
nanoribbon-containing semiconductor structure
semiconductor device with graphene nanoribbon device element
Materials described outside the worked examples.
graphene nanoribbon
insulating ribbon
dielectric substrate material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 200000 cm2 V-1 s-1 | graphene nanoribbon |
Thickness | 0.34–10 nm |
Related documents with shared materials, methods, properties, or citations.
Chemical Oxidation of Graphene and Carbon Nanotubes Using Cerium (IV) Ammonium Nitrate
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 8,361,853Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial structure including, from bottom to top, a substrate, a graphene …
FIG. 2 after forming a conformal material layer on exposed surfaces of the structure including atop the exposed surfaces of the graphene layer as well as on …
FIG. 3 after removing the patterned hard mask to provide a structure including a nanoribbon- containing layer of alternating graphene nanoribbons separated by …
FIG. 4 is a pictorial representation (through a cross sectional view) depicting the structure of
FIG. 5 after performing a selective directional etching step which converts the conformal material layer into spacers without etching the graphene layer. [0020]
FIG. 6A including an additional mask used to trim the spacer 32 at each ends of the patterned hard mask. [0021]
FIG. 7 after converting the exposed portions of the graphene layer that are not protected by the spacers into insulating ribbons. [0023]
FIG. 8 after removing the spacers to provide a structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating …
FIG. 9 is a pictorial presentation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a top down view) illustrating the structure shown in either
FIGS. 11 A and 11 B are pictorial representations (through a top down view and a cross sectional view, respectively) of a semiconductor device that includes …
FIGS. 12A and 12B are pictorial representations (through a top down view and a cross sectional view, respectively) of another semiconductor device that …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; and a nanoribbon-containing layer located on an upper surface of the substrate, wherein the nanoribbon-containing layer includes alternating graphene nanoribbons that are separated by alternating insulating ribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material is selected from the group consisting of glass, SiO2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (Cx BN) and a mixture of amorphous/hexagonal bonding boron nitride and carbon boron nitride.
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material is selected from the group consisting of Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, and I nP.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 20 nm.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 2 nm.
YO R₉₂₀₁₀₀₄₂₇U S 1 Page 20 of 24 8. The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a hexagonal crystallographic bonding structure.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fully or partially hydrogenated graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fluorinated graphene or fluorographene.
A method of fabricating a semiconductor structure comprising: providing a graphene layer on an upper surface of a substrate; and converting alternating portions of the graphene layer into insulating ribbons, while remaining alternating portions of the graphene layer form graphene nanoribbons.
The method of Claim 12 wherein said providing the graphene layer includes mechanical exfoliation of graphite; epitaxial growth; hydrazine reduction in which a graphene oxide paper is placed in a solution of pure hydrazine which reduces the graphene oxide paper into single-layered graphene; sodium reduction of ethanol to form an ethoxide product, pyrolyzing the ethoxide product and washing to remove sodium salts; formation of carbon nanotubes, or a layer transfer technique.
The method of Claim 12 further comprising forming a patterned hard mask on an upper surface of the graphene layer prior to said converting, wherein other portions of said graphene layer not protected by said patterned hard mask are converted into said insulating ribbons, and YO R₉₂₀₁₀₀₄₂₇US₁ Page 21 of 24 wherein portions of said graphene layer that are protected by said patterned hard mask form said graphene nanoribbons.
The method of Claim 12 further comprising forming spacers on an upper surface of said graphene layer prior to converting, wherein portions of said graphene layer not protected by said spacers are converted into said insulating ribbons, and wherein other portions of said graphene layer that are protected by said spacer form said graphene nanoribbons.
The method of Claim 12 wherein said converting includes exposing alternating portions of the graphene layer to a hydrogen-containing ambient or a fluorine-containing ambient.
A structure comprising: at least one semiconductor device located atop a substrate, wherein the at least one semiconductor devices includes at least one graphene nanoribbon as a device element, and the at least one graphene nanoribbon is a component of a nanoribbon-containing layer comprising alternating graphene nanoribbons separated by alternating insulating ribbons.
YO R₉₂₀₁₀₀₄₂₇US₁ Page 22 of 24 21. An integrated circuit containing at least the structure of Claim 20.
Layer stacks claimed or described, ordered top of device to substrate.
nanoribbon-containing semiconductor structure
semiconductor device with graphene nanoribbon device element
Materials described outside the worked examples.
graphene nanoribbon
insulating ribbon
dielectric substrate material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 200000 cm2 V-1 s-1 | graphene nanoribbon |
Thickness | 0.34–10 nm |
Related documents with shared materials, methods, properties, or citations.
Chemical Oxidation of Graphene and Carbon Nanotubes Using Cerium (IV) Ammonium Nitrate
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 8,361,853Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial structure including, from bottom to top, a substrate, a graphene …
FIG. 2 after forming a conformal material layer on exposed surfaces of the structure including atop the exposed surfaces of the graphene layer as well as on …
FIG. 3 after removing the patterned hard mask to provide a structure including a nanoribbon- containing layer of alternating graphene nanoribbons separated by …
FIG. 4 is a pictorial representation (through a cross sectional view) depicting the structure of
FIG. 5 after performing a selective directional etching step which converts the conformal material layer into spacers without etching the graphene layer. [0020]
FIG. 6A including an additional mask used to trim the spacer 32 at each ends of the patterned hard mask. [0021]
FIG. 7 after converting the exposed portions of the graphene layer that are not protected by the spacers into insulating ribbons. [0023]
FIG. 8 after removing the spacers to provide a structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating …
FIG. 9 is a pictorial presentation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a top down view) illustrating the structure shown in either
FIGS. 11 A and 11 B are pictorial representations (through a top down view and a cross sectional view, respectively) of a semiconductor device that includes …
FIGS. 12A and 12B are pictorial representations (through a top down view and a cross sectional view, respectively) of another semiconductor device that …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; and a nanoribbon-containing layer located on an upper surface of the substrate, wherein the nanoribbon-containing layer includes alternating graphene nanoribbons that are separated by alternating insulating ribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material is selected from the group consisting of glass, SiO2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (Cx BN) and a mixture of amorphous/hexagonal bonding boron nitride and carbon boron nitride.
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material is selected from the group consisting of Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, and I nP.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 20 nm.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 2 nm.
YO R₉₂₀₁₀₀₄₂₇U S 1 Page 20 of 24 8. The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a hexagonal crystallographic bonding structure.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fully or partially hydrogenated graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fluorinated graphene or fluorographene.
A method of fabricating a semiconductor structure comprising: providing a graphene layer on an upper surface of a substrate; and converting alternating portions of the graphene layer into insulating ribbons, while remaining alternating portions of the graphene layer form graphene nanoribbons.
The method of Claim 12 wherein said providing the graphene layer includes mechanical exfoliation of graphite; epitaxial growth; hydrazine reduction in which a graphene oxide paper is placed in a solution of pure hydrazine which reduces the graphene oxide paper into single-layered graphene; sodium reduction of ethanol to form an ethoxide product, pyrolyzing the ethoxide product and washing to remove sodium salts; formation of carbon nanotubes, or a layer transfer technique.
The method of Claim 12 further comprising forming a patterned hard mask on an upper surface of the graphene layer prior to said converting, wherein other portions of said graphene layer not protected by said patterned hard mask are converted into said insulating ribbons, and YO R₉₂₀₁₀₀₄₂₇US₁ Page 21 of 24 wherein portions of said graphene layer that are protected by said patterned hard mask form said graphene nanoribbons.
The method of Claim 12 further comprising forming spacers on an upper surface of said graphene layer prior to converting, wherein portions of said graphene layer not protected by said spacers are converted into said insulating ribbons, and wherein other portions of said graphene layer that are protected by said spacer form said graphene nanoribbons.
The method of Claim 12 wherein said converting includes exposing alternating portions of the graphene layer to a hydrogen-containing ambient or a fluorine-containing ambient.
A structure comprising: at least one semiconductor device located atop a substrate, wherein the at least one semiconductor devices includes at least one graphene nanoribbon as a device element, and the at least one graphene nanoribbon is a component of a nanoribbon-containing layer comprising alternating graphene nanoribbons separated by alternating insulating ribbons.
YO R₉₂₀₁₀₀₄₂₇US₁ Page 22 of 24 21. An integrated circuit containing at least the structure of Claim 20.
Layer stacks claimed or described, ordered top of device to substrate.
nanoribbon-containing semiconductor structure
semiconductor device with graphene nanoribbon device element
Materials described outside the worked examples.
graphene nanoribbon
insulating ribbon
dielectric substrate material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 200000 cm2 V-1 s-1 | graphene nanoribbon |
Thickness | 0.34–10 nm |
Related documents with shared materials, methods, properties, or citations.
Chemical Oxidation of Graphene and Carbon Nanotubes Using Cerium (IV) Ammonium Nitrate
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 8,361,853Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) depicting an initial structure including, from bottom to top, a substrate, a graphene …
FIG. 2 after forming a conformal material layer on exposed surfaces of the structure including atop the exposed surfaces of the graphene layer as well as on …
FIG. 3 after removing the patterned hard mask to provide a structure including a nanoribbon- containing layer of alternating graphene nanoribbons separated by …
FIG. 4 is a pictorial representation (through a cross sectional view) depicting the structure of
FIG. 5 after performing a selective directional etching step which converts the conformal material layer into spacers without etching the graphene layer. [0020]
FIG. 6A including an additional mask used to trim the spacer 32 at each ends of the patterned hard mask. [0021]
FIG. 7 after converting the exposed portions of the graphene layer that are not protected by the spacers into insulating ribbons. [0023]
FIG. 8 after removing the spacers to provide a structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating …
FIG. 9 is a pictorial presentation (through a cross sectional view) illustrating the structure of
FIG. 10 is a pictorial representation (through a top down view) illustrating the structure shown in either
FIGS. 11 A and 11 B are pictorial representations (through a top down view and a cross sectional view, respectively) of a semiconductor device that includes …
FIGS. 12A and 12B are pictorial representations (through a top down view and a cross sectional view, respectively) of another semiconductor device that …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a substrate; and a nanoribbon-containing layer located on an upper surface of the substrate, wherein the nanoribbon-containing layer includes alternating graphene nanoribbons that are separated by alternating insulating ribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material is selected from the group consisting of glass, SiO2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (Cx BN) and a mixture of amorphous/hexagonal bonding boron nitride and carbon boron nitride.
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material is selected from the group consisting of Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, and I nP.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 20 nm.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a width from 1 nm to 2 nm.
YO R₉₂₀₁₀₀₄₂₇U S 1 Page 20 of 24 8. The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons has a hexagonal crystallographic bonding structure.
The semiconductor structure of Claim 1 wherein each of said alternating graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fully or partially hydrogenated graphene.
The semiconductor structure of Claim 1 wherein each of said alternating insulating ribbons is comprised of fluorinated graphene or fluorographene.
A method of fabricating a semiconductor structure comprising: providing a graphene layer on an upper surface of a substrate; and converting alternating portions of the graphene layer into insulating ribbons, while remaining alternating portions of the graphene layer form graphene nanoribbons.
The method of Claim 12 wherein said providing the graphene layer includes mechanical exfoliation of graphite; epitaxial growth; hydrazine reduction in which a graphene oxide paper is placed in a solution of pure hydrazine which reduces the graphene oxide paper into single-layered graphene; sodium reduction of ethanol to form an ethoxide product, pyrolyzing the ethoxide product and washing to remove sodium salts; formation of carbon nanotubes, or a layer transfer technique.
The method of Claim 12 further comprising forming a patterned hard mask on an upper surface of the graphene layer prior to said converting, wherein other portions of said graphene layer not protected by said patterned hard mask are converted into said insulating ribbons, and YO R₉₂₀₁₀₀₄₂₇US₁ Page 21 of 24 wherein portions of said graphene layer that are protected by said patterned hard mask form said graphene nanoribbons.
The method of Claim 12 further comprising forming spacers on an upper surface of said graphene layer prior to converting, wherein portions of said graphene layer not protected by said spacers are converted into said insulating ribbons, and wherein other portions of said graphene layer that are protected by said spacer form said graphene nanoribbons.
The method of Claim 12 wherein said converting includes exposing alternating portions of the graphene layer to a hydrogen-containing ambient or a fluorine-containing ambient.
A structure comprising: at least one semiconductor device located atop a substrate, wherein the at least one semiconductor devices includes at least one graphene nanoribbon as a device element, and the at least one graphene nanoribbon is a component of a nanoribbon-containing layer comprising alternating graphene nanoribbons separated by alternating insulating ribbons.
YO R₉₂₀₁₀₀₄₂₇US₁ Page 22 of 24 21. An integrated circuit containing at least the structure of Claim 20.
Layer stacks claimed or described, ordered top of device to substrate.
nanoribbon-containing semiconductor structure
semiconductor device with graphene nanoribbon device element
Materials described outside the worked examples.
graphene nanoribbon
insulating ribbon
dielectric substrate material
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 200000 cm2 V-1 s-1 | graphene nanoribbon |
Thickness | 0.34–10 nm |
Related documents with shared materials, methods, properties, or citations.
Chemical Oxidation of Graphene and Carbon Nanotubes Using Cerium (IV) Ammonium Nitrate
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
field effect transistor with graphene nanoribbon channel
semiconductor substrate material
hydrogenated graphene (graphane)
fluorinated graphene/fluorographene
| — |
Thickness | 0.34–3.4 nm | — |
Thickness | 1–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–20 nm | — |
Thickness | 1–7 nm | — |
Thickness | 1–50 nm | — |
Thickness | 3–15 nm | — |
Thickness | 1–2 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
field effect transistor with graphene nanoribbon channel
semiconductor substrate material
hydrogenated graphene (graphane)
fluorinated graphene/fluorographene
| — |
Thickness | 0.34–3.4 nm | — |
Thickness | 1–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–20 nm | — |
Thickness | 1–7 nm | — |
Thickness | 1–50 nm | — |
Thickness | 3–15 nm | — |
Thickness | 1–2 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
field effect transistor with graphene nanoribbon channel
semiconductor substrate material
hydrogenated graphene (graphane)
fluorinated graphene/fluorographene
| — |
Thickness | 0.34–3.4 nm | — |
Thickness | 1–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–20 nm | — |
Thickness | 1–7 nm | — |
Thickness | 1–50 nm | — |
Thickness | 3–15 nm | — |
Thickness | 1–2 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
field effect transistor with graphene nanoribbon channel
semiconductor substrate material
hydrogenated graphene (graphane)
fluorinated graphene/fluorographene
| — |
Thickness | 0.34–3.4 nm | — |
Thickness | 1–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–20 nm | — |
Thickness | 1–7 nm | — |
Thickness | 1–50 nm | — |
Thickness | 3–15 nm | — |
Thickness | 1–2 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |