Patent
US 10,186,582Graphene Fluorination for Integration of Graphene with Insulators and Devices
Roman Caudillo, Uygar Avci
Intel Corporation·17 December 2015·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,186,582Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A-E schematically illustrate cross-section side views of different graphene assemblies, in accordance with some embodiments.
FIGS. 2A-B schematically illustrate cross-section side views of graphene assemblies incorporating other dielectric materials, in accordance with some …
FIGS. 3A-B schematically illustrate cross-section side views of graphene assemblies for use in channel or interconnect structures, in accordance with some …
FIGS. 4A-C schematically illustrate cross-section side views of WO 2015/191089 PCT/US₂₀₁₄/042395 graphene and fluorinated graphene used as a tunnel barrier, in …
FIG. 5 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments. 5
FIG. 6 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 7 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 8 schematically illustrates a flow diagram for a method of 10 fabricating a graphene assembly including selectively fluorinated regions, in accordance with …
FIG. 9 schematically illustrates an example system that may include a graphene structure as described herein, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An assembly for use in an integrated circuit, the assembly comprising: a first layer comprising graphene; a second layer comprising fluorinated graphene directly on the first layer comprising graphene; a layer of electrically insulative material on the second layer of fluorinated graphene; and an additional layer comprising fluorinated graphene on the layer of electrically insulative material. Previously presented
The assembly of claim 1, wherein the first layer comprising graphene is directly on a third layer comprising graphene. Previously presented
The assembly of claim 1, further comprising an electrically conductive material on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, further comprising an additional layer comprising graphene on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, wherein the layer of second layer of fluorinated graphene, and the directly on the layer of electrically insulative electrically insulative material is directly on the additional layer comprising fluorinated graphene is material. Previously presented
3-5. Canceled
Canceled
Canceled
A die comprising: a semiconductor substrate; a device layer on the semiconductor substrate, wherein the device layer includes one or more transistor devices; Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 an interconnect layer on the device layer; a layer comprising graphene in the interconnect layer and configured to route electrical signals of the one or more transistor devices; and a layer comprising fluorinated graphene directly on the layer comprising graphene. Currently amended
The die of claim 9, further comprising a gate electrode on the layer comprising fluorinated graphene. Previously presented
The die of claim 9, wherein the layer comprising graphene serves as a channel of a transistor device and the layer comprising fluorinated graphene serves as a gate dielectric of the transistor device. Original
The die of claim 9, further comprising a low-k dielectric material on the layer comprising fluorinated graphene, wherein the low-k dielectric materials is between the layer comprising fluorinated graphene and an additional interconnect layer. Previously presented
Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 Canceled
A method of fabricating an assembly, the method comprising: providing a multilayer stack including a first layer comprising graphene directly on a second layer comprising graphene; fluorinating the graphene of the first layer comprising graphene; forming a layer of electrically insulative material on the first layer comprising graphene; and coupling an additional layer comprising fluorinated graphene to the layer of electrically insulative material. Currently amended
The method of claim 18, wherein providing a multilayer stack includes: depositing the second layer comprising graphene on a substrate by chemical vapor deposition; and coupling the first layer comprising graphene to the second layer comprising graphene. Original
The method of claim 18, further comprising: depositing an electrically conductive material on the first layer comprising graphene prior to fluorinating the graphene of the first layer; and selectively removing portions of the electrically conductive material to expose one or more portions of the first layer comprising graphene prior to fluorinating the graphene of the first layer, wherein the electrically conductive material prevents the portions of the first layer comprising graphene covered by the electrically conductive material from being fluorinated during said fluorinating the graphene of the first layer. Original
20-22. Canceled
Canceled
A computing device, comprising: a circuit board; and a die coupled with the circuit board, the die including: a semiconductor substrate; a first layer comprising graphene on the semiconductor substrate; a second layer comprising fluorinated graphene directly on the layer comprising graphene; a third layer of electrically insulative material directly on the second layer; and a fourth layer comprising fluorinated graphene directly on the third layer. Previously presented
The computing device of claim 24, wherein the die is a processor; and the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and camera. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
multi-layer graphene assembly for integrated circuit
die with graphene interconnect and transistor
Materials described outside the worked examples.
graphene
fluorinated graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
ROLL-TO-ROLL TRANSFER METHOD OF GRAPHENE, GRAPHENE ROLL PRODUCED BY THE METHOD, AND ROLL-TO-ROLL TRANSFER EQUIPMENT FOR GRAPHENE
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 10,186,582Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A-E schematically illustrate cross-section side views of different graphene assemblies, in accordance with some embodiments.
FIGS. 2A-B schematically illustrate cross-section side views of graphene assemblies incorporating other dielectric materials, in accordance with some …
FIGS. 3A-B schematically illustrate cross-section side views of graphene assemblies for use in channel or interconnect structures, in accordance with some …
FIGS. 4A-C schematically illustrate cross-section side views of WO 2015/191089 PCT/US₂₀₁₄/042395 graphene and fluorinated graphene used as a tunnel barrier, in …
FIG. 5 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments. 5
FIG. 6 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 7 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 8 schematically illustrates a flow diagram for a method of 10 fabricating a graphene assembly including selectively fluorinated regions, in accordance with …
FIG. 9 schematically illustrates an example system that may include a graphene structure as described herein, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An assembly for use in an integrated circuit, the assembly comprising: a first layer comprising graphene; a second layer comprising fluorinated graphene directly on the first layer comprising graphene; a layer of electrically insulative material on the second layer of fluorinated graphene; and an additional layer comprising fluorinated graphene on the layer of electrically insulative material. Previously presented
The assembly of claim 1, wherein the first layer comprising graphene is directly on a third layer comprising graphene. Previously presented
The assembly of claim 1, further comprising an electrically conductive material on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, further comprising an additional layer comprising graphene on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, wherein the layer of second layer of fluorinated graphene, and the directly on the layer of electrically insulative electrically insulative material is directly on the additional layer comprising fluorinated graphene is material. Previously presented
3-5. Canceled
Canceled
Canceled
A die comprising: a semiconductor substrate; a device layer on the semiconductor substrate, wherein the device layer includes one or more transistor devices; Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 an interconnect layer on the device layer; a layer comprising graphene in the interconnect layer and configured to route electrical signals of the one or more transistor devices; and a layer comprising fluorinated graphene directly on the layer comprising graphene. Currently amended
The die of claim 9, further comprising a gate electrode on the layer comprising fluorinated graphene. Previously presented
The die of claim 9, wherein the layer comprising graphene serves as a channel of a transistor device and the layer comprising fluorinated graphene serves as a gate dielectric of the transistor device. Original
The die of claim 9, further comprising a low-k dielectric material on the layer comprising fluorinated graphene, wherein the low-k dielectric materials is between the layer comprising fluorinated graphene and an additional interconnect layer. Previously presented
Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 Canceled
A method of fabricating an assembly, the method comprising: providing a multilayer stack including a first layer comprising graphene directly on a second layer comprising graphene; fluorinating the graphene of the first layer comprising graphene; forming a layer of electrically insulative material on the first layer comprising graphene; and coupling an additional layer comprising fluorinated graphene to the layer of electrically insulative material. Currently amended
The method of claim 18, wherein providing a multilayer stack includes: depositing the second layer comprising graphene on a substrate by chemical vapor deposition; and coupling the first layer comprising graphene to the second layer comprising graphene. Original
The method of claim 18, further comprising: depositing an electrically conductive material on the first layer comprising graphene prior to fluorinating the graphene of the first layer; and selectively removing portions of the electrically conductive material to expose one or more portions of the first layer comprising graphene prior to fluorinating the graphene of the first layer, wherein the electrically conductive material prevents the portions of the first layer comprising graphene covered by the electrically conductive material from being fluorinated during said fluorinating the graphene of the first layer. Original
20-22. Canceled
Canceled
A computing device, comprising: a circuit board; and a die coupled with the circuit board, the die including: a semiconductor substrate; a first layer comprising graphene on the semiconductor substrate; a second layer comprising fluorinated graphene directly on the layer comprising graphene; a third layer of electrically insulative material directly on the second layer; and a fourth layer comprising fluorinated graphene directly on the third layer. Previously presented
The computing device of claim 24, wherein the die is a processor; and the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and camera. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
multi-layer graphene assembly for integrated circuit
die with graphene interconnect and transistor
Materials described outside the worked examples.
graphene
fluorinated graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
ROLL-TO-ROLL TRANSFER METHOD OF GRAPHENE, GRAPHENE ROLL PRODUCED BY THE METHOD, AND ROLL-TO-ROLL TRANSFER EQUIPMENT FOR GRAPHENE
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 10,186,582Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A-E schematically illustrate cross-section side views of different graphene assemblies, in accordance with some embodiments.
FIGS. 2A-B schematically illustrate cross-section side views of graphene assemblies incorporating other dielectric materials, in accordance with some …
FIGS. 3A-B schematically illustrate cross-section side views of graphene assemblies for use in channel or interconnect structures, in accordance with some …
FIGS. 4A-C schematically illustrate cross-section side views of WO 2015/191089 PCT/US₂₀₁₄/042395 graphene and fluorinated graphene used as a tunnel barrier, in …
FIG. 5 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments. 5
FIG. 6 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 7 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 8 schematically illustrates a flow diagram for a method of 10 fabricating a graphene assembly including selectively fluorinated regions, in accordance with …
FIG. 9 schematically illustrates an example system that may include a graphene structure as described herein, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An assembly for use in an integrated circuit, the assembly comprising: a first layer comprising graphene; a second layer comprising fluorinated graphene directly on the first layer comprising graphene; a layer of electrically insulative material on the second layer of fluorinated graphene; and an additional layer comprising fluorinated graphene on the layer of electrically insulative material. Previously presented
The assembly of claim 1, wherein the first layer comprising graphene is directly on a third layer comprising graphene. Previously presented
The assembly of claim 1, further comprising an electrically conductive material on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, further comprising an additional layer comprising graphene on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, wherein the layer of second layer of fluorinated graphene, and the directly on the layer of electrically insulative electrically insulative material is directly on the additional layer comprising fluorinated graphene is material. Previously presented
3-5. Canceled
Canceled
Canceled
A die comprising: a semiconductor substrate; a device layer on the semiconductor substrate, wherein the device layer includes one or more transistor devices; Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 an interconnect layer on the device layer; a layer comprising graphene in the interconnect layer and configured to route electrical signals of the one or more transistor devices; and a layer comprising fluorinated graphene directly on the layer comprising graphene. Currently amended
The die of claim 9, further comprising a gate electrode on the layer comprising fluorinated graphene. Previously presented
The die of claim 9, wherein the layer comprising graphene serves as a channel of a transistor device and the layer comprising fluorinated graphene serves as a gate dielectric of the transistor device. Original
The die of claim 9, further comprising a low-k dielectric material on the layer comprising fluorinated graphene, wherein the low-k dielectric materials is between the layer comprising fluorinated graphene and an additional interconnect layer. Previously presented
Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 Canceled
A method of fabricating an assembly, the method comprising: providing a multilayer stack including a first layer comprising graphene directly on a second layer comprising graphene; fluorinating the graphene of the first layer comprising graphene; forming a layer of electrically insulative material on the first layer comprising graphene; and coupling an additional layer comprising fluorinated graphene to the layer of electrically insulative material. Currently amended
The method of claim 18, wherein providing a multilayer stack includes: depositing the second layer comprising graphene on a substrate by chemical vapor deposition; and coupling the first layer comprising graphene to the second layer comprising graphene. Original
The method of claim 18, further comprising: depositing an electrically conductive material on the first layer comprising graphene prior to fluorinating the graphene of the first layer; and selectively removing portions of the electrically conductive material to expose one or more portions of the first layer comprising graphene prior to fluorinating the graphene of the first layer, wherein the electrically conductive material prevents the portions of the first layer comprising graphene covered by the electrically conductive material from being fluorinated during said fluorinating the graphene of the first layer. Original
20-22. Canceled
Canceled
A computing device, comprising: a circuit board; and a die coupled with the circuit board, the die including: a semiconductor substrate; a first layer comprising graphene on the semiconductor substrate; a second layer comprising fluorinated graphene directly on the layer comprising graphene; a third layer of electrically insulative material directly on the second layer; and a fourth layer comprising fluorinated graphene directly on the third layer. Previously presented
The computing device of claim 24, wherein the die is a processor; and the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and camera. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
multi-layer graphene assembly for integrated circuit
die with graphene interconnect and transistor
Materials described outside the worked examples.
graphene
fluorinated graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
ROLL-TO-ROLL TRANSFER METHOD OF GRAPHENE, GRAPHENE ROLL PRODUCED BY THE METHOD, AND ROLL-TO-ROLL TRANSFER EQUIPMENT FOR GRAPHENE
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
Patent
Atlas literature
Patent
US 10,186,582Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 A-E schematically illustrate cross-section side views of different graphene assemblies, in accordance with some embodiments.
FIGS. 2A-B schematically illustrate cross-section side views of graphene assemblies incorporating other dielectric materials, in accordance with some …
FIGS. 3A-B schematically illustrate cross-section side views of graphene assemblies for use in channel or interconnect structures, in accordance with some …
FIGS. 4A-C schematically illustrate cross-section side views of WO 2015/191089 PCT/US₂₀₁₄/042395 graphene and fluorinated graphene used as a tunnel barrier, in …
FIG. 5 schematically illustrates a cross-section side view of an integrated circuit (IC) assembly, in accordance with some embodiments. 5
FIG. 6 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 7 schematically illustrates a flow diagram for a method of fabricating a graphene assembly, in accordance with some embodiments.
FIG. 8 schematically illustrates a flow diagram for a method of 10 fabricating a graphene assembly including selectively fluorinated regions, in accordance with …
FIG. 9 schematically illustrates an example system that may include a graphene structure as described herein, in accordance with some embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An assembly for use in an integrated circuit, the assembly comprising: a first layer comprising graphene; a second layer comprising fluorinated graphene directly on the first layer comprising graphene; a layer of electrically insulative material on the second layer of fluorinated graphene; and an additional layer comprising fluorinated graphene on the layer of electrically insulative material. Previously presented
The assembly of claim 1, wherein the first layer comprising graphene is directly on a third layer comprising graphene. Previously presented
The assembly of claim 1, further comprising an electrically conductive material on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, further comprising an additional layer comprising graphene on the additional layer comprising fluorinated graphene. Previously presented
The assembly of claim 1, wherein the layer of second layer of fluorinated graphene, and the directly on the layer of electrically insulative electrically insulative material is directly on the additional layer comprising fluorinated graphene is material. Previously presented
3-5. Canceled
Canceled
Canceled
A die comprising: a semiconductor substrate; a device layer on the semiconductor substrate, wherein the device layer includes one or more transistor devices; Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 an interconnect layer on the device layer; a layer comprising graphene in the interconnect layer and configured to route electrical signals of the one or more transistor devices; and a layer comprising fluorinated graphene directly on the layer comprising graphene. Currently amended
The die of claim 9, further comprising a gate electrode on the layer comprising fluorinated graphene. Previously presented
The die of claim 9, wherein the layer comprising graphene serves as a channel of a transistor device and the layer comprising fluorinated graphene serves as a gate dielectric of the transistor device. Original
The die of claim 9, further comprising a low-k dielectric material on the layer comprising fluorinated graphene, wherein the low-k dielectric materials is between the layer comprising fluorinated graphene and an additional interconnect layer. Previously presented
Attorney Docket No. 110348-217151 (P₆₅₅₆₉US) App l ciation No.: 15/123,242 Canceled
A method of fabricating an assembly, the method comprising: providing a multilayer stack including a first layer comprising graphene directly on a second layer comprising graphene; fluorinating the graphene of the first layer comprising graphene; forming a layer of electrically insulative material on the first layer comprising graphene; and coupling an additional layer comprising fluorinated graphene to the layer of electrically insulative material. Currently amended
The method of claim 18, wherein providing a multilayer stack includes: depositing the second layer comprising graphene on a substrate by chemical vapor deposition; and coupling the first layer comprising graphene to the second layer comprising graphene. Original
The method of claim 18, further comprising: depositing an electrically conductive material on the first layer comprising graphene prior to fluorinating the graphene of the first layer; and selectively removing portions of the electrically conductive material to expose one or more portions of the first layer comprising graphene prior to fluorinating the graphene of the first layer, wherein the electrically conductive material prevents the portions of the first layer comprising graphene covered by the electrically conductive material from being fluorinated during said fluorinating the graphene of the first layer. Original
20-22. Canceled
Canceled
A computing device, comprising: a circuit board; and a die coupled with the circuit board, the die including: a semiconductor substrate; a first layer comprising graphene on the semiconductor substrate; a second layer comprising fluorinated graphene directly on the layer comprising graphene; a third layer of electrically insulative material directly on the second layer; and a fourth layer comprising fluorinated graphene directly on the third layer. Previously presented
The computing device of claim 24, wherein the die is a processor; and the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and camera. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
multi-layer graphene assembly for integrated circuit
die with graphene interconnect and transistor
Materials described outside the worked examples.
graphene
fluorinated graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
ROLL-TO-ROLL TRANSFER METHOD OF GRAPHENE, GRAPHENE ROLL PRODUCED BY THE METHOD, AND ROLL-TO-ROLL TRANSFER EQUIPMENT FOR GRAPHENE
THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF
computing device die with graphene layers
field-effect transistor with graphene channel and fluorinated graphene gate dielectric
electrically insulative material
semiconductor substrate
low-k dielectric material
nonflourinated graphene
workfunction metals
computing device die with graphene layers
field-effect transistor with graphene channel and fluorinated graphene gate dielectric
electrically insulative material
semiconductor substrate
low-k dielectric material
nonflourinated graphene
workfunction metals
computing device die with graphene layers
field-effect transistor with graphene channel and fluorinated graphene gate dielectric
electrically insulative material
semiconductor substrate
low-k dielectric material
nonflourinated graphene
workfunction metals
computing device die with graphene layers
field-effect transistor with graphene channel and fluorinated graphene gate dielectric
electrically insulative material
semiconductor substrate
low-k dielectric material
nonflourinated graphene
workfunction metals