Patent
US 9,087,691METHOD FOR MANUFACTURING GRAPHENE NANO-RIBBON, MOSFET AND METHOD FOR MANUFACTURING THE SAME
Huilong Zhu
US
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Patent
Atlas literature
Patent
US 9,087,691Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a graphene nano-ribbon, comprising: forming a stack of a seed layer and a growth blocking layer on an insulating substrate; patterning the stack of the seed layer and the growth blocking layer to form at least one stack stripe which exposes a side surface of the seed layer; and growing a graphene nano-ribbon at the side surface of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a width substantially equal to a thickness of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite. withdrawn
The method according to claim 1, wherein the stack of the seed layer and the growth blocking layer comprises at least one seed layer and at least one growth blocking layer which are alternately stacked in a vertical direction. withdrawn
The method according to claim 1, wherein the seed layer is made of one selected from a group consisting of Ni, Co, Pt, I r and Ru. withdrawn
The method according to claim 1, wherein the growth blocking layer is made of nitride. -3-withdrawn
The method according to claim 1, wherein forming the stack of the seed layer and the growth blocking layer comprises growing a superlattice of the seed layer and the growth blocking layer. withdrawn
A method for manufacturing a MOSFET, comprising: manufacturing at least one graphene nano-ribbon with the method according to any of claim 1; forming a protection layer between the at least one stack stripe so that the graphene nano- ribbon is embedded in the protection layer; removing the at least one stack stripe to form at least one trench which exposes a surface of the graphene nano-ribbon at a side surface of the protection layer; forming a stack of a gate dielectric and a gate conductor on the graphene nano-ribbon; forming sidewall spacers at both sides of the gate conductor; forming a source region and a drain region at portions of the graphene nanoribbon; and filling the trench in the protection layer with a metal so as to form a source contact for the source region and a drain contact for the drain region. withdrawn
(Cu rr ently Amended) A MOSFET, comprising an insulating substrate; a protection layer on the insulating substrate; at least one graphene nano-ribbon: i its bod embedded n-inside the protection layer-a side surface w.,.ek -- -exposed bh o lae rtat a cside su r face of the protection layer; amiestegalis ona t, e si des)rfag of e ot io I, e, afyl rgtn wi ecosdsi de suace of the a t oioni i gt a channel region in each of the at least one graphene nano -ri bbon; a source region and a drain region in each of the at least one graphene nano-ribbon, the channel region being located between the source region and the drain region; a-t-enega-i and -5- a source contact and a drain contact which contact the source region and the drain region respectively on the side surface of the protection layer.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon comprises a plurality of graphene nano-ribbons which are stacked in a vertical direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a plurality of graphene nano-ribbons which are arranged laterally.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a width of about 5-20 nm.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite.
The MOSFET according to claim 14, wherein the gate conductor extends in a direction perpendicular to an extension direction of the at least one graphene nano-ribbon.
The MOSFET according to claim 14, further comprising a diffusion barrier layer between the gate conductor and the gate dielectric.
The m-eth--M- SE I according to claim 14, wherein the protection layer is made of an oxide. -6-
The MOSFET according to claim 14, wherein the protection layer extends in a first direction, the at least one graphene nano-ribbon extends along the protection layer in the first direction, and the gate stack extends in a second direction crossing the first direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a number of graphene nano-ribbons in pairs, each pair being disposed in the protection layer opposite to each other and thus having their respective side surfaces exposed by opposite side surfaces of the protection layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-ribbon MOSFET
Materials described outside the worked examples.
graphene nano-ribbon
seed layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,087,691Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a graphene nano-ribbon, comprising: forming a stack of a seed layer and a growth blocking layer on an insulating substrate; patterning the stack of the seed layer and the growth blocking layer to form at least one stack stripe which exposes a side surface of the seed layer; and growing a graphene nano-ribbon at the side surface of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a width substantially equal to a thickness of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite. withdrawn
The method according to claim 1, wherein the stack of the seed layer and the growth blocking layer comprises at least one seed layer and at least one growth blocking layer which are alternately stacked in a vertical direction. withdrawn
The method according to claim 1, wherein the seed layer is made of one selected from a group consisting of Ni, Co, Pt, I r and Ru. withdrawn
The method according to claim 1, wherein the growth blocking layer is made of nitride. -3-withdrawn
The method according to claim 1, wherein forming the stack of the seed layer and the growth blocking layer comprises growing a superlattice of the seed layer and the growth blocking layer. withdrawn
A method for manufacturing a MOSFET, comprising: manufacturing at least one graphene nano-ribbon with the method according to any of claim 1; forming a protection layer between the at least one stack stripe so that the graphene nano- ribbon is embedded in the protection layer; removing the at least one stack stripe to form at least one trench which exposes a surface of the graphene nano-ribbon at a side surface of the protection layer; forming a stack of a gate dielectric and a gate conductor on the graphene nano-ribbon; forming sidewall spacers at both sides of the gate conductor; forming a source region and a drain region at portions of the graphene nanoribbon; and filling the trench in the protection layer with a metal so as to form a source contact for the source region and a drain contact for the drain region. withdrawn
(Cu rr ently Amended) A MOSFET, comprising an insulating substrate; a protection layer on the insulating substrate; at least one graphene nano-ribbon: i its bod embedded n-inside the protection layer-a side surface w.,.ek -- -exposed bh o lae rtat a cside su r face of the protection layer; amiestegalis ona t, e si des)rfag of e ot io I, e, afyl rgtn wi ecosdsi de suace of the a t oioni i gt a channel region in each of the at least one graphene nano -ri bbon; a source region and a drain region in each of the at least one graphene nano-ribbon, the channel region being located between the source region and the drain region; a-t-enega-i and -5- a source contact and a drain contact which contact the source region and the drain region respectively on the side surface of the protection layer.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon comprises a plurality of graphene nano-ribbons which are stacked in a vertical direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a plurality of graphene nano-ribbons which are arranged laterally.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a width of about 5-20 nm.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite.
The MOSFET according to claim 14, wherein the gate conductor extends in a direction perpendicular to an extension direction of the at least one graphene nano-ribbon.
The MOSFET according to claim 14, further comprising a diffusion barrier layer between the gate conductor and the gate dielectric.
The m-eth--M- SE I according to claim 14, wherein the protection layer is made of an oxide. -6-
The MOSFET according to claim 14, wherein the protection layer extends in a first direction, the at least one graphene nano-ribbon extends along the protection layer in the first direction, and the gate stack extends in a second direction crossing the first direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a number of graphene nano-ribbons in pairs, each pair being disposed in the protection layer opposite to each other and thus having their respective side surfaces exposed by opposite side surfaces of the protection layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-ribbon MOSFET
Materials described outside the worked examples.
graphene nano-ribbon
seed layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,087,691Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a graphene nano-ribbon, comprising: forming a stack of a seed layer and a growth blocking layer on an insulating substrate; patterning the stack of the seed layer and the growth blocking layer to form at least one stack stripe which exposes a side surface of the seed layer; and growing a graphene nano-ribbon at the side surface of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a width substantially equal to a thickness of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite. withdrawn
The method according to claim 1, wherein the stack of the seed layer and the growth blocking layer comprises at least one seed layer and at least one growth blocking layer which are alternately stacked in a vertical direction. withdrawn
The method according to claim 1, wherein the seed layer is made of one selected from a group consisting of Ni, Co, Pt, I r and Ru. withdrawn
The method according to claim 1, wherein the growth blocking layer is made of nitride. -3-withdrawn
The method according to claim 1, wherein forming the stack of the seed layer and the growth blocking layer comprises growing a superlattice of the seed layer and the growth blocking layer. withdrawn
A method for manufacturing a MOSFET, comprising: manufacturing at least one graphene nano-ribbon with the method according to any of claim 1; forming a protection layer between the at least one stack stripe so that the graphene nano- ribbon is embedded in the protection layer; removing the at least one stack stripe to form at least one trench which exposes a surface of the graphene nano-ribbon at a side surface of the protection layer; forming a stack of a gate dielectric and a gate conductor on the graphene nano-ribbon; forming sidewall spacers at both sides of the gate conductor; forming a source region and a drain region at portions of the graphene nanoribbon; and filling the trench in the protection layer with a metal so as to form a source contact for the source region and a drain contact for the drain region. withdrawn
(Cu rr ently Amended) A MOSFET, comprising an insulating substrate; a protection layer on the insulating substrate; at least one graphene nano-ribbon: i its bod embedded n-inside the protection layer-a side surface w.,.ek -- -exposed bh o lae rtat a cside su r face of the protection layer; amiestegalis ona t, e si des)rfag of e ot io I, e, afyl rgtn wi ecosdsi de suace of the a t oioni i gt a channel region in each of the at least one graphene nano -ri bbon; a source region and a drain region in each of the at least one graphene nano-ribbon, the channel region being located between the source region and the drain region; a-t-enega-i and -5- a source contact and a drain contact which contact the source region and the drain region respectively on the side surface of the protection layer.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon comprises a plurality of graphene nano-ribbons which are stacked in a vertical direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a plurality of graphene nano-ribbons which are arranged laterally.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a width of about 5-20 nm.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite.
The MOSFET according to claim 14, wherein the gate conductor extends in a direction perpendicular to an extension direction of the at least one graphene nano-ribbon.
The MOSFET according to claim 14, further comprising a diffusion barrier layer between the gate conductor and the gate dielectric.
The m-eth--M- SE I according to claim 14, wherein the protection layer is made of an oxide. -6-
The MOSFET according to claim 14, wherein the protection layer extends in a first direction, the at least one graphene nano-ribbon extends along the protection layer in the first direction, and the gate stack extends in a second direction crossing the first direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a number of graphene nano-ribbons in pairs, each pair being disposed in the protection layer opposite to each other and thus having their respective side surfaces exposed by opposite side surfaces of the protection layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-ribbon MOSFET
Materials described outside the worked examples.
graphene nano-ribbon
seed layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,087,691Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for manufacturing a graphene nano-ribbon, comprising: forming a stack of a seed layer and a growth blocking layer on an insulating substrate; patterning the stack of the seed layer and the growth blocking layer to form at least one stack stripe which exposes a side surface of the seed layer; and growing a graphene nano-ribbon at the side surface of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a width substantially equal to a thickness of the seed layer. withdrawn
The method according to claim 1, wherein the graphene nano-ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite. withdrawn
The method according to claim 1, wherein the stack of the seed layer and the growth blocking layer comprises at least one seed layer and at least one growth blocking layer which are alternately stacked in a vertical direction. withdrawn
The method according to claim 1, wherein the seed layer is made of one selected from a group consisting of Ni, Co, Pt, I r and Ru. withdrawn
The method according to claim 1, wherein the growth blocking layer is made of nitride. -3-withdrawn
The method according to claim 1, wherein forming the stack of the seed layer and the growth blocking layer comprises growing a superlattice of the seed layer and the growth blocking layer. withdrawn
A method for manufacturing a MOSFET, comprising: manufacturing at least one graphene nano-ribbon with the method according to any of claim 1; forming a protection layer between the at least one stack stripe so that the graphene nano- ribbon is embedded in the protection layer; removing the at least one stack stripe to form at least one trench which exposes a surface of the graphene nano-ribbon at a side surface of the protection layer; forming a stack of a gate dielectric and a gate conductor on the graphene nano-ribbon; forming sidewall spacers at both sides of the gate conductor; forming a source region and a drain region at portions of the graphene nanoribbon; and filling the trench in the protection layer with a metal so as to form a source contact for the source region and a drain contact for the drain region. withdrawn
(Cu rr ently Amended) A MOSFET, comprising an insulating substrate; a protection layer on the insulating substrate; at least one graphene nano-ribbon: i its bod embedded n-inside the protection layer-a side surface w.,.ek -- -exposed bh o lae rtat a cside su r face of the protection layer; amiestegalis ona t, e si des)rfag of e ot io I, e, afyl rgtn wi ecosdsi de suace of the a t oioni i gt a channel region in each of the at least one graphene nano -ri bbon; a source region and a drain region in each of the at least one graphene nano-ribbon, the channel region being located between the source region and the drain region; a-t-enega-i and -5- a source contact and a drain contact which contact the source region and the drain region respectively on the side surface of the protection layer.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon comprises a plurality of graphene nano-ribbons which are stacked in a vertical direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a plurality of graphene nano-ribbons which are arranged laterally.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a width of about 5-20 nm.
The MOSFET according to claim 14, wherein the at least one graphene nano- ribbon has a thickness substantially equal to one layer, two layers or more layers of carbon atoms of graphite.
The MOSFET according to claim 14, wherein the gate conductor extends in a direction perpendicular to an extension direction of the at least one graphene nano-ribbon.
The MOSFET according to claim 14, further comprising a diffusion barrier layer between the gate conductor and the gate dielectric.
The m-eth--M- SE I according to claim 14, wherein the protection layer is made of an oxide. -6-
The MOSFET according to claim 14, wherein the protection layer extends in a first direction, the at least one graphene nano-ribbon extends along the protection layer in the first direction, and the gate stack extends in a second direction crossing the first direction.
The MOSFET according to claim 14, wherein the at least one graphene nano-ribbon comprises a number of graphene nano-ribbons in pairs, each pair being disposed in the protection layer opposite to each other and thus having their respective side surfaces exposed by opposite side surfaces of the protection layer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene nano-ribbon MOSFET
Materials described outside the worked examples.
graphene nano-ribbon
seed layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 5–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
growth blocking layer
Ni
Co
Pt
Ir
Ru
nitride
oxide protection layer
insulating substrate
strontium titanate (STO) substrate
SrTiO₃
TRANSISTOR WITH FLUORINATED GRAPHENE SPACER
growth blocking layer
Ni
Co
Pt
Ir
Ru
nitride
oxide protection layer
insulating substrate
strontium titanate (STO) substrate
SrTiO₃
TRANSISTOR WITH FLUORINATED GRAPHENE SPACER
growth blocking layer
Ni
Co
Pt
Ir
Ru
nitride
oxide protection layer
insulating substrate
strontium titanate (STO) substrate
SrTiO₃
TRANSISTOR WITH FLUORINATED GRAPHENE SPACER
growth blocking layer
Ni
Co
Pt
Ir
Ru
nitride
oxide protection layer
insulating substrate
strontium titanate (STO) substrate
SrTiO₃
TRANSISTOR WITH FLUORINATED GRAPHENE SPACER