Patent
US 10,037,886METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
Takeshi FUJII
US
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US 10,037,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
: A method of manufacturing a silicon carbide semiconductor device including a p-type silicon carbide semiconductor body and a metal electrode, the method comprising: forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce an electrical potential drop generated in a conjunction interface between the p- type silicon carbide semiconductor body and the metal electrode, the grapheme la y er being in contact with the surface of the p-t y pe silicon carbide semiconductor body; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming, on a surface of the insulator la y er, the metal electrode, the metal electrode being in ohmic contact with the p-type silicon carbide semiconductor body. Currently amended
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming a laminated layer including one to three graphene laminated layers. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming the graphene layer on the p- type silicon carbide semiconductor body so that coverage of the graphene layer that is a ratio of an area of a surface area of the p-type silicon carbide semiconductor body covered by the graphene layer to a total surface area of the p-type silicon carbide semiconductor body is equal to or greater than % of a surface area of the p-type silicon carbide semiconductor body. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the p-type silicon carbide semiconductor body include a carrier concentration that is equal to or greater than i x 10 16/cm 3. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal electrode comprised of one or more material selected from a group consisting of gold, silver, platinum, titanium, nickel, iron, cobalt, copper, chromium, aluminum, palladium, and an alloy thereof. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming an insulator layer includes forming one insulator layer or two laminated insulator layers. Original
Layer stacks claimed or described, ordered top of device to substrate.
silicon carbide semiconductor device with ohmic contact
Materials described outside the worked examples.
graphene
p-type silicon carbide semiconductor body
SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
contact resistance of p-type SiC and metal electrode by silicidation (prior art, insufficient) | 0.01–0.001 Ω·cm² | SiC |
contact resistance of n-type SiC semiconductor device region and metal electrode by silicidation (prior art, sufficient) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,037,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
: A method of manufacturing a silicon carbide semiconductor device including a p-type silicon carbide semiconductor body and a metal electrode, the method comprising: forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce an electrical potential drop generated in a conjunction interface between the p- type silicon carbide semiconductor body and the metal electrode, the grapheme la y er being in contact with the surface of the p-t y pe silicon carbide semiconductor body; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming, on a surface of the insulator la y er, the metal electrode, the metal electrode being in ohmic contact with the p-type silicon carbide semiconductor body. Currently amended
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming a laminated layer including one to three graphene laminated layers. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming the graphene layer on the p- type silicon carbide semiconductor body so that coverage of the graphene layer that is a ratio of an area of a surface area of the p-type silicon carbide semiconductor body covered by the graphene layer to a total surface area of the p-type silicon carbide semiconductor body is equal to or greater than % of a surface area of the p-type silicon carbide semiconductor body. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the p-type silicon carbide semiconductor body include a carrier concentration that is equal to or greater than i x 10 16/cm 3. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal electrode comprised of one or more material selected from a group consisting of gold, silver, platinum, titanium, nickel, iron, cobalt, copper, chromium, aluminum, palladium, and an alloy thereof. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming an insulator layer includes forming one insulator layer or two laminated insulator layers. Original
Layer stacks claimed or described, ordered top of device to substrate.
silicon carbide semiconductor device with ohmic contact
Materials described outside the worked examples.
graphene
p-type silicon carbide semiconductor body
SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
contact resistance of p-type SiC and metal electrode by silicidation (prior art, insufficient) | 0.01–0.001 Ω·cm² | SiC |
contact resistance of n-type SiC semiconductor device region and metal electrode by silicidation (prior art, sufficient) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,037,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
: A method of manufacturing a silicon carbide semiconductor device including a p-type silicon carbide semiconductor body and a metal electrode, the method comprising: forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce an electrical potential drop generated in a conjunction interface between the p- type silicon carbide semiconductor body and the metal electrode, the grapheme la y er being in contact with the surface of the p-t y pe silicon carbide semiconductor body; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming, on a surface of the insulator la y er, the metal electrode, the metal electrode being in ohmic contact with the p-type silicon carbide semiconductor body. Currently amended
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming a laminated layer including one to three graphene laminated layers. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming the graphene layer on the p- type silicon carbide semiconductor body so that coverage of the graphene layer that is a ratio of an area of a surface area of the p-type silicon carbide semiconductor body covered by the graphene layer to a total surface area of the p-type silicon carbide semiconductor body is equal to or greater than % of a surface area of the p-type silicon carbide semiconductor body. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the p-type silicon carbide semiconductor body include a carrier concentration that is equal to or greater than i x 10 16/cm 3. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal electrode comprised of one or more material selected from a group consisting of gold, silver, platinum, titanium, nickel, iron, cobalt, copper, chromium, aluminum, palladium, and an alloy thereof. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming an insulator layer includes forming one insulator layer or two laminated insulator layers. Original
Layer stacks claimed or described, ordered top of device to substrate.
silicon carbide semiconductor device with ohmic contact
Materials described outside the worked examples.
graphene
p-type silicon carbide semiconductor body
SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
contact resistance of p-type SiC and metal electrode by silicidation (prior art, insufficient) | 0.01–0.001 Ω·cm² | SiC |
contact resistance of n-type SiC semiconductor device region and metal electrode by silicidation (prior art, sufficient) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,037,886Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
: A method of manufacturing a silicon carbide semiconductor device including a p-type silicon carbide semiconductor body and a metal electrode, the method comprising: forming on a surface of the p-type silicon carbide semiconductor body, a graphene layer so as to reduce an electrical potential drop generated in a conjunction interface between the p- type silicon carbide semiconductor body and the metal electrode, the grapheme la y er being in contact with the surface of the p-t y pe silicon carbide semiconductor body; forming an insulator layer comprising a hexagonal boron nitride on a surface of the graphene layer; and forming, on a surface of the insulator la y er, the metal electrode, the metal electrode being in ohmic contact with the p-type silicon carbide semiconductor body. Currently amended
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming a laminated layer including one to three graphene laminated layers. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming a graphene layer includes forming the graphene layer on the p- type silicon carbide semiconductor body so that coverage of the graphene layer that is a ratio of an area of a surface area of the p-type silicon carbide semiconductor body covered by the graphene layer to a total surface area of the p-type silicon carbide semiconductor body is equal to or greater than % of a surface area of the p-type silicon carbide semiconductor body. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the p-type silicon carbide semiconductor body include a carrier concentration that is equal to or greater than i x 10 16/cm 3. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the metal electrode comprised of one or more material selected from a group consisting of gold, silver, platinum, titanium, nickel, iron, cobalt, copper, chromium, aluminum, palladium, and an alloy thereof. Original
: The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the forming an insulator layer includes forming one insulator layer or two laminated insulator layers. Original
Layer stacks claimed or described, ordered top of device to substrate.
silicon carbide semiconductor device with ohmic contact
Materials described outside the worked examples.
graphene
p-type silicon carbide semiconductor body
SiC
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
contact resistance of p-type SiC and metal electrode by silicidation (prior art, insufficient) | 0.01–0.001 Ω·cm² | SiC |
contact resistance of n-type SiC semiconductor device region and metal electrode by silicidation (prior art, sufficient) |
Related documents with shared materials, methods, properties, or citations.
metal electrode
hexagonal boron nitride
h-BN
| — |
Pressure | 0.1 Pa | — |
metal electrode
hexagonal boron nitride
h-BN
| — |
Pressure | 0.1 Pa | — |
metal electrode
hexagonal boron nitride
h-BN
| — |
Pressure | 0.1 Pa | — |
metal electrode
hexagonal boron nitride
h-BN
| — |
Pressure | 0.1 Pa | — |