Patent
US 10,439,051METHODS RELATED TO SEMICONDUCTOR STRUCTURE WITH GALLIUM ARSENIDE AND TANTALUM NITRIDE
Cristian Cismaru
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,439,051Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Figure 2 shows that in some implementations, a circuit can include the Schottky diode and/or the HBT of
Figure 1.
Figure 3A shows that one or more circuits of
Figure 3B shows that one or more circuits of
Figure 4A schematically shows that in some implementations, a packaged module can include one or more circuits of
Figures 4B and 4 C show different views of a more specific example of the packaged module of
Figure 5A schematically shows that in some implementations, a radio-frequency (RF) device such as a wireless device can include the module of
Figure 4.
Figure 5B shows a more specific example of a wireless device.
Figure 6 shows an example configuration of an HBT structure.
Figure 7 shows that in some embodiments, a process for fabricating the HBT of
Figure 8 shows a layout view of the example structure of
Figure 9 shows forward and reverse I -V curves of a sample Schottky device having one or more features described herein.
Figure 10 shows a clamp voltage distribution for a sample Schottky device having one or more features described herein.
Figure 11 shows a process that can be implemented to fabricate the example Schottky structure of
Figure 12 shows a process that can be implemented to fabricate the example HBT structure of
Figure 13 shows a process that can be implemented as a more specific example of the process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor structure, the method comprising: forming a subcollector layer over a gallium arsenide substrate; forming a collector layer over and in physical contact with the sub-collector layer; and forming a tantalum nitride layer over the collector layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being planar and in physical contact with the collector layer. Previously presented
The method of claim 1, further comprising: forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the sub-collector layer to yield a Schottky diode with the first electrical contact being an anode and the second electrical contact being a cathode. Previously presented
The method of claim 1, wherein the tantalum nitride layer, the collector layer, and the subcollector layer are included in a Schottky diode. Previously presented
The method of claim 1, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the collector layer opposite the sub-collector layer. Previously presented
The method of claim 1, further comprising: forming an isolation implant region having a surface that is co-planar with a surface of the sub-collector layer. Previously presented
Canceled
Canceled
Canceled
A method of fabricating a Schottky diode, the method comprising: forming a doped gallium arsenide layer over a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being in physical contact with the doped gallium arsenide layer; forming a passivation structure such that the tantalum nitride layer and the passivation structure are in physical contact with and fully covering the doped gallium arsenide layer opposite the second doped gallium arsenide layer; and forming a cathode in physical contact with the second doped gallium arsenide layer on opposing sides of the tantalum nitride layer; the doped gallium arsenide layer, the tantalum nitride layer, and the cathode layer being included in the Schottky diode. Previously presented
The method of claim 12, further comprising: forming an anode of the Schottky diode on the tantalum nitride layer. Previously presented
The method of claim 12, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of less than 0.45 Volts. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of about 0.42 Volts. Previously presented
The method of claim 12, wherein the doped gallium arsenide layer is a collector layer, and the second doped gallium arsenide layer is a sub-collector layer. Previously presented
A method of fabricating a semiconductor structure, the method comprising: forming a doped gallium arsenide layer over and in physical contact with a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top side and a bottom side, and an entirety of the bottom side of the tantalum nitride layer being planar and in physical contact with the doped gallium arsenide layer; and forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the second doped gallium arsenide layer such that the first electrical contact is an anode of a Schottky diode and the second electrical contact is a cathode of the Schottky diode. Previously presented
The method of claim 18, wherein the Schottky diode has a turn on voltage of less than 0.5 Volts. Previously presented
The method of claim 18, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 18, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the doped gallium arsenide layer opposite the second doped gallium arsenide layer. Previously presented
The method of claim 18, f urther comprising: forming a cathode of the Schottky diode, the cathode including an electrical contact contacting the second doped gallium arsenide layer on opposing side of the doped gallium arsenide layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
Schottky diode with TaN/GaAs junction on GaAs substrate
Heterojunction Bipolar Transistor (HBT) with integrated Schottky diode
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
tantalum nitride layer
TaN
Measurements and analyses referenced in the patent, with their drawing references.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky diode turn-on voltage (claimed upper bound, claim 5) | ≤ 0.45 V | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,439,051Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Figure 2 shows that in some implementations, a circuit can include the Schottky diode and/or the HBT of
Figure 1.
Figure 3A shows that one or more circuits of
Figure 3B shows that one or more circuits of
Figure 4A schematically shows that in some implementations, a packaged module can include one or more circuits of
Figures 4B and 4 C show different views of a more specific example of the packaged module of
Figure 5A schematically shows that in some implementations, a radio-frequency (RF) device such as a wireless device can include the module of
Figure 4.
Figure 5B shows a more specific example of a wireless device.
Figure 6 shows an example configuration of an HBT structure.
Figure 7 shows that in some embodiments, a process for fabricating the HBT of
Figure 8 shows a layout view of the example structure of
Figure 9 shows forward and reverse I -V curves of a sample Schottky device having one or more features described herein.
Figure 10 shows a clamp voltage distribution for a sample Schottky device having one or more features described herein.
Figure 11 shows a process that can be implemented to fabricate the example Schottky structure of
Figure 12 shows a process that can be implemented to fabricate the example HBT structure of
Figure 13 shows a process that can be implemented as a more specific example of the process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor structure, the method comprising: forming a subcollector layer over a gallium arsenide substrate; forming a collector layer over and in physical contact with the sub-collector layer; and forming a tantalum nitride layer over the collector layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being planar and in physical contact with the collector layer. Previously presented
The method of claim 1, further comprising: forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the sub-collector layer to yield a Schottky diode with the first electrical contact being an anode and the second electrical contact being a cathode. Previously presented
The method of claim 1, wherein the tantalum nitride layer, the collector layer, and the subcollector layer are included in a Schottky diode. Previously presented
The method of claim 1, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the collector layer opposite the sub-collector layer. Previously presented
The method of claim 1, further comprising: forming an isolation implant region having a surface that is co-planar with a surface of the sub-collector layer. Previously presented
Canceled
Canceled
Canceled
A method of fabricating a Schottky diode, the method comprising: forming a doped gallium arsenide layer over a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being in physical contact with the doped gallium arsenide layer; forming a passivation structure such that the tantalum nitride layer and the passivation structure are in physical contact with and fully covering the doped gallium arsenide layer opposite the second doped gallium arsenide layer; and forming a cathode in physical contact with the second doped gallium arsenide layer on opposing sides of the tantalum nitride layer; the doped gallium arsenide layer, the tantalum nitride layer, and the cathode layer being included in the Schottky diode. Previously presented
The method of claim 12, further comprising: forming an anode of the Schottky diode on the tantalum nitride layer. Previously presented
The method of claim 12, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of less than 0.45 Volts. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of about 0.42 Volts. Previously presented
The method of claim 12, wherein the doped gallium arsenide layer is a collector layer, and the second doped gallium arsenide layer is a sub-collector layer. Previously presented
A method of fabricating a semiconductor structure, the method comprising: forming a doped gallium arsenide layer over and in physical contact with a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top side and a bottom side, and an entirety of the bottom side of the tantalum nitride layer being planar and in physical contact with the doped gallium arsenide layer; and forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the second doped gallium arsenide layer such that the first electrical contact is an anode of a Schottky diode and the second electrical contact is a cathode of the Schottky diode. Previously presented
The method of claim 18, wherein the Schottky diode has a turn on voltage of less than 0.5 Volts. Previously presented
The method of claim 18, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 18, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the doped gallium arsenide layer opposite the second doped gallium arsenide layer. Previously presented
The method of claim 18, f urther comprising: forming a cathode of the Schottky diode, the cathode including an electrical contact contacting the second doped gallium arsenide layer on opposing side of the doped gallium arsenide layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
Schottky diode with TaN/GaAs junction on GaAs substrate
Heterojunction Bipolar Transistor (HBT) with integrated Schottky diode
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
tantalum nitride layer
TaN
Measurements and analyses referenced in the patent, with their drawing references.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky diode turn-on voltage (claimed upper bound, claim 5) | ≤ 0.45 V | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,439,051Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Figure 2 shows that in some implementations, a circuit can include the Schottky diode and/or the HBT of
Figure 1.
Figure 3A shows that one or more circuits of
Figure 3B shows that one or more circuits of
Figure 4A schematically shows that in some implementations, a packaged module can include one or more circuits of
Figures 4B and 4 C show different views of a more specific example of the packaged module of
Figure 5A schematically shows that in some implementations, a radio-frequency (RF) device such as a wireless device can include the module of
Figure 4.
Figure 5B shows a more specific example of a wireless device.
Figure 6 shows an example configuration of an HBT structure.
Figure 7 shows that in some embodiments, a process for fabricating the HBT of
Figure 8 shows a layout view of the example structure of
Figure 9 shows forward and reverse I -V curves of a sample Schottky device having one or more features described herein.
Figure 10 shows a clamp voltage distribution for a sample Schottky device having one or more features described herein.
Figure 11 shows a process that can be implemented to fabricate the example Schottky structure of
Figure 12 shows a process that can be implemented to fabricate the example HBT structure of
Figure 13 shows a process that can be implemented as a more specific example of the process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor structure, the method comprising: forming a subcollector layer over a gallium arsenide substrate; forming a collector layer over and in physical contact with the sub-collector layer; and forming a tantalum nitride layer over the collector layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being planar and in physical contact with the collector layer. Previously presented
The method of claim 1, further comprising: forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the sub-collector layer to yield a Schottky diode with the first electrical contact being an anode and the second electrical contact being a cathode. Previously presented
The method of claim 1, wherein the tantalum nitride layer, the collector layer, and the subcollector layer are included in a Schottky diode. Previously presented
The method of claim 1, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the collector layer opposite the sub-collector layer. Previously presented
The method of claim 1, further comprising: forming an isolation implant region having a surface that is co-planar with a surface of the sub-collector layer. Previously presented
Canceled
Canceled
Canceled
A method of fabricating a Schottky diode, the method comprising: forming a doped gallium arsenide layer over a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being in physical contact with the doped gallium arsenide layer; forming a passivation structure such that the tantalum nitride layer and the passivation structure are in physical contact with and fully covering the doped gallium arsenide layer opposite the second doped gallium arsenide layer; and forming a cathode in physical contact with the second doped gallium arsenide layer on opposing sides of the tantalum nitride layer; the doped gallium arsenide layer, the tantalum nitride layer, and the cathode layer being included in the Schottky diode. Previously presented
The method of claim 12, further comprising: forming an anode of the Schottky diode on the tantalum nitride layer. Previously presented
The method of claim 12, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of less than 0.45 Volts. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of about 0.42 Volts. Previously presented
The method of claim 12, wherein the doped gallium arsenide layer is a collector layer, and the second doped gallium arsenide layer is a sub-collector layer. Previously presented
A method of fabricating a semiconductor structure, the method comprising: forming a doped gallium arsenide layer over and in physical contact with a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top side and a bottom side, and an entirety of the bottom side of the tantalum nitride layer being planar and in physical contact with the doped gallium arsenide layer; and forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the second doped gallium arsenide layer such that the first electrical contact is an anode of a Schottky diode and the second electrical contact is a cathode of the Schottky diode. Previously presented
The method of claim 18, wherein the Schottky diode has a turn on voltage of less than 0.5 Volts. Previously presented
The method of claim 18, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 18, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the doped gallium arsenide layer opposite the second doped gallium arsenide layer. Previously presented
The method of claim 18, f urther comprising: forming a cathode of the Schottky diode, the cathode including an electrical contact contacting the second doped gallium arsenide layer on opposing side of the doped gallium arsenide layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
Schottky diode with TaN/GaAs junction on GaAs substrate
Heterojunction Bipolar Transistor (HBT) with integrated Schottky diode
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
tantalum nitride layer
TaN
Measurements and analyses referenced in the patent, with their drawing references.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky diode turn-on voltage (claimed upper bound, claim 5) | ≤ 0.45 V | GaAs |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,439,051Patent drawings and their descriptions. Click a drawing to enlarge it.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Figure 2 shows that in some implementations, a circuit can include the Schottky diode and/or the HBT of
Figure 1.
Figure 3A shows that one or more circuits of
Figure 3B shows that one or more circuits of
Figure 4A schematically shows that in some implementations, a packaged module can include one or more circuits of
Figures 4B and 4 C show different views of a more specific example of the packaged module of
Figure 5A schematically shows that in some implementations, a radio-frequency (RF) device such as a wireless device can include the module of
Figure 4.
Figure 5B shows a more specific example of a wireless device.
Figure 6 shows an example configuration of an HBT structure.
Figure 7 shows that in some embodiments, a process for fabricating the HBT of
Figure 8 shows a layout view of the example structure of
Figure 9 shows forward and reverse I -V curves of a sample Schottky device having one or more features described herein.
Figure 10 shows a clamp voltage distribution for a sample Schottky device having one or more features described herein.
Figure 11 shows a process that can be implemented to fabricate the example Schottky structure of
Figure 12 shows a process that can be implemented to fabricate the example HBT structure of
Figure 13 shows a process that can be implemented as a more specific example of the process of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor structure, the method comprising: forming a subcollector layer over a gallium arsenide substrate; forming a collector layer over and in physical contact with the sub-collector layer; and forming a tantalum nitride layer over the collector layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being planar and in physical contact with the collector layer. Previously presented
The method of claim 1, further comprising: forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the sub-collector layer to yield a Schottky diode with the first electrical contact being an anode and the second electrical contact being a cathode. Previously presented
The method of claim 1, wherein the tantalum nitride layer, the collector layer, and the subcollector layer are included in a Schottky diode. Previously presented
The method of claim 1, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the collector layer opposite the sub-collector layer. Previously presented
The method of claim 1, further comprising: forming an isolation implant region having a surface that is co-planar with a surface of the sub-collector layer. Previously presented
Canceled
Canceled
Canceled
A method of fabricating a Schottky diode, the method comprising: forming a doped gallium arsenide layer over a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top surface and a bottom surface, and an entirety of the bottom surface being in physical contact with the doped gallium arsenide layer; forming a passivation structure such that the tantalum nitride layer and the passivation structure are in physical contact with and fully covering the doped gallium arsenide layer opposite the second doped gallium arsenide layer; and forming a cathode in physical contact with the second doped gallium arsenide layer on opposing sides of the tantalum nitride layer; the doped gallium arsenide layer, the tantalum nitride layer, and the cathode layer being included in the Schottky diode. Previously presented
The method of claim 12, further comprising: forming an anode of the Schottky diode on the tantalum nitride layer. Previously presented
The method of claim 12, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of less than 0.45 Volts. Previously presented
The method of claim 12, wherein the Schottky diode has a turn-on voltage of about 0.42 Volts. Previously presented
The method of claim 12, wherein the doped gallium arsenide layer is a collector layer, and the second doped gallium arsenide layer is a sub-collector layer. Previously presented
A method of fabricating a semiconductor structure, the method comprising: forming a doped gallium arsenide layer over and in physical contact with a second doped gallium arsenide layer; forming a tantalum nitride layer over the doped gallium arsenide layer, the tantalum nitride layer including a top side and a bottom side, and an entirety of the bottom side of the tantalum nitride layer being planar and in physical contact with the doped gallium arsenide layer; and forming a first electrical contact on the tantalum nitride layer and a second electrical contact on the second doped gallium arsenide layer such that the first electrical contact is an anode of a Schottky diode and the second electrical contact is a cathode of the Schottky diode. Previously presented
The method of claim 18, wherein the Schottky diode has a turn on voltage of less than 0.5 Volts. Previously presented
The method of claim 18, wherein the cathode has an inverted-U shaped footprint. Previously presented
The method of claim 18, further comprising: forming a passivation layer such that the tantalum nitride layer and the passivation layer are in physical contact with and fully cover the doped gallium arsenide layer opposite the second doped gallium arsenide layer. Previously presented
The method of claim 18, f urther comprising: forming a cathode of the Schottky diode, the cathode including an electrical contact contacting the second doped gallium arsenide layer on opposing side of the doped gallium arsenide layer. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
Schottky diode with TaN/GaAs junction on GaAs substrate
Heterojunction Bipolar Transistor (HBT) with integrated Schottky diode
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
tantalum nitride layer
TaN
Measurements and analyses referenced in the patent, with their drawing references.
Figures 1 A and 1 B schematically depict a Schottky diode and a heterojunction bipolar transistor (HBT) having one or more features as described herein.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Schottky diode turn-on voltage (claimed upper bound, claim 5) | ≤ 0.45 V | GaAs |
Related documents with shared materials, methods, properties, or citations.
passivation layer
n- InGaP emitter layer
InGaP
Schottky diode turn-on voltage (claimed value, claim 16) | 0.42 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 15) | ≤ 0.45 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 19) | ≤ 0.5 V | GaAsTaN |
Schottky diode turn-on voltage (claimed value, claim 23) | 0.42 V | GaAsTaN |
Typical GaAs HBT/BiFET Schottky diode turn-on voltage (background/prior art reference value) | 0.7 V | — |
Voltage | 0.42–0.7 V | — |
Thickness | 10–200 nm | — |
Thickness | 20–100 nm | — |
Thickness | 30–70 nm | — |
Thickness | 40–60 nm | — |
Voltage | ≤ 0.6 V | — |
passivation layer
n- InGaP emitter layer
InGaP
Schottky diode turn-on voltage (claimed value, claim 16) | 0.42 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 15) | ≤ 0.45 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 19) | ≤ 0.5 V | GaAsTaN |
Schottky diode turn-on voltage (claimed value, claim 23) | 0.42 V | GaAsTaN |
Typical GaAs HBT/BiFET Schottky diode turn-on voltage (background/prior art reference value) | 0.7 V | — |
Voltage | 0.42–0.7 V | — |
Thickness | 10–200 nm | — |
Thickness | 20–100 nm | — |
Thickness | 30–70 nm | — |
Thickness | 40–60 nm | — |
Voltage | ≤ 0.6 V | — |
passivation layer
n- InGaP emitter layer
InGaP
Schottky diode turn-on voltage (claimed value, claim 16) | 0.42 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 15) | ≤ 0.45 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 19) | ≤ 0.5 V | GaAsTaN |
Schottky diode turn-on voltage (claimed value, claim 23) | 0.42 V | GaAsTaN |
Typical GaAs HBT/BiFET Schottky diode turn-on voltage (background/prior art reference value) | 0.7 V | — |
Voltage | 0.42–0.7 V | — |
Thickness | 10–200 nm | — |
Thickness | 20–100 nm | — |
Thickness | 30–70 nm | — |
Thickness | 40–60 nm | — |
Voltage | ≤ 0.6 V | — |
passivation layer
n- InGaP emitter layer
InGaP
Schottky diode turn-on voltage (claimed value, claim 16) | 0.42 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 15) | ≤ 0.45 V | GaAsTaN |
Schottky diode turn-on voltage (claimed upper bound, claim 19) | ≤ 0.5 V | GaAsTaN |
Schottky diode turn-on voltage (claimed value, claim 23) | 0.42 V | GaAsTaN |
Typical GaAs HBT/BiFET Schottky diode turn-on voltage (background/prior art reference value) | 0.7 V | — |
Voltage | 0.42–0.7 V | — |
Thickness | 10–200 nm | — |
Thickness | 20–100 nm | — |
Thickness | 30–70 nm | — |
Thickness | 40–60 nm | — |
Voltage | ≤ 0.6 V | — |