Patent
US 8,618,587QUANTUM WELL GRAPHENE STRUCTURE FORMED ON A DIELECTRIC LAYER HAVING A FLAT SURFACE
Ernesto E. Marinero
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic, cross sectional view of a structure employing graphene according to an embodiment of the invention; 10
FIG. 2 is a schematic, cross sectional view of a structure employing graphene according to an alternate embodiment of the invention;
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
FIG. 4 is a top down view of the structure of
FIG. 5. DETA I LED DESCR I PTION OF T IE PREFERRED EMBOD IhAENTS The following description is of the best embodiments presently contemplated for carrying out …
FIG. 6 is a view of the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: an under-layer constructed of a dielectric material and having a surface with a root mean square roughness of less than 0.5 nm; and a layer of n-graphene formed on the under-layer; wherein the under-layer comprises HfO 2, A₁ 2O 3, Si 3 N4, Y 20 3, PrO, GdO, La 2O3, TiO, ZrO, A l N, BN, Ta 205, Ba XSr(x), Ti O 3, Pb XZr(x), or Ti O3.
An electronic device as in claim 1 wherein further comprising an over- layer formed of a dielectric material, the layer of n-graphene being formed between the under-layer and the overlayer.
The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface.
The electric device as in claim 1 wherein the under-layer is constructed of a highly ordered crystalline material. original
The electronic device as in claim 1 wherein the under-layer has a dielectric constant of at least
canceled
An electronic device, comprising: an under-layer formed of a dielectric material and having a root mean square surface roughness of less than 0.5 nm; an interfacial layer formed on the underlayer; and HIT₁P₄₂₅A/HSJ₉-2009-0036US₂ 3 an n-graphene layer formed on the interfacial layer.
The electronic device as in claim 11 further comprising: a second interfacial layer formed over the n-graphene layer; and a over-layer formed over the second interfacial layer.
The electronic device as in claim 11 the interfacial layer comprises a material having a weak frequency dependence of its dielectric constant.
The electronic device as in claim 11 wherein the interfacial layer has a thickness that is not greater than 10 nm.
The electronic device as in claim 11 wherein the interfacial layer comprises a self-assembled mono-layer. HIT₁P₄₂ 5A/HSJ₉-2009-0036US₂ 4
The electronic device as in claim 11 wherein the interfacial layer comprises 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a- methylstyrene), polyethylene, polypropylene or polystyrene.
Layer stacks claimed or described, ordered top of device to substrate.
quantum well graphene electronic device
quantum well graphene electronic device with interfacial layers
Materials described outside the worked examples.
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon nitride
Si₃N₄
yttrium oxide
Y₂O₃
praseodymium oxide
PrO
gadolinium oxide
GdO
lanthanum oxide
La₂O₃
titanium oxide
TiO
zirconium oxide
ZrO
aluminum nitride
AlN
boron nitride
BN
tantalum pentoxide
Ta₂O₅
barium strontium titanate
BaxSr(1-x)TiO₃
lead zirconate titanate
PbxZr(1-x)TiO₃
titanium oxide (rutile/anatase)
TiO₃
n-graphene
interfacial layer material (non-polar dielectric)
18-phenoxyoctadecyl-trichlorosilane
octadecyltrichlorosilane
poly(alpha-methylstyrene)
polyethylene
polypropylene
polystyrene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.5 nm | — |
Thickness | ≥ 10 nm | — |
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic, cross sectional view of a structure employing graphene according to an embodiment of the invention; 10
FIG. 2 is a schematic, cross sectional view of a structure employing graphene according to an alternate embodiment of the invention;
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
FIG. 4 is a top down view of the structure of
FIG. 5. DETA I LED DESCR I PTION OF T IE PREFERRED EMBOD IhAENTS The following description is of the best embodiments presently contemplated for carrying out …
FIG. 6 is a view of the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: an under-layer constructed of a dielectric material and having a surface with a root mean square roughness of less than 0.5 nm; and a layer of n-graphene formed on the under-layer; wherein the under-layer comprises HfO 2, A₁ 2O 3, Si 3 N4, Y 20 3, PrO, GdO, La 2O3, TiO, ZrO, A l N, BN, Ta 205, Ba XSr(x), Ti O 3, Pb XZr(x), or Ti O3.
An electronic device as in claim 1 wherein further comprising an over- layer formed of a dielectric material, the layer of n-graphene being formed between the under-layer and the overlayer.
The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface.
The electric device as in claim 1 wherein the under-layer is constructed of a highly ordered crystalline material. original
The electronic device as in claim 1 wherein the under-layer has a dielectric constant of at least
canceled
An electronic device, comprising: an under-layer formed of a dielectric material and having a root mean square surface roughness of less than 0.5 nm; an interfacial layer formed on the underlayer; and HIT₁P₄₂₅A/HSJ₉-2009-0036US₂ 3 an n-graphene layer formed on the interfacial layer.
The electronic device as in claim 11 further comprising: a second interfacial layer formed over the n-graphene layer; and a over-layer formed over the second interfacial layer.
The electronic device as in claim 11 the interfacial layer comprises a material having a weak frequency dependence of its dielectric constant.
The electronic device as in claim 11 wherein the interfacial layer has a thickness that is not greater than 10 nm.
The electronic device as in claim 11 wherein the interfacial layer comprises a self-assembled mono-layer. HIT₁P₄₂ 5A/HSJ₉-2009-0036US₂ 4
The electronic device as in claim 11 wherein the interfacial layer comprises 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a- methylstyrene), polyethylene, polypropylene or polystyrene.
Layer stacks claimed or described, ordered top of device to substrate.
quantum well graphene electronic device
quantum well graphene electronic device with interfacial layers
Materials described outside the worked examples.
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon nitride
Si₃N₄
yttrium oxide
Y₂O₃
praseodymium oxide
PrO
gadolinium oxide
GdO
lanthanum oxide
La₂O₃
titanium oxide
TiO
zirconium oxide
ZrO
aluminum nitride
AlN
boron nitride
BN
tantalum pentoxide
Ta₂O₅
barium strontium titanate
BaxSr(1-x)TiO₃
lead zirconate titanate
PbxZr(1-x)TiO₃
titanium oxide (rutile/anatase)
TiO₃
n-graphene
interfacial layer material (non-polar dielectric)
18-phenoxyoctadecyl-trichlorosilane
octadecyltrichlorosilane
poly(alpha-methylstyrene)
polyethylene
polypropylene
polystyrene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.5 nm | — |
Thickness | ≥ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF
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ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
Landau Zener Interaction Enhanced Quantum Sensing in Spin Defects of Hexagonal Boron Nitride
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic, cross sectional view of a structure employing graphene according to an embodiment of the invention; 10
FIG. 2 is a schematic, cross sectional view of a structure employing graphene according to an alternate embodiment of the invention;
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
FIG. 4 is a top down view of the structure of
FIG. 5. DETA I LED DESCR I PTION OF T IE PREFERRED EMBOD IhAENTS The following description is of the best embodiments presently contemplated for carrying out …
FIG. 6 is a view of the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: an under-layer constructed of a dielectric material and having a surface with a root mean square roughness of less than 0.5 nm; and a layer of n-graphene formed on the under-layer; wherein the under-layer comprises HfO 2, A₁ 2O 3, Si 3 N4, Y 20 3, PrO, GdO, La 2O3, TiO, ZrO, A l N, BN, Ta 205, Ba XSr(x), Ti O 3, Pb XZr(x), or Ti O3.
An electronic device as in claim 1 wherein further comprising an over- layer formed of a dielectric material, the layer of n-graphene being formed between the under-layer and the overlayer.
The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface.
The electric device as in claim 1 wherein the under-layer is constructed of a highly ordered crystalline material. original
The electronic device as in claim 1 wherein the under-layer has a dielectric constant of at least
canceled
An electronic device, comprising: an under-layer formed of a dielectric material and having a root mean square surface roughness of less than 0.5 nm; an interfacial layer formed on the underlayer; and HIT₁P₄₂₅A/HSJ₉-2009-0036US₂ 3 an n-graphene layer formed on the interfacial layer.
The electronic device as in claim 11 further comprising: a second interfacial layer formed over the n-graphene layer; and a over-layer formed over the second interfacial layer.
The electronic device as in claim 11 the interfacial layer comprises a material having a weak frequency dependence of its dielectric constant.
The electronic device as in claim 11 wherein the interfacial layer has a thickness that is not greater than 10 nm.
The electronic device as in claim 11 wherein the interfacial layer comprises a self-assembled mono-layer. HIT₁P₄₂ 5A/HSJ₉-2009-0036US₂ 4
The electronic device as in claim 11 wherein the interfacial layer comprises 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a- methylstyrene), polyethylene, polypropylene or polystyrene.
Layer stacks claimed or described, ordered top of device to substrate.
quantum well graphene electronic device
quantum well graphene electronic device with interfacial layers
Materials described outside the worked examples.
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon nitride
Si₃N₄
yttrium oxide
Y₂O₃
praseodymium oxide
PrO
gadolinium oxide
GdO
lanthanum oxide
La₂O₃
titanium oxide
TiO
zirconium oxide
ZrO
aluminum nitride
AlN
boron nitride
BN
tantalum pentoxide
Ta₂O₅
barium strontium titanate
BaxSr(1-x)TiO₃
lead zirconate titanate
PbxZr(1-x)TiO₃
titanium oxide (rutile/anatase)
TiO₃
n-graphene
interfacial layer material (non-polar dielectric)
18-phenoxyoctadecyl-trichlorosilane
octadecyltrichlorosilane
poly(alpha-methylstyrene)
polyethylene
polypropylene
polystyrene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.5 nm | — |
Thickness | ≥ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF
METHOD OF MANUFACTURING GATE STRUCTURE FOR GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
Landau Zener Interaction Enhanced Quantum Sensing in Spin Defects of Hexagonal Boron Nitride
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a schematic, cross sectional view of a structure employing graphene according to an embodiment of the invention; 10
FIG. 2 is a schematic, cross sectional view of a structure employing graphene according to an alternate embodiment of the invention;
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
FIG. 4 is a top down view of the structure of
FIG. 5. DETA I LED DESCR I PTION OF T IE PREFERRED EMBOD IhAENTS The following description is of the best embodiments presently contemplated for carrying out …
FIG. 6 is a view of the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device, comprising: an under-layer constructed of a dielectric material and having a surface with a root mean square roughness of less than 0.5 nm; and a layer of n-graphene formed on the under-layer; wherein the under-layer comprises HfO 2, A₁ 2O 3, Si 3 N4, Y 20 3, PrO, GdO, La 2O3, TiO, ZrO, A l N, BN, Ta 205, Ba XSr(x), Ti O 3, Pb XZr(x), or Ti O3.
An electronic device as in claim 1 wherein further comprising an over- layer formed of a dielectric material, the layer of n-graphene being formed between the under-layer and the overlayer.
The electronic device as in claim 1 wherein the over-layer has a substantially atomically flat surface.
The electric device as in claim 1 wherein the under-layer is constructed of a highly ordered crystalline material. original
The electronic device as in claim 1 wherein the under-layer has a dielectric constant of at least
canceled
An electronic device, comprising: an under-layer formed of a dielectric material and having a root mean square surface roughness of less than 0.5 nm; an interfacial layer formed on the underlayer; and HIT₁P₄₂₅A/HSJ₉-2009-0036US₂ 3 an n-graphene layer formed on the interfacial layer.
The electronic device as in claim 11 further comprising: a second interfacial layer formed over the n-graphene layer; and a over-layer formed over the second interfacial layer.
The electronic device as in claim 11 the interfacial layer comprises a material having a weak frequency dependence of its dielectric constant.
The electronic device as in claim 11 wherein the interfacial layer has a thickness that is not greater than 10 nm.
The electronic device as in claim 11 wherein the interfacial layer comprises a self-assembled mono-layer. HIT₁P₄₂ 5A/HSJ₉-2009-0036US₂ 4
The electronic device as in claim 11 wherein the interfacial layer comprises 18-phenoxyoctadecyl)-trichlorsilane, octadecyltrichlorsilane, poly(a- methylstyrene), polyethylene, polypropylene or polystyrene.
Layer stacks claimed or described, ordered top of device to substrate.
quantum well graphene electronic device
quantum well graphene electronic device with interfacial layers
Materials described outside the worked examples.
hafnium oxide
HfO₂
aluminum oxide
Al₂O₃
silicon nitride
Si₃N₄
yttrium oxide
Y₂O₃
praseodymium oxide
PrO
gadolinium oxide
GdO
lanthanum oxide
La₂O₃
titanium oxide
TiO
zirconium oxide
ZrO
aluminum nitride
AlN
boron nitride
BN
tantalum pentoxide
Ta₂O₅
barium strontium titanate
BaxSr(1-x)TiO₃
lead zirconate titanate
PbxZr(1-x)TiO₃
titanium oxide (rutile/anatase)
TiO₃
n-graphene
interfacial layer material (non-polar dielectric)
18-phenoxyoctadecyl-trichlorosilane
octadecyltrichlorosilane
poly(alpha-methylstyrene)
polyethylene
polypropylene
polystyrene
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is a schematic, cross sectional showing a graphene st r uct u re employed in a field effect transistor illustrating a possible application of a graphene …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 0.5 nm | — |
Thickness | ≥ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR AND GATE STRUCTURE THEREOF
METHOD OF MANUFACTURING GATE STRUCTURE FOR GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
ENHANCEMENT-MODE N-CHANNEL AND P-CHANNEL GAN DEVICE INTEGRATION STRUCTURE
GaN-BASED BIDIRECTIONAL SWITCH DEVICE
Landau Zener Interaction Enhanced Quantum Sensing in Spin Defects of Hexagonal Boron Nitride