Patent
US 10,651,279SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING GRAPHENE-CAPPED METAL INTERCONNECTS
Shin-Yi YANG
US
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Patent
Atlas literature
Patent
US 10,651,279Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a substrate; a metal layer formed on the substrate; a dielectric layer formed on the metal layer; a first conductive layer formed in the dielectric layer and on a portion of the metal layer; a graphene barrier layer formed at least on side surfaces of the dielectric layer and on the first conductive layer; and a second conductive layer formed in the dielectric layer and on the graphene barrier layer. Currently amended
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer comprises one or more layers of graphene. Original
The semiconductor structure of claim 1, wherein the first conductive layer is formed directly on the portion of the metal layer. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of less than 10 angstroms. Original
The semiconductor structure of claim 1, wherein at least a portion of the graphene barrier layer is between the first and second conductive layers. Original
The semiconductor structure of claim 1, wherein the first and second conductive layers comprise different materials. Original
The semiconductor structure of claim 1, wherein the first conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Original
The semiconductor structure of claim 1, wherein a top surface of the second conductive layer is coplanar with a top surface of the dielectric layer. Original
A semiconductor structure, comprising: a conductive interconnect layer; a dielectric layer formed over the conductive interconnect layer; a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer; a second conductive layer formed in the dielectric layer and over the first conductive layer, the second conductive layer comprising at least one sidewall; and a graphene barrier layer formed between the first and second conductive layers and between the at least one sidewall of the second conductive layer and the dielectric layer. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness less than about 10 angstroms.
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 11, wherein the [[first]] second conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer comprises one or more layers of graphene. Original
A semiconductor interconnect structure, comprising: a substrate; a conductive interconnect layer on the substrate; a patterned dielectric layer over the substrate and over a portion of the conductive interconnect layer, the patterned dielectric layer comprising a pair of opposing sidewall surfaces; a first conductive layer on the conductive interconnect layer; a graphene layer formed on the first conductive layer and on the pair of opposing sidewall surfaces of the patterned dielectric layer; and a second conductive layer formed on the graphene layer, wherein at least a portion of the second conductive layer is between the pair of opposing sidewall surfaces of the patterned dielectric la y er. Currently amended
The semiconductor interconnect structure of claim 16, wherein the graphene layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers are formed in a via and a trench, respectively. Original
The semiconductor interconnect structure of claim 16, wherein the patterned dielectric layer further comprises a top surface, and the least one portion of the second conductive layer is formed below the top surface of the patterned dielectric layer. Currently amended
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers comprise different materials. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor interconnect structure with graphene barrier layer (claim 1)
Materials described outside the worked examples.
graphene barrier layer
first conductive layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–2000 Å | — |
Thickness | 10–5000 Å |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,279Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a substrate; a metal layer formed on the substrate; a dielectric layer formed on the metal layer; a first conductive layer formed in the dielectric layer and on a portion of the metal layer; a graphene barrier layer formed at least on side surfaces of the dielectric layer and on the first conductive layer; and a second conductive layer formed in the dielectric layer and on the graphene barrier layer. Currently amended
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer comprises one or more layers of graphene. Original
The semiconductor structure of claim 1, wherein the first conductive layer is formed directly on the portion of the metal layer. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of less than 10 angstroms. Original
The semiconductor structure of claim 1, wherein at least a portion of the graphene barrier layer is between the first and second conductive layers. Original
The semiconductor structure of claim 1, wherein the first and second conductive layers comprise different materials. Original
The semiconductor structure of claim 1, wherein the first conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Original
The semiconductor structure of claim 1, wherein a top surface of the second conductive layer is coplanar with a top surface of the dielectric layer. Original
A semiconductor structure, comprising: a conductive interconnect layer; a dielectric layer formed over the conductive interconnect layer; a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer; a second conductive layer formed in the dielectric layer and over the first conductive layer, the second conductive layer comprising at least one sidewall; and a graphene barrier layer formed between the first and second conductive layers and between the at least one sidewall of the second conductive layer and the dielectric layer. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness less than about 10 angstroms.
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 11, wherein the [[first]] second conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer comprises one or more layers of graphene. Original
A semiconductor interconnect structure, comprising: a substrate; a conductive interconnect layer on the substrate; a patterned dielectric layer over the substrate and over a portion of the conductive interconnect layer, the patterned dielectric layer comprising a pair of opposing sidewall surfaces; a first conductive layer on the conductive interconnect layer; a graphene layer formed on the first conductive layer and on the pair of opposing sidewall surfaces of the patterned dielectric layer; and a second conductive layer formed on the graphene layer, wherein at least a portion of the second conductive layer is between the pair of opposing sidewall surfaces of the patterned dielectric la y er. Currently amended
The semiconductor interconnect structure of claim 16, wherein the graphene layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers are formed in a via and a trench, respectively. Original
The semiconductor interconnect structure of claim 16, wherein the patterned dielectric layer further comprises a top surface, and the least one portion of the second conductive layer is formed below the top surface of the patterned dielectric layer. Currently amended
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers comprise different materials. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor interconnect structure with graphene barrier layer (claim 1)
Materials described outside the worked examples.
graphene barrier layer
first conductive layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–2000 Å | — |
Thickness | 10–5000 Å |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,279Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a substrate; a metal layer formed on the substrate; a dielectric layer formed on the metal layer; a first conductive layer formed in the dielectric layer and on a portion of the metal layer; a graphene barrier layer formed at least on side surfaces of the dielectric layer and on the first conductive layer; and a second conductive layer formed in the dielectric layer and on the graphene barrier layer. Currently amended
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer comprises one or more layers of graphene. Original
The semiconductor structure of claim 1, wherein the first conductive layer is formed directly on the portion of the metal layer. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of less than 10 angstroms. Original
The semiconductor structure of claim 1, wherein at least a portion of the graphene barrier layer is between the first and second conductive layers. Original
The semiconductor structure of claim 1, wherein the first and second conductive layers comprise different materials. Original
The semiconductor structure of claim 1, wherein the first conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Original
The semiconductor structure of claim 1, wherein a top surface of the second conductive layer is coplanar with a top surface of the dielectric layer. Original
A semiconductor structure, comprising: a conductive interconnect layer; a dielectric layer formed over the conductive interconnect layer; a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer; a second conductive layer formed in the dielectric layer and over the first conductive layer, the second conductive layer comprising at least one sidewall; and a graphene barrier layer formed between the first and second conductive layers and between the at least one sidewall of the second conductive layer and the dielectric layer. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness less than about 10 angstroms.
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 11, wherein the [[first]] second conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer comprises one or more layers of graphene. Original
A semiconductor interconnect structure, comprising: a substrate; a conductive interconnect layer on the substrate; a patterned dielectric layer over the substrate and over a portion of the conductive interconnect layer, the patterned dielectric layer comprising a pair of opposing sidewall surfaces; a first conductive layer on the conductive interconnect layer; a graphene layer formed on the first conductive layer and on the pair of opposing sidewall surfaces of the patterned dielectric layer; and a second conductive layer formed on the graphene layer, wherein at least a portion of the second conductive layer is between the pair of opposing sidewall surfaces of the patterned dielectric la y er. Currently amended
The semiconductor interconnect structure of claim 16, wherein the graphene layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers are formed in a via and a trench, respectively. Original
The semiconductor interconnect structure of claim 16, wherein the patterned dielectric layer further comprises a top surface, and the least one portion of the second conductive layer is formed below the top surface of the patterned dielectric layer. Currently amended
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers comprise different materials. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor interconnect structure with graphene barrier layer (claim 1)
Materials described outside the worked examples.
graphene barrier layer
first conductive layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–2000 Å | — |
Thickness | 10–5000 Å |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,279Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure, comprising: a substrate; a metal layer formed on the substrate; a dielectric layer formed on the metal layer; a first conductive layer formed in the dielectric layer and on a portion of the metal layer; a graphene barrier layer formed at least on side surfaces of the dielectric layer and on the first conductive layer; and a second conductive layer formed in the dielectric layer and on the graphene barrier layer. Currently amended
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer comprises one or more layers of graphene. Original
The semiconductor structure of claim 1, wherein the first conductive layer is formed directly on the portion of the metal layer. Original
The semiconductor structure of claim 1, wherein the graphene barrier layer has a thickness in a range of less than 10 angstroms. Original
The semiconductor structure of claim 1, wherein at least a portion of the graphene barrier layer is between the first and second conductive layers. Original
The semiconductor structure of claim 1, wherein the first and second conductive layers comprise different materials. Original
The semiconductor structure of claim 1, wherein the first conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Original
The semiconductor structure of claim 1, wherein a top surface of the second conductive layer is coplanar with a top surface of the dielectric layer. Original
A semiconductor structure, comprising: a conductive interconnect layer; a dielectric layer formed over the conductive interconnect layer; a first conductive layer formed in the dielectric layer and in contact with a portion of the conductive interconnect layer; a second conductive layer formed in the dielectric layer and over the first conductive layer, the second conductive layer comprising at least one sidewall; and a graphene barrier layer formed between the first and second conductive layers and between the at least one sidewall of the second conductive layer and the dielectric layer. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness less than about 10 angstroms.
The semiconductor structure of claim 11, wherein the graphene barrier layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor structure of claim 11, wherein the [[first]] second conductive layer comprises silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof. Currently amended
The semiconductor structure of claim 11, wherein the graphene barrier layer comprises one or more layers of graphene. Original
A semiconductor interconnect structure, comprising: a substrate; a conductive interconnect layer on the substrate; a patterned dielectric layer over the substrate and over a portion of the conductive interconnect layer, the patterned dielectric layer comprising a pair of opposing sidewall surfaces; a first conductive layer on the conductive interconnect layer; a graphene layer formed on the first conductive layer and on the pair of opposing sidewall surfaces of the patterned dielectric layer; and a second conductive layer formed on the graphene layer, wherein at least a portion of the second conductive layer is between the pair of opposing sidewall surfaces of the patterned dielectric la y er. Currently amended
The semiconductor interconnect structure of claim 16, wherein the graphene layer has a thickness in a range of about 1 angstrom to about 300 angstroms. Original
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers are formed in a via and a trench, respectively. Original
The semiconductor interconnect structure of claim 16, wherein the patterned dielectric layer further comprises a top surface, and the least one portion of the second conductive layer is formed below the top surface of the patterned dielectric layer. Currently amended
The semiconductor interconnect structure of claim 16, wherein the first and second conductive layers comprise different materials. Original
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor interconnect structure with graphene barrier layer (claim 1)
Materials described outside the worked examples.
graphene barrier layer
first conductive layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 50–2000 Å | — |
Thickness | 10–5000 Å |
Related documents with shared materials, methods, properties, or citations.
semiconductor interconnect structure with graphene barrier layer (claim 11)
semiconductor interconnect structure with graphene layer (claim 16)
second conductive layer
silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof
amorphous carbon
copper
Cu
titanium nitride
TiN
tantalum nitride
TaN
tungsten
W
| — |
Thickness | 20–5000 Å | — |
Thickness | 100–2000 Å | — |
Thickness | 1–300 Å | — |
Temperature | 200–1250 °C | — |
Temperature | 200–450 °C | — |
Temperature | 250–1250 °C | — |
Temperature | 250–450 °C | — |
Thickness | ≤ 10 Å | — |
semiconductor interconnect structure with graphene barrier layer (claim 11)
semiconductor interconnect structure with graphene layer (claim 16)
second conductive layer
silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof
amorphous carbon
copper
Cu
titanium nitride
TiN
tantalum nitride
TaN
tungsten
W
| — |
Thickness | 20–5000 Å | — |
Thickness | 100–2000 Å | — |
Thickness | 1–300 Å | — |
Temperature | 200–1250 °C | — |
Temperature | 200–450 °C | — |
Temperature | 250–1250 °C | — |
Temperature | 250–450 °C | — |
Thickness | ≤ 10 Å | — |
semiconductor interconnect structure with graphene barrier layer (claim 11)
semiconductor interconnect structure with graphene layer (claim 16)
second conductive layer
silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof
amorphous carbon
copper
Cu
titanium nitride
TiN
tantalum nitride
TaN
tungsten
W
| — |
Thickness | 20–5000 Å | — |
Thickness | 100–2000 Å | — |
Thickness | 1–300 Å | — |
Temperature | 200–1250 °C | — |
Temperature | 200–450 °C | — |
Temperature | 250–1250 °C | — |
Temperature | 250–450 °C | — |
Thickness | ≤ 10 Å | — |
semiconductor interconnect structure with graphene barrier layer (claim 11)
semiconductor interconnect structure with graphene layer (claim 16)
second conductive layer
silver, aluminum, gold, copper, ruthenium, cobalt, nickel, tungsten, manganese, molybdenum, cobalt tungsten, cobalt tungsten phosphorous, or an alloy thereof
amorphous carbon
copper
Cu
titanium nitride
TiN
tantalum nitride
TaN
tungsten
W
| — |
Thickness | 20–5000 Å | — |
Thickness | 100–2000 Å | — |
Thickness | 1–300 Å | — |
Temperature | 200–1250 °C | — |
Temperature | 200–450 °C | — |
Temperature | 250–1250 °C | — |
Temperature | 250–450 °C | — |
Thickness | ≤ 10 Å | — |