Patent
US 8,759,824SEMICONDUCTOR STRUCTURE AND CIRCUIT INCLUDING ORDERED ARRANGEMENT OF GRAPHENE NANORIBBONS, AND METHODS OF FORMING SAME
Christos D. Dimitrakopoulos
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an initial structure including a substrate and an overlying graphene layer …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the initial structure of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 6 is a pictorial representation (through a top down view) illustrating the structure whose cross sectional view is shown in
FIG. 7 is a pictorial representation (through a top down view) illustrating the structure of
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
FIG. 9 is a pictorial representation (through a top down view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising-a substrate having an upper surface; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of the upper surface of the substrate; and a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 2 I \IBM\ 105\ 27134A\AMEND \ 27134A am l doc
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 n m.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene. 3 I \IBM\105\27134A\AMEND\27134A a m1 doc
A semiconductor circuit comprising: a substrate; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of an upper surface of the substrate; at least one semiconductor device formed on the first set of said ordered array of parallel graphene nanoribbons; a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate; and at least one second semiconductor device formed on the second set of said ordered array of parallel graphene nanoribbons, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor circuit of Claim 9 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 4 I \IB M\1 05\27134A\AMEND\27134A am l do c 11 The semiconductor circuit of Claim 9 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons comprises a single-layer of graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor circuit of Claim 9 wherein said semiconductor device is a field effect transistor 15.-20.
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with ordered array of parallel graphene nanoribbons
semiconductor circuit with ordered arrays of parallel graphene nanoribbons and semiconductor devices
field effect transistor on graphene nanoribbons
Materials described outside the worked examples.
graphene nanoribbon
glass
silicon dioxide
SiO₂
silicon nitride
SiN
organosilicate glass
SiC:H
SiCN:H
plastic
diamond-like carbon
boron nitride
BN
carbon boron nitride
CxBN
silicon
Si
silicon germanium
SiGe
silicon germanium carbon
SiGeC
silicon carbide
SiC
germanium alloys
gallium arsenide
GaAs
indium arsenide
InAs
indium phosphide
InP
single-layer graphene
few-layer graphene
multi-layer graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.34–10 nm | — |
Thickness | 0.34–3.4 nm | — |
Thickness | 0.34–1.1 nm | — |
Thickness | 500–5000 nm | — |
Thickness | 3–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 30 nm | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an initial structure including a substrate and an overlying graphene layer …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the initial structure of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 6 is a pictorial representation (through a top down view) illustrating the structure whose cross sectional view is shown in
FIG. 7 is a pictorial representation (through a top down view) illustrating the structure of
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
FIG. 9 is a pictorial representation (through a top down view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising-a substrate having an upper surface; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of the upper surface of the substrate; and a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 2 I \IBM\ 105\ 27134A\AMEND \ 27134A am l doc
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 n m.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene. 3 I \IBM\105\27134A\AMEND\27134A a m1 doc
A semiconductor circuit comprising: a substrate; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of an upper surface of the substrate; at least one semiconductor device formed on the first set of said ordered array of parallel graphene nanoribbons; a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate; and at least one second semiconductor device formed on the second set of said ordered array of parallel graphene nanoribbons, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor circuit of Claim 9 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 4 I \IB M\1 05\27134A\AMEND\27134A am l do c 11 The semiconductor circuit of Claim 9 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons comprises a single-layer of graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor circuit of Claim 9 wherein said semiconductor device is a field effect transistor 15.-20.
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with ordered array of parallel graphene nanoribbons
semiconductor circuit with ordered arrays of parallel graphene nanoribbons and semiconductor devices
field effect transistor on graphene nanoribbons
Materials described outside the worked examples.
graphene nanoribbon
glass
silicon dioxide
SiO₂
silicon nitride
SiN
organosilicate glass
SiC:H
SiCN:H
plastic
diamond-like carbon
boron nitride
BN
carbon boron nitride
CxBN
silicon
Si
silicon germanium
SiGe
silicon germanium carbon
SiGeC
silicon carbide
SiC
germanium alloys
gallium arsenide
GaAs
indium arsenide
InAs
indium phosphide
InP
single-layer graphene
few-layer graphene
multi-layer graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.34–10 nm | — |
Thickness | 0.34–3.4 nm | — |
Thickness | 0.34–1.1 nm | — |
Thickness | 500–5000 nm | — |
Thickness | 3–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 30 nm | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an initial structure including a substrate and an overlying graphene layer …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the initial structure of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 6 is a pictorial representation (through a top down view) illustrating the structure whose cross sectional view is shown in
FIG. 7 is a pictorial representation (through a top down view) illustrating the structure of
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
FIG. 9 is a pictorial representation (through a top down view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising-a substrate having an upper surface; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of the upper surface of the substrate; and a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 2 I \IBM\ 105\ 27134A\AMEND \ 27134A am l doc
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 n m.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene. 3 I \IBM\105\27134A\AMEND\27134A a m1 doc
A semiconductor circuit comprising: a substrate; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of an upper surface of the substrate; at least one semiconductor device formed on the first set of said ordered array of parallel graphene nanoribbons; a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate; and at least one second semiconductor device formed on the second set of said ordered array of parallel graphene nanoribbons, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor circuit of Claim 9 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 4 I \IB M\1 05\27134A\AMEND\27134A am l do c 11 The semiconductor circuit of Claim 9 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons comprises a single-layer of graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor circuit of Claim 9 wherein said semiconductor device is a field effect transistor 15.-20.
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with ordered array of parallel graphene nanoribbons
semiconductor circuit with ordered arrays of parallel graphene nanoribbons and semiconductor devices
field effect transistor on graphene nanoribbons
Materials described outside the worked examples.
graphene nanoribbon
glass
silicon dioxide
SiO₂
silicon nitride
SiN
organosilicate glass
SiC:H
SiCN:H
plastic
diamond-like carbon
boron nitride
BN
carbon boron nitride
CxBN
silicon
Si
silicon germanium
SiGe
silicon germanium carbon
SiGeC
silicon carbide
SiC
germanium alloys
gallium arsenide
GaAs
indium arsenide
InAs
indium phosphide
InP
single-layer graphene
few-layer graphene
multi-layer graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.34–10 nm | — |
Thickness | 0.34–3.4 nm | — |
Thickness | 0.34–1.1 nm | — |
Thickness | 500–5000 nm | — |
Thickness | 3–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 30 nm | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a pictorial representation (through a cross sectional view) illustrating an initial structure including a substrate and an overlying graphene layer …
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the initial structure of
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 5 is a pictorial representation (through a cross sectional view) illustrating the structure of
FIG. 6 is a pictorial representation (through a top down view) illustrating the structure whose cross sectional view is shown in
FIG. 7 is a pictorial representation (through a top down view) illustrating the structure of
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
FIG. 9 is a pictorial representation (through a top down view) illustrating the structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising-a substrate having an upper surface; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of the upper surface of the substrate; and a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor structure of Claim 1 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 2 I \IBM\ 105\ 27134A\AMEND \ 27134A am l doc
The semiconductor structure of Claim 1 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons has a width from 1 nm to 30 n m.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor structure of Claim 1 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is comprised of single-layer graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene. 3 I \IBM\105\27134A\AMEND\27134A a m1 doc
A semiconductor circuit comprising: a substrate; a first set of an ordered array of parallel graphene nanoribbons located on a first portion of an upper surface of the substrate; at least one semiconductor device formed on the first set of said ordered array of parallel graphene nanoribbons; a second set of an ordered array of parallel graphene nanoribbons located on a second portion of the upper surface of the substrate; and at least one second semiconductor device formed on the second set of said ordered array of parallel graphene nanoribbons, wherein a gap oriented perpendicular to each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons separates said first set of said ordered array of parallel graphene nanoribbons from said second set of said ordered array of parallel graphene nanoribbons, and wherein each graphene nanoribbon of said first set of said ordered array of parallel graphene nanoribbons is aligned with a corresponding graphene nanoribbon of said second set of said ordered array of parallel graphene nanoribbons.
The semiconductor circuit of Claim 9 wherein said substrate is a dielectric material, and said dielectric material comprises glass, Si O 2, SiN, organosilicate glass, SC:H, SiCN:H, plastic, diamond-like carbon, boron nitride (BN), carbon boron nitride (C X BN) and a mixture of amorphous/hexagonal bonding boron nitride or carbon boron nitride. 4 I \IB M\1 05\27134A\AMEND\27134A am l do c 11 The semiconductor circuit of Claim 9 wherein said substrate is a semiconductor material, and said semiconductor material comprises Si, Si G e, SiGeC, SiC, Ge alloys, GaAs, InAs, or InP.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons is separated by a uniform width.
The semiconductor circuit of Claim 9 wherein each graphene nanoribbon of said first and second sets of said ordered array of parallel graphene nanoribbons comprises a single-layer of graphene, few-layer graphene, multi-layer graphene, a mixture of single-layer, few-layer, and multi-layer graphene.
The semiconductor circuit of Claim 9 wherein said semiconductor device is a field effect transistor 15.-20.
canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with ordered array of parallel graphene nanoribbons
semiconductor circuit with ordered arrays of parallel graphene nanoribbons and semiconductor devices
field effect transistor on graphene nanoribbons
Materials described outside the worked examples.
graphene nanoribbon
glass
silicon dioxide
SiO₂
silicon nitride
SiN
organosilicate glass
SiC:H
SiCN:H
plastic
diamond-like carbon
boron nitride
BN
carbon boron nitride
CxBN
silicon
Si
silicon germanium
SiGe
silicon germanium carbon
SiGeC
silicon carbide
SiC
germanium alloys
gallium arsenide
GaAs
indium arsenide
InAs
indium phosphide
InP
single-layer graphene
few-layer graphene
multi-layer graphene
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 after forming a field effect transistor (FET) in on the ordered array of parallel graphene nanoribbons.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.34–10 nm | — |
Thickness | 0.34–3.4 nm | — |
Thickness | 0.34–1.1 nm | — |
Thickness | 500–5000 nm | — |
Thickness | 3–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 1–30 nm | — |
Thickness | 1–10 nm | — |
Thickness | 1–20 nm | — |
Thickness | 2–10 nm | — |
Thickness | 1–100 nm | — |
Thickness | 3–30 nm | — |
Thickness | ≤ 1 nm | — |
Thickness | ≤ 30 nm | — |