Patent
US 9,276,529A HIGH PERFORMANCE GaN OPERATIONAL AMPLIFIER WITH WIDE BANDWIDTH AND HIGH DYNAMIC RANGE
David F. Brown
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,276,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An operational amplifier comprising: a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; 15 a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors. 16
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; and the Schottky diodes comprise GaN Schottky diodes.
The operational amplifier of claim 1 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The operational amplifier of claim 1 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz. 17
The operational amplifier of claim 1 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes.
The operational amplifier of claim 1 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a source connected to a third current source, and a drain coupled to the second current source.
A method of providing an operational amplifier comprising: providing a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; 19 providing a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and providing a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; providing a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; providing a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; providing a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; providing a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; providing a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and 20 providing a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; and the Schottky diodes comprise G aN Schottky diodes. 21
The method of claim 12 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The method of claim 12 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz.
The method of claim 12 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a 22 source connected to a third current source, and a drain coupled to the second current source.
The method of claim 12 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes. 24
The method of claim 22 wherein each respective differential output amplifier comprises: a fifth field effect transistor having a gate coupled to the second Schottky diode, a source connected to a fourth current source, and a drain coupled to the ground; a sixth field effect transistor having a gate coupled to the fourth Schottky diode, a source connected to a fifth current source, and a drain coupled to the ground; 23 a first capacitor coupled between the gate and the source of the fifth field effect transistor; and a second capacitor coupled between the gate and the source of the sixth field effect transistor; wherein the source of the fifth field effect transistor is coupled to the negative output of the respective differential output amplifier; and wherein the source of the sixth field effect transistor is coupled to the positive output of the respective differential output amplifier.
Layer stacks claimed or described, ordered top of device to substrate.
GaN operational amplifier
Materials described outside the worked examples.
Schottky diode
GaN MMIC
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
fT of GaN HEMT | ≥ 250 | GaN HEMT field effect transistor |
fmax of GaN HEMT | ≥ 300 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,276,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An operational amplifier comprising: a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; 15 a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors. 16
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; and the Schottky diodes comprise GaN Schottky diodes.
The operational amplifier of claim 1 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The operational amplifier of claim 1 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz. 17
The operational amplifier of claim 1 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes.
The operational amplifier of claim 1 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a source connected to a third current source, and a drain coupled to the second current source.
A method of providing an operational amplifier comprising: providing a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; 19 providing a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and providing a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; providing a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; providing a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; providing a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; providing a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; providing a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and 20 providing a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; and the Schottky diodes comprise G aN Schottky diodes. 21
The method of claim 12 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The method of claim 12 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz.
The method of claim 12 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a 22 source connected to a third current source, and a drain coupled to the second current source.
The method of claim 12 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes. 24
The method of claim 22 wherein each respective differential output amplifier comprises: a fifth field effect transistor having a gate coupled to the second Schottky diode, a source connected to a fourth current source, and a drain coupled to the ground; a sixth field effect transistor having a gate coupled to the fourth Schottky diode, a source connected to a fifth current source, and a drain coupled to the ground; 23 a first capacitor coupled between the gate and the source of the fifth field effect transistor; and a second capacitor coupled between the gate and the source of the sixth field effect transistor; wherein the source of the fifth field effect transistor is coupled to the negative output of the respective differential output amplifier; and wherein the source of the sixth field effect transistor is coupled to the positive output of the respective differential output amplifier.
Layer stacks claimed or described, ordered top of device to substrate.
GaN operational amplifier
Materials described outside the worked examples.
Schottky diode
GaN MMIC
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
fT of GaN HEMT | ≥ 250 | GaN HEMT field effect transistor |
fmax of GaN HEMT | ≥ 300 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,276,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An operational amplifier comprising: a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; 15 a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors. 16
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; and the Schottky diodes comprise GaN Schottky diodes.
The operational amplifier of claim 1 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The operational amplifier of claim 1 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz. 17
The operational amplifier of claim 1 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes.
The operational amplifier of claim 1 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a source connected to a third current source, and a drain coupled to the second current source.
A method of providing an operational amplifier comprising: providing a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; 19 providing a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and providing a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; providing a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; providing a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; providing a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; providing a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; providing a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and 20 providing a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; and the Schottky diodes comprise G aN Schottky diodes. 21
The method of claim 12 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The method of claim 12 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz.
The method of claim 12 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a 22 source connected to a third current source, and a drain coupled to the second current source.
The method of claim 12 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes. 24
The method of claim 22 wherein each respective differential output amplifier comprises: a fifth field effect transistor having a gate coupled to the second Schottky diode, a source connected to a fourth current source, and a drain coupled to the ground; a sixth field effect transistor having a gate coupled to the fourth Schottky diode, a source connected to a fifth current source, and a drain coupled to the ground; 23 a first capacitor coupled between the gate and the source of the fifth field effect transistor; and a second capacitor coupled between the gate and the source of the sixth field effect transistor; wherein the source of the fifth field effect transistor is coupled to the negative output of the respective differential output amplifier; and wherein the source of the sixth field effect transistor is coupled to the positive output of the respective differential output amplifier.
Layer stacks claimed or described, ordered top of device to substrate.
GaN operational amplifier
Materials described outside the worked examples.
Schottky diode
GaN MMIC
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
fT of GaN HEMT | ≥ 250 | GaN HEMT field effect transistor |
fmax of GaN HEMT | ≥ 300 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,276,529Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An operational amplifier comprising: a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; 15 a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors. 16
The operational amplifier of claim 1 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises GaN HEMT field effect transistors; and the Schottky diodes comprise GaN Schottky diodes.
The operational amplifier of claim 1 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The operational amplifier of claim 1 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz. 17
The operational amplifier of claim 1 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes.
The operational amplifier of claim 1 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a source connected to a third current source, and a drain coupled to the second current source.
A method of providing an operational amplifier comprising: providing a first transconductance stage having a first differential input and a first differential output, the first differential input having a positive and negative input, and the first differential output having a positive and negative output; 19 providing a second transconductance stage having a second differential input and a second differential output, the second differential input having a positive and negative input, and the second differential output having a positive and negative output; and providing a third transconductance stage having a third differential input and a third differential output, the third differential input having a positive and negative input, and the third differential output having a positive and negative output; wherein the positive and negative output of the first differential output are coupled to the positive and negative input, respectively, of the second differential input; and wherein the positive and negative output of the second differential output are coupled to the positive and negative input, respectively, of the third differential input; providing a first resistor coupled between the negative output of the first differential output and the positive input of the first differential input; providing a second resistor coupled between the positive output of the first differential output and the negative input of the first differential input; providing a third resistor coupled between the negative output of the third differential output and the positive input of the first differential input; providing a fourth resistor coupled between the positive output of the third differential output and the negative input of the first differential input; providing a first capacitor coupled between the positive output of the third differential output and the negative input of the third differential input; and 20 providing a second capacitor coupled between the negative output of the third differential output and the positive input of the third differential input; wherein the first, second, and third transconductance stages each comprise: a differential input amplifier coupled to the differential input of the respective transconductance stage; a differential output amplifier coupled to the differential output of the respective transconductance stage; and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for shifting a voltage level of the differential input amplifier.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors; and the differential output amplifier of the first, second, and third transconductance stages comprises depletion mode field effect transistors.
The method of claim 12 wherein: the differential input amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; the differential output amplifier of the first, second, and third transconductance stages comprises G aN HEMT field effect transistors; and the Schottky diodes comprise G aN Schottky diodes. 21
The method of claim 12 wherein: a frequency bandwidth of the operational amplifier is greater than 6 G hz; a voltage gain of the operational amplifier is greater than 20 dB; and a linearity figure of merit (L F oM) of the operational amplifier is greater than 100.
The method of claim 12 wherein: a noise figure of the operational amplifier is 6 dB at 4 G Hz.
The method of claim 12 wherein each respective differential input amplifier comprises: a first field effect transistor having a gate coupled to the positive input of the respective differential input, a source connected to a first current source, and a drain coupled to a second current source, the second current source coupled to a ground; and a second field effect transistor having a gate coupled to the negative input of the respective differential input a 22 source connected to a third current source, and a drain coupled to the second current source.
The method of claim 12 wherein: the Schottky diodes comprise monolithically integrated lateral GaN Schottky diodes. 24
The method of claim 22 wherein each respective differential output amplifier comprises: a fifth field effect transistor having a gate coupled to the second Schottky diode, a source connected to a fourth current source, and a drain coupled to the ground; a sixth field effect transistor having a gate coupled to the fourth Schottky diode, a source connected to a fifth current source, and a drain coupled to the ground; 23 a first capacitor coupled between the gate and the source of the fifth field effect transistor; and a second capacitor coupled between the gate and the source of the sixth field effect transistor; wherein the source of the fifth field effect transistor is coupled to the negative output of the respective differential output amplifier; and wherein the source of the sixth field effect transistor is coupled to the positive output of the respective differential output amplifier.
Layer stacks claimed or described, ordered top of device to substrate.
GaN operational amplifier
Materials described outside the worked examples.
Schottky diode
GaN MMIC
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
fT of GaN HEMT | ≥ 250 | GaN HEMT field effect transistor |
fmax of GaN HEMT | ≥ 300 |
Related documents with shared materials, methods, properties, or citations.
GaN HEMT field effect transistor
GaN Schottky diode
monolithically integrated lateral GaN Schottky diode
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
BV of GaN HEMT | ≥ 10 | GaN HEMT field effect transistor |
on-resistance of GaN Schottky diode | ≤ 1 | GaN Schottky diode |
blocking voltage of GaN Schottky diode | ≥ 10 | GaN Schottky diode |
current-handling capability of GaN Schottky diode | ≥ 0.5 | GaN Schottky diode |
frequency bandwidth of operational amplifier | ≥ 6 | — |
voltage gain of operational amplifier | ≥ 20 | — |
linearity figure of merit (LFoM) of operational amplifier | ≥ 100 | — |
noise figure of operational amplifier at 4 GHz | 6 | — |
fT of GaN MMIC device (described embodiment) | 342 | GaN HEMT field effect transistor |
fmax of GaN MMIC device (described embodiment) | 518 | GaN HEMT field effect transistor |
NFmin of GaN device at 50 GHz | 0.8 | GaN HEMT field effect transistor |
NFmin of GaN 2x25um device at 50 GHz with Vds=0.6V and DC power=6mW | 1.1 | GaN HEMT field effect transistor |
Voltage | ≥ 10 V | — |
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
GaN HEMT field effect transistor
GaN Schottky diode
monolithically integrated lateral GaN Schottky diode
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
BV of GaN HEMT | ≥ 10 | GaN HEMT field effect transistor |
on-resistance of GaN Schottky diode | ≤ 1 | GaN Schottky diode |
blocking voltage of GaN Schottky diode | ≥ 10 | GaN Schottky diode |
current-handling capability of GaN Schottky diode | ≥ 0.5 | GaN Schottky diode |
frequency bandwidth of operational amplifier | ≥ 6 | — |
voltage gain of operational amplifier | ≥ 20 | — |
linearity figure of merit (LFoM) of operational amplifier | ≥ 100 | — |
noise figure of operational amplifier at 4 GHz | 6 | — |
fT of GaN MMIC device (described embodiment) | 342 | GaN HEMT field effect transistor |
fmax of GaN MMIC device (described embodiment) | 518 | GaN HEMT field effect transistor |
NFmin of GaN device at 50 GHz | 0.8 | GaN HEMT field effect transistor |
NFmin of GaN 2x25um device at 50 GHz with Vds=0.6V and DC power=6mW | 1.1 | GaN HEMT field effect transistor |
Voltage | ≥ 10 V | — |
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
GaN HEMT field effect transistor
GaN Schottky diode
monolithically integrated lateral GaN Schottky diode
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
BV of GaN HEMT | ≥ 10 | GaN HEMT field effect transistor |
on-resistance of GaN Schottky diode | ≤ 1 | GaN Schottky diode |
blocking voltage of GaN Schottky diode | ≥ 10 | GaN Schottky diode |
current-handling capability of GaN Schottky diode | ≥ 0.5 | GaN Schottky diode |
frequency bandwidth of operational amplifier | ≥ 6 | — |
voltage gain of operational amplifier | ≥ 20 | — |
linearity figure of merit (LFoM) of operational amplifier | ≥ 100 | — |
noise figure of operational amplifier at 4 GHz | 6 | — |
fT of GaN MMIC device (described embodiment) | 342 | GaN HEMT field effect transistor |
fmax of GaN MMIC device (described embodiment) | 518 | GaN HEMT field effect transistor |
NFmin of GaN device at 50 GHz | 0.8 | GaN HEMT field effect transistor |
NFmin of GaN 2x25um device at 50 GHz with Vds=0.6V and DC power=6mW | 1.1 | GaN HEMT field effect transistor |
Voltage | ≥ 10 V | — |
GAN DRIVER USING ACTIVE PRE-DRIVER WITH FEEDBACK
GaN HEMT field effect transistor
GaN Schottky diode
monolithically integrated lateral GaN Schottky diode
FIG. 1A, a feature that InP HEMTs and conventional un- scaled GaN HEMTs do not provide. Third-order distortion has been shown to be inversely proportional to …
FIG. 2 C shows the corresponding current- voltage (IV) characteristic for the monolithically integrated lateral Schottky diode in accordance with the present …
FIG. 3B shows a cross section scanning electron microscope (SEM) 5 image of a 3- level metal layer/benzocyclobutene (B CB) interconnect technology, and
FIG. 4B shows an operational amplifier circuit utilizing three transconductance stages, each stage using the two stage amplifier of
BV of GaN HEMT | ≥ 10 | GaN HEMT field effect transistor |
on-resistance of GaN Schottky diode | ≤ 1 | GaN Schottky diode |
blocking voltage of GaN Schottky diode | ≥ 10 | GaN Schottky diode |
current-handling capability of GaN Schottky diode | ≥ 0.5 | GaN Schottky diode |
frequency bandwidth of operational amplifier | ≥ 6 | — |
voltage gain of operational amplifier | ≥ 20 | — |
linearity figure of merit (LFoM) of operational amplifier | ≥ 100 | — |
noise figure of operational amplifier at 4 GHz | 6 | — |
fT of GaN MMIC device (described embodiment) | 342 | GaN HEMT field effect transistor |
fmax of GaN MMIC device (described embodiment) | 518 | GaN HEMT field effect transistor |
NFmin of GaN device at 50 GHz | 0.8 | GaN HEMT field effect transistor |
NFmin of GaN 2x25um device at 50 GHz with Vds=0.6V and DC power=6mW | 1.1 | GaN HEMT field effect transistor |
Voltage | ≥ 10 V | — |